DE60336787D1 - Halbleiterspeicher - Google Patents
HalbleiterspeicherInfo
- Publication number
- DE60336787D1 DE60336787D1 DE60336787T DE60336787T DE60336787D1 DE 60336787 D1 DE60336787 D1 DE 60336787D1 DE 60336787 T DE60336787 T DE 60336787T DE 60336787 T DE60336787 T DE 60336787T DE 60336787 D1 DE60336787 D1 DE 60336787D1
- Authority
- DE
- Germany
- Prior art keywords
- semiconductor memory
- semiconductor
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/103—Read-write modes for single port memories, i.e. having either a random port or a serial port using serially addressed read-write data registers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/002—Isolation gates, i.e. gates coupling bit lines to the sense amplifier
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2002251850A JP4246977B2 (ja) | 2002-08-29 | 2002-08-29 | 半導体メモリ |
Publications (1)
Publication Number | Publication Date |
---|---|
DE60336787D1 true DE60336787D1 (de) | 2011-06-01 |
Family
ID=31884695
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE60336787T Expired - Lifetime DE60336787D1 (de) | 2002-08-29 | 2003-03-10 | Halbleiterspeicher |
Country Status (7)
Country | Link |
---|---|
US (1) | US6963518B2 (de) |
EP (2) | EP2166540B1 (de) |
JP (1) | JP4246977B2 (de) |
KR (1) | KR100942739B1 (de) |
CN (1) | CN100338774C (de) |
DE (1) | DE60336787D1 (de) |
TW (1) | TWI254939B (de) |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7130233B2 (en) * | 2003-03-21 | 2006-10-31 | Mediatek Incorporation | Sensing circuit for single bit-line semiconductor memory device |
EP1624573B1 (de) * | 2003-05-14 | 2018-04-04 | Fujitsu Limited | Verfahren zur stabilisierung des betriebs einer elektronischen schaltung und ihre elektronische einrichtung |
JP4511462B2 (ja) * | 2003-06-30 | 2010-07-28 | 富士通セミコンダクター株式会社 | 半導体記憶装置 |
WO2005045846A1 (ja) * | 2003-11-06 | 2005-05-19 | International Business Machines Corporation | 半導体記憶装置及びそのバースト動作方法 |
KR100525107B1 (ko) * | 2004-02-06 | 2005-11-01 | 주식회사 하이닉스반도체 | 메모리 장치의 동작 주파수 변동에 따라 비트라인 감지증폭기와 데이타 감지 증폭기를 연결하는 데이타 버스의동작을 제어하는 신호의 인에이블 구간을 제어하는 방법과그 장치 |
KR100608365B1 (ko) * | 2004-05-17 | 2006-08-08 | 주식회사 하이닉스반도체 | 메모리 장치의 내부 제어 신호를 측정하는 방법 및 장치 |
US7319612B2 (en) * | 2005-05-18 | 2008-01-15 | Intel Corporation | Performing multiple read operations via a single read command |
JP4850578B2 (ja) * | 2006-05-19 | 2012-01-11 | 富士通セミコンダクター株式会社 | 半導体記憶装置及びリフレッシュ周期制御方法 |
KR100909805B1 (ko) * | 2006-09-21 | 2009-07-29 | 주식회사 하이닉스반도체 | 멀티포트 메모리 장치 |
US7995410B2 (en) * | 2009-06-26 | 2011-08-09 | Apple Inc. | Leakage and NBTI reduction technique for memory |
KR102223007B1 (ko) | 2014-07-28 | 2021-03-04 | 삼성전자주식회사 | 반도체 메모리 장치, 이의 리프레쉬 방법 및 반도체 메모리 장치의 리프레쉬 카운터 |
US10127979B2 (en) | 2016-03-11 | 2018-11-13 | Western Digital Technologies, Inc. | Memory cell located pulse generator |
US10381408B2 (en) | 2016-03-24 | 2019-08-13 | Western Digital Technologies, Inc. | Method to fabricate discrete vertical transistors |
KR20180058478A (ko) * | 2016-11-24 | 2018-06-01 | 에스케이하이닉스 주식회사 | 반도체 장치, 이를 포함하는 반도체 시스템 및 반도체 장치의 리드 및 라이트 동작 방법 |
KR102504614B1 (ko) * | 2018-04-27 | 2023-03-02 | 에스케이하이닉스 주식회사 | 반도체 장치 |
KR102653251B1 (ko) * | 2018-09-07 | 2024-04-01 | 에스케이하이닉스 주식회사 | 고속 데이터 리드아웃 장치 및 그를 이용한 씨모스 이미지 센서 |
US11561603B2 (en) * | 2018-12-20 | 2023-01-24 | Micron Technology, Inc. | Memory device low power mode |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4961172A (en) * | 1988-08-11 | 1990-10-02 | Waferscale Integration, Inc. | Decoder for a memory address bus |
JP3344494B2 (ja) * | 1993-03-23 | 2002-11-11 | インターナショナル・ビジネス・マシーンズ・コーポレーション | ページモードを有するシングルクロックメモリ |
JPH08315567A (ja) * | 1995-05-22 | 1996-11-29 | Mitsubishi Electric Corp | 半導体記憶装置 |
KR100218734B1 (ko) * | 1996-05-06 | 1999-09-01 | 김영환 | 싱크로노스 메모리의 내부펄스 신호발생 방법 및 그장치 |
US5970022A (en) * | 1997-03-21 | 1999-10-19 | Winbond Electronics Corporation | Semiconductor memory device with reduced read disturbance |
US6172935B1 (en) | 1997-04-25 | 2001-01-09 | Micron Technology, Inc. | Synchronous dynamic random access memory device |
KR100278923B1 (ko) * | 1997-12-31 | 2001-02-01 | 김영환 | 초고속 순차 컬럼 디코더 |
JP2000048565A (ja) * | 1998-07-29 | 2000-02-18 | Mitsubishi Electric Corp | 同期型半導体記憶装置 |
JP2000163965A (ja) * | 1998-11-27 | 2000-06-16 | Mitsubishi Electric Corp | 同期型半導体記憶装置 |
JP4748828B2 (ja) * | 1999-06-22 | 2011-08-17 | ルネサスエレクトロニクス株式会社 | 半導体記憶装置 |
JP4531892B2 (ja) * | 1999-10-29 | 2010-08-25 | 富士通セミコンダクター株式会社 | 半導体集積回路、半導体集積回路の制御方法、および可変遅延回路 |
JP2002025272A (ja) * | 2000-07-10 | 2002-01-25 | Sharp Corp | 半導体記憶装置およびその評価方法 |
US6229735B1 (en) * | 2000-08-11 | 2001-05-08 | Advanced Micro Devices, Inc. | Burst read mode word line boosting |
JP2002093159A (ja) * | 2000-09-08 | 2002-03-29 | Mitsubishi Electric Corp | 半導体記憶装置 |
JP2003157699A (ja) * | 2001-11-20 | 2003-05-30 | Oki Electric Ind Co Ltd | 半導体記憶装置 |
-
2002
- 2002-08-29 JP JP2002251850A patent/JP4246977B2/ja not_active Expired - Fee Related
-
2003
- 2003-03-10 EP EP09169013.1A patent/EP2166540B1/de not_active Expired - Fee Related
- 2003-03-10 EP EP03005253A patent/EP1398785B1/de not_active Expired - Fee Related
- 2003-03-10 DE DE60336787T patent/DE60336787D1/de not_active Expired - Lifetime
- 2003-03-13 TW TW092105506A patent/TWI254939B/zh not_active IP Right Cessation
- 2003-03-14 US US10/387,398 patent/US6963518B2/en not_active Expired - Lifetime
- 2003-03-31 KR KR1020030020257A patent/KR100942739B1/ko active IP Right Grant
- 2003-03-31 CN CNB031084338A patent/CN100338774C/zh not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP4246977B2 (ja) | 2009-04-02 |
EP1398785A3 (de) | 2005-02-09 |
EP2166540A1 (de) | 2010-03-24 |
KR20040019859A (ko) | 2004-03-06 |
TWI254939B (en) | 2006-05-11 |
JP2004095002A (ja) | 2004-03-25 |
TW200403679A (en) | 2004-03-01 |
KR100942739B1 (ko) | 2010-02-17 |
EP2166540B1 (de) | 2013-07-17 |
EP1398785B1 (de) | 2011-04-20 |
EP1398785A2 (de) | 2004-03-17 |
US6963518B2 (en) | 2005-11-08 |
CN1479378A (zh) | 2004-03-03 |
CN100338774C (zh) | 2007-09-19 |
US20040042334A1 (en) | 2004-03-04 |
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