DE60314068D1 - Nichtflüchtiger Halbleiterspeicher - Google Patents

Nichtflüchtiger Halbleiterspeicher

Info

Publication number
DE60314068D1
DE60314068D1 DE60314068T DE60314068T DE60314068D1 DE 60314068 D1 DE60314068 D1 DE 60314068D1 DE 60314068 T DE60314068 T DE 60314068T DE 60314068 T DE60314068 T DE 60314068T DE 60314068 D1 DE60314068 D1 DE 60314068D1
Authority
DE
Germany
Prior art keywords
semiconductor memory
volatile semiconductor
volatile
memory
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60314068T
Other languages
English (en)
Other versions
DE60314068T2 (de
Inventor
Tomoharu Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE60314068D1 publication Critical patent/DE60314068D1/de
Publication of DE60314068T2 publication Critical patent/DE60314068T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G11C11/5635—Erasing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642—Sensing or reading circuits; Data output circuits
DE60314068T 2002-09-26 2003-02-28 Nichtflüchtiger Halbleiterspeicher Expired - Lifetime DE60314068T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2002281205 2002-09-26
JP2002281205A JP4270832B2 (ja) 2002-09-26 2002-09-26 不揮発性半導体メモリ

Publications (2)

Publication Number Publication Date
DE60314068D1 true DE60314068D1 (de) 2007-07-12
DE60314068T2 DE60314068T2 (de) 2008-01-24

Family

ID=31973305

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60314068T Expired - Lifetime DE60314068T2 (de) 2002-09-26 2003-02-28 Nichtflüchtiger Halbleiterspeicher

Country Status (7)

Country Link
US (2) US6850435B2 (de)
EP (1) EP1403877B1 (de)
JP (1) JP4270832B2 (de)
KR (1) KR100515867B1 (de)
CN (1) CN1295794C (de)
DE (1) DE60314068T2 (de)
TW (1) TWI247427B (de)

Families Citing this family (51)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3631463B2 (ja) 2001-12-27 2005-03-23 株式会社東芝 不揮発性半導体記憶装置
JP3977799B2 (ja) * 2003-12-09 2007-09-19 株式会社東芝 不揮発性半導体記憶装置
TWI292914B (de) * 2002-01-17 2008-01-21 Macronix Int Co Ltd
JP3935139B2 (ja) * 2002-11-29 2007-06-20 株式会社東芝 半導体記憶装置
US6657891B1 (en) 2002-11-29 2003-12-02 Kabushiki Kaisha Toshiba Semiconductor memory device for storing multivalued data
US7392436B2 (en) * 2003-05-08 2008-06-24 Micron Technology, Inc. Program failure recovery
JP4170952B2 (ja) 2004-01-30 2008-10-22 株式会社東芝 半導体記憶装置
JP4504138B2 (ja) * 2004-09-03 2010-07-14 株式会社東芝 記憶システム及びそのデータコピー方法
JP4417813B2 (ja) * 2004-10-01 2010-02-17 株式会社東芝 半導体記憶装置及びメモリカード
JP4786171B2 (ja) 2004-12-10 2011-10-05 株式会社東芝 半導体記憶装置
US7564713B2 (en) * 2005-04-28 2009-07-21 Kabushiki Kaisha Toshiba Semiconductor integrated circuit device wherein during data write a potential transferred to each bit line is changed in accordance with program order of program data
KR100673703B1 (ko) * 2005-06-14 2007-01-24 주식회사 하이닉스반도체 멀티 레벨 셀들을 포함하는 플래시 메모리 장치의 카피백동작 제어 방법
KR100729355B1 (ko) * 2005-07-04 2007-06-15 삼성전자주식회사 멀티 레벨 셀을 갖는 노어 플래시 메모리 장치 및 그것의읽기 방법
KR100642892B1 (ko) 2005-07-19 2006-11-03 주식회사 하이닉스반도체 면적이 감소된 페이지 버퍼 회로와 그 독출 및 프로그램동작 방법
KR100729359B1 (ko) 2005-09-23 2007-06-15 삼성전자주식회사 낸드 플래시 메모리 장치 및 그것의 프로그램 방법
JP2007102848A (ja) * 2005-09-30 2007-04-19 Toshiba Corp 半導体集積回路装置
US7206235B1 (en) 2005-10-14 2007-04-17 Sandisk Corporation Apparatus for controlled programming of non-volatile memory exhibiting bit line coupling
US7286406B2 (en) * 2005-10-14 2007-10-23 Sandisk Corporation Method for controlled programming of non-volatile memory exhibiting bit line coupling
US7517482B2 (en) * 2005-11-09 2009-04-14 Industrial Technology Research Institute Method for producing polymeric membranes with high-recovery rate
JP2007164892A (ja) * 2005-12-13 2007-06-28 Toshiba Corp 不揮発性半導体記憶装置のしきい値読み出し方法及び不揮発性半導体記憶装置
JP2007280505A (ja) * 2006-04-06 2007-10-25 Toshiba Corp 半導体記憶装置
JP4896569B2 (ja) * 2006-04-10 2012-03-14 株式会社東芝 半導体集積回路装置及びそのダイナミックラッチのリフレッシュ方法
JP4995264B2 (ja) * 2006-04-12 2012-08-08 サンディスク コーポレイション 読み出し中におけるプログラム外乱による影響の軽減
US7499326B2 (en) 2006-04-12 2009-03-03 Sandisk Corporation Apparatus for reducing the impact of program disturb
JP2007310936A (ja) * 2006-05-17 2007-11-29 Toshiba Corp 半導体記憶装置
KR100754226B1 (ko) * 2006-08-22 2007-09-03 삼성전자주식회사 비휘발성 데이터 저장장치의 프로그래밍 방법 및 그 장치
US7593259B2 (en) * 2006-09-13 2009-09-22 Mosaid Technologies Incorporated Flash multi-level threshold distribution scheme
JP2008111921A (ja) * 2006-10-30 2008-05-15 Renesas Technology Corp 表示制御用半導体集積回路
KR100801035B1 (ko) * 2006-12-14 2008-02-04 삼성전자주식회사 멀티 레벨 셀의 프로그램 방법, 페이지 버퍼 블록 및 이를포함하는 불휘발성 메모리 장치
KR100855971B1 (ko) 2007-01-23 2008-09-02 삼성전자주식회사 초기 독출 동작없이 메모리 셀에 데이터를 프로그래밍할 수있는 메모리 셀 프로그래밍 방법 및 반도체 메모리 장치
KR100885912B1 (ko) 2007-01-23 2009-02-26 삼성전자주식회사 기입된 데이터 값에 기초하여 데이터를 선택적으로검증하는 데이터 검증 방법 및 반도체 메모리 장치
KR100819102B1 (ko) 2007-02-06 2008-04-03 삼성전자주식회사 개선된 멀티 페이지 프로그램 동작을 갖는 불휘발성 반도체메모리 장치
US7646636B2 (en) * 2007-02-16 2010-01-12 Mosaid Technologies Incorporated Non-volatile memory with dynamic multi-mode operation
US7577059B2 (en) * 2007-02-27 2009-08-18 Mosaid Technologies Incorporated Decoding control with address transition detection in page erase function
US7804718B2 (en) * 2007-03-07 2010-09-28 Mosaid Technologies Incorporated Partial block erase architecture for flash memory
US7577029B2 (en) * 2007-05-04 2009-08-18 Mosaid Technologies Incorporated Multi-level cell access buffer with dual function
KR100965066B1 (ko) * 2008-03-28 2010-06-21 주식회사 하이닉스반도체 플래시 메모리 소자 및 그 블록 선택 회로
KR20100050789A (ko) * 2008-11-06 2010-05-14 삼성전자주식회사 메모리 장치 및 그것을 포함하는 메모리 시스템
JP5193830B2 (ja) 2008-12-03 2013-05-08 株式会社東芝 不揮発性半導体メモリ
JP2010140521A (ja) * 2008-12-09 2010-06-24 Powerchip Semiconductor Corp 不揮発性半導体記憶装置とその読み出し方法
JP2011003850A (ja) * 2009-06-22 2011-01-06 Toshiba Corp 半導体記憶装置
JP2011008838A (ja) * 2009-06-23 2011-01-13 Toshiba Corp 不揮発性半導体記憶装置およびその書き込み方法
KR101009751B1 (ko) * 2009-06-24 2011-01-19 주식회사 아이에스시테크놀러지 Ｌｅｄ용 전기적 검사장비
JP5075992B2 (ja) * 2011-02-02 2012-11-21 株式会社東芝 半導体記憶装置
JP5380506B2 (ja) * 2011-09-22 2014-01-08 株式会社東芝 不揮発性半導体記憶装置
US9588883B2 (en) 2011-09-23 2017-03-07 Conversant Intellectual Property Management Inc. Flash memory system
JP5536255B2 (ja) * 2012-06-04 2014-07-02 慧榮科技股▲分▼有限公司 データアクセス時間を短縮したフラッシュメモリ装置及びフラッシュメモリのデータアクセス方法
TWI506630B (zh) * 2012-06-11 2015-11-01 Macronix Int Co Ltd 具有變動壓降的位元線偏壓電路
US9530469B2 (en) * 2013-03-15 2016-12-27 Sony Semiconductor Solutions Corporation Integrated circuit system with non-volatile memory stress suppression and method of manufacture thereof
CN107370351B (zh) * 2016-05-13 2019-12-27 中芯国际集成电路制造（天津）有限公司 电荷泄放电路
KR102540765B1 (ko) * 2016-09-07 2023-06-08 에스케이하이닉스 주식회사 메모리 장치 및 이를 포함하는 메모리 시스템

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KR960002006B1 (ko) * 1991-03-12 1996-02-09 가부시끼가이샤 도시바 2개의 기준 레벨을 사용하는 기록 검증 제어기를 갖는 전기적으로 소거 가능하고 프로그램 가능한 불휘발성 메모리 장치
US5357462A (en) * 1991-09-24 1994-10-18 Kabushiki Kaisha Toshiba Electrically erasable and programmable non-volatile semiconductor memory with automatic write-verify controller
JP3421365B2 (ja) * 1992-07-29 2003-06-30 直 柴田 半導体装置
JP3252306B2 (ja) * 1993-08-10 2002-02-04 株式会社日立製作所 半導体不揮発性記憶装置
KR0169267B1 (ko) * 1993-09-21 1999-02-01 사토 후미오 불휘발성 반도체 기억장치
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JP3863330B2 (ja) * 1999-09-28 2006-12-27 株式会社東芝 不揮発性半導体メモリ
JP3784229B2 (ja) * 2000-01-21 2006-06-07 シャープ株式会社 不揮発性半導体記憶装置およびそれを用いたシステムｌｓｉ
JP3983969B2 (ja) * 2000-03-08 2007-09-26 株式会社東芝 不揮発性半導体記憶装置
JP2002207715A (ja) * 2001-01-11 2002-07-26 Mitsubishi Electric Corp マイクロコンピュータ及びそれに用いるメモリ制御方法
US6480419B2 (en) * 2001-02-22 2002-11-12 Samsung Electronics Co., Ltd. Bit line setup and discharge circuit for programming non-volatile memory

Also Published As

Publication number Publication date
KR100515867B1 (ko) 2005-09-21
CN1497730A (zh) 2004-05-19
US20040062077A1 (en) 2004-04-01
TW200409360A (en) 2004-06-01
EP1403877A1 (de) 2004-03-31
EP1403877B1 (de) 2007-05-30
JP2004118940A (ja) 2004-04-15
KR20040027407A (ko) 2004-04-01
DE60314068T2 (de) 2008-01-24
TWI247427B (en) 2006-01-11
US20040174741A1 (en) 2004-09-09
US6885583B2 (en) 2005-04-26
CN1295794C (zh) 2007-01-17
US6850435B2 (en) 2005-02-01
JP4270832B2 (ja) 2009-06-03

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