DE60235846D1 - Speicherschaltung mit Paritätszellenmatrix - Google Patents

Speicherschaltung mit Paritätszellenmatrix

Info

Publication number
DE60235846D1
DE60235846D1 DE60235846T DE60235846T DE60235846D1 DE 60235846 D1 DE60235846 D1 DE 60235846D1 DE 60235846 T DE60235846 T DE 60235846T DE 60235846 T DE60235846 T DE 60235846T DE 60235846 D1 DE60235846 D1 DE 60235846D1
Authority
DE
Germany
Prior art keywords
memory circuit
cell matrix
parity cell
parity
matrix
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60235846T
Other languages
English (en)
Inventor
Shinya Fujioka
Waichiro Fujieda
Kota Hara
Toru Koga
Katsuhiro Mori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Semiconductor Ltd
Original Assignee
Fujitsu Semiconductor Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP2001358102A external-priority patent/JP3938298B2/ja
Priority claimed from JP2001374136A external-priority patent/JP2003173698A/ja
Application filed by Fujitsu Semiconductor Ltd filed Critical Fujitsu Semiconductor Ltd
Application granted granted Critical
Publication of DE60235846D1 publication Critical patent/DE60235846D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
    • G06F11/106—Correcting systematically all correctable errors, i.e. scrubbing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40603—Arbitration, priority and concurrent access to memory cells for read/write or refresh operations
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40615—Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C2211/406—Refreshing of dynamic cells
    • G11C2211/4062—Parity or ECC in refresh operations

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Dram (AREA)
DE60235846T 2001-11-22 2002-10-22 Speicherschaltung mit Paritätszellenmatrix Expired - Lifetime DE60235846D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2001358102A JP3938298B2 (ja) 2001-11-22 2001-11-22 パリティセルアレイを有するメモリ回路
JP2001374136A JP2003173698A (ja) 2001-12-07 2001-12-07 半導体メモリ

Publications (1)

Publication Number Publication Date
DE60235846D1 true DE60235846D1 (de) 2010-05-12

Family

ID=26624665

Family Applications (2)

Application Number Title Priority Date Filing Date
DE60235846T Expired - Lifetime DE60235846D1 (de) 2001-11-22 2002-10-22 Speicherschaltung mit Paritätszellenmatrix
DE60234076T Expired - Lifetime DE60234076D1 (de) 2001-11-22 2002-10-22 Speicherschaltung mit Paritätszellenmatrix

Family Applications After (1)

Application Number Title Priority Date Filing Date
DE60234076T Expired - Lifetime DE60234076D1 (de) 2001-11-22 2002-10-22 Speicherschaltung mit Paritätszellenmatrix

Country Status (6)

Country Link
US (1) US7032142B2 (de)
EP (2) EP1746606B1 (de)
KR (2) KR100864035B1 (de)
CN (1) CN1255818C (de)
DE (2) DE60235846D1 (de)
TW (1) TW569235B (de)

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JP5606880B2 (ja) * 2010-11-11 2014-10-15 ピーエスフォー ルクスコ エスエイアールエル 半導体記憶装置
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JP6915372B2 (ja) * 2017-05-16 2021-08-04 富士通株式会社 メモリセル、メモリモジュール、情報処理装置およびメモリセルのエラー訂正方法
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KR20190086936A (ko) * 2018-01-15 2019-07-24 삼성전자주식회사 메모리 장치
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KR20200119613A (ko) * 2019-04-10 2020-10-20 에스케이하이닉스 주식회사 반도체 메모리 장치 및 그의 동작 방법
KR20210093610A (ko) * 2020-01-20 2021-07-28 에스케이하이닉스 주식회사 비휘발성 메모리 장치 및 그것을 포함하는 메모리 시스템
TWI719841B (zh) * 2020-02-25 2021-02-21 世界先進積體電路股份有限公司 測試電路及電子裝置
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Also Published As

Publication number Publication date
US7032142B2 (en) 2006-04-18
EP1315176A2 (de) 2003-05-28
EP1746606A3 (de) 2007-03-07
EP1315176A3 (de) 2006-01-11
KR20080077948A (ko) 2008-08-26
DE60234076D1 (de) 2009-12-03
CN1421871A (zh) 2003-06-04
EP1315176B1 (de) 2009-10-21
CN1255818C (zh) 2006-05-10
EP1746606B1 (de) 2010-03-31
KR100864035B1 (ko) 2008-10-16
TW569235B (en) 2004-01-01
US20030106010A1 (en) 2003-06-05
KR20030043658A (ko) 2003-06-02
KR100901404B1 (ko) 2009-06-05
EP1746606A2 (de) 2007-01-24

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8327 Change in the person/name/address of the patent owner

Owner name: FUJITSU SEMICONDUCTOR LTD., YOKOHAMA, KANAGAWA, JP

8328 Change in the person/name/address of the agent

Representative=s name: SEEGER SEEGER LINDNER PARTNERSCHAFT PATENTANWAELTE

8364 No opposition during term of opposition