DE60212004D1 - Speicheranordnung - Google Patents
SpeicheranordnungInfo
- Publication number
- DE60212004D1 DE60212004D1 DE60212004T DE60212004T DE60212004D1 DE 60212004 D1 DE60212004 D1 DE 60212004D1 DE 60212004 T DE60212004 T DE 60212004T DE 60212004 T DE60212004 T DE 60212004T DE 60212004 D1 DE60212004 D1 DE 60212004D1
- Authority
- DE
- Germany
- Prior art keywords
- memory array
- array
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C5/066—Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Read Only Memory (AREA)
- Memory System (AREA)
- Semiconductor Memories (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/894,143 US6478231B1 (en) | 2001-06-29 | 2001-06-29 | Methods for reducing the number of interconnects to the PIRM memory module |
US894143 | 2001-06-29 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE60212004D1 true DE60212004D1 (de) | 2006-07-20 |
DE60212004T2 DE60212004T2 (de) | 2007-03-29 |
Family
ID=25402663
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE60212004T Expired - Fee Related DE60212004T2 (de) | 2001-06-29 | 2002-06-24 | Speicheranordnung |
Country Status (7)
Country | Link |
---|---|
US (1) | US6478231B1 (de) |
EP (1) | EP1271539B1 (de) |
JP (1) | JP3953902B2 (de) |
KR (1) | KR20030003054A (de) |
CN (1) | CN1395252A (de) |
DE (1) | DE60212004T2 (de) |
TW (1) | TW556214B (de) |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5673218A (en) * | 1996-03-05 | 1997-09-30 | Shepard; Daniel R. | Dual-addressed rectifier storage device |
US6956757B2 (en) | 2000-06-22 | 2005-10-18 | Contour Semiconductor, Inc. | Low cost high density rectifier matrix memory |
US6586327B2 (en) * | 2000-09-27 | 2003-07-01 | Nup2 Incorporated | Fabrication of semiconductor devices |
US7800932B2 (en) * | 2005-09-28 | 2010-09-21 | Sandisk 3D Llc | Memory cell comprising switchable semiconductor memory element with trimmable resistance |
US7139183B2 (en) * | 2004-07-21 | 2006-11-21 | Hewlett-Packard Development Company, L.P. | Logical arrangement of memory arrays |
US7106639B2 (en) * | 2004-09-01 | 2006-09-12 | Hewlett-Packard Development Company, L.P. | Defect management enabled PIRM and method |
US7450414B2 (en) * | 2006-07-31 | 2008-11-11 | Sandisk 3D Llc | Method for using a mixed-use memory array |
US7486537B2 (en) * | 2006-07-31 | 2009-02-03 | Sandisk 3D Llc | Method for using a mixed-use memory array with different data states |
US20080025069A1 (en) * | 2006-07-31 | 2008-01-31 | Scheuerlein Roy E | Mixed-use memory array with different data states |
US7393739B2 (en) * | 2006-08-30 | 2008-07-01 | International Business Machines Corporation | Demultiplexers using transistors for accessing memory cell arrays |
US7813157B2 (en) | 2007-10-29 | 2010-10-12 | Contour Semiconductor, Inc. | Non-linear conductor memory |
US8045416B2 (en) * | 2008-03-05 | 2011-10-25 | Micron Technology, Inc. | Method and memory device providing reduced quantity of interconnections |
US8325556B2 (en) | 2008-10-07 | 2012-12-04 | Contour Semiconductor, Inc. | Sequencing decoder circuit |
US8422324B2 (en) * | 2011-08-26 | 2013-04-16 | Nanya Technology Corp. | Method and apparatus for sending test mode signals |
WO2014113024A1 (en) | 2013-01-18 | 2014-07-24 | Hewlett-Packard Development Company, L.P. | Interconnection architecture for multilayer circuits |
KR102222445B1 (ko) | 2015-01-26 | 2021-03-04 | 삼성전자주식회사 | 선택적으로 동작하는 복수의 디램 장치를 포함하는 메모리 시스템 |
CN109884613A (zh) * | 2019-03-29 | 2019-06-14 | 湖南赛博诺格电子科技有限公司 | 一种基于fpga的二极管阵列在线同步控制系统及方法 |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3828263A (en) * | 1971-08-09 | 1974-08-06 | Physics Int Co | Demodulator for frequency-burst-duration modulated signals |
US4415991A (en) * | 1981-06-22 | 1983-11-15 | The United States Of America As Represented By The Secretary Of The Navy | Multiplexed MOS multiaccess memory system |
JPS63128463A (ja) * | 1986-11-18 | 1988-06-01 | Nec Corp | マイクロプロセツサ多重化システム構成 |
FR2629941B1 (fr) * | 1988-04-12 | 1991-01-18 | Commissariat Energie Atomique | Memoire et cellule memoire statiques du type mis, procede de memorisation |
JPH0935490A (ja) * | 1995-07-17 | 1997-02-07 | Yamaha Corp | 半導体記憶装置 |
US5909617A (en) * | 1995-11-07 | 1999-06-01 | Micron Technology, Inc. | Method of manufacturing self-aligned resistor and local interconnect |
US5905670A (en) * | 1997-05-13 | 1999-05-18 | International Business Machines Corp. | ROM storage cell and method of fabrication |
US5952691A (en) * | 1997-05-14 | 1999-09-14 | Ricoh Company, Ltd. | Non-volatile electrically alterable semiconductor memory device |
KR100289813B1 (ko) * | 1998-07-03 | 2001-10-26 | 윤종용 | 노아형플렛-셀마스크롬장치 |
JP3344331B2 (ja) * | 1998-09-30 | 2002-11-11 | 日本電気株式会社 | 不揮発性半導体記憶装置 |
US6256767B1 (en) * | 1999-03-29 | 2001-07-03 | Hewlett-Packard Company | Demultiplexer for a molecular wire crossbar network (MWCN DEMUX) |
US6683372B1 (en) * | 1999-11-18 | 2004-01-27 | Sun Microsystems, Inc. | Memory expansion module with stacked memory packages and a serial storage unit |
US6603168B1 (en) * | 2000-04-20 | 2003-08-05 | Agere Systems Inc. | Vertical DRAM device with channel access transistor and stacked storage capacitor and associated method |
KR100372247B1 (ko) * | 2000-05-22 | 2003-02-17 | 삼성전자주식회사 | 프리페치 동작모드를 가지는 반도체 메모리 장치 및 메인데이터 라인수를 줄이기 위한 데이터 전송방법 |
US6385075B1 (en) * | 2001-06-05 | 2002-05-07 | Hewlett-Packard Company | Parallel access of cross-point diode memory arrays |
-
2001
- 2001-06-29 US US09/894,143 patent/US6478231B1/en not_active Expired - Lifetime
-
2002
- 2002-05-29 TW TW091111446A patent/TW556214B/zh active
- 2002-06-24 DE DE60212004T patent/DE60212004T2/de not_active Expired - Fee Related
- 2002-06-24 EP EP02254398A patent/EP1271539B1/de not_active Expired - Lifetime
- 2002-06-28 KR KR1020020036573A patent/KR20030003054A/ko not_active Application Discontinuation
- 2002-06-28 JP JP2002189456A patent/JP3953902B2/ja not_active Expired - Fee Related
- 2002-07-01 CN CN02140563A patent/CN1395252A/zh active Pending
Also Published As
Publication number | Publication date |
---|---|
EP1271539B1 (de) | 2006-06-07 |
TW556214B (en) | 2003-10-01 |
KR20030003054A (ko) | 2003-01-09 |
JP2003022690A (ja) | 2003-01-24 |
JP3953902B2 (ja) | 2007-08-08 |
DE60212004T2 (de) | 2007-03-29 |
CN1395252A (zh) | 2003-02-05 |
US6478231B1 (en) | 2002-11-12 |
EP1271539A3 (de) | 2004-06-23 |
EP1271539A2 (de) | 2003-01-02 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8327 | Change in the person/name/address of the patent owner |
Owner name: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P., HOUSTON |
|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |