JP7143463B2 - 半導体記憶装置 - Google Patents
半導体記憶装置 Download PDFInfo
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- JP7143463B2 JP7143463B2 JP2021029784A JP2021029784A JP7143463B2 JP 7143463 B2 JP7143463 B2 JP 7143463B2 JP 2021029784 A JP2021029784 A JP 2021029784A JP 2021029784 A JP2021029784 A JP 2021029784A JP 7143463 B2 JP7143463 B2 JP 7143463B2
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40615—Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40603—Arbitration, priority and concurrent access to memory cells for read/write or refresh operations
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40622—Partial refresh of memory arrays
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4078—Safety or protection circuits, e.g. for preventing inadvertent or unauthorised reading or writing; Status cells; Test cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
- G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/24—Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C2029/0411—Online error correction
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Databases & Information Systems (AREA)
- Computer Security & Cryptography (AREA)
- Dram (AREA)
- Memory System (AREA)
Description
図2は、本発明の第1実施形態に係る半導体記憶装置の構成例を示すブロック図である。本実施形態に係る半導体記憶装置10は、I/O部11と、コマンドデコーダ12と、アドレスデコーダ13と、データバス制御部14と、メモリコア15と、リフレッシュ制御部16と、ECC制御部17と、を備える。半導体記憶装置10内の各部11~17は、専用のハードウェアデバイスや論理回路によって構成されてもよい。なお、本実施形態では、説明を簡略化するために、例えば電源回路、クロックジェネレータ等の他の周知の構成が示されていない。
以下、本発明の第2実施形態について説明する。本実施形態の半導体記憶装置10は、ECCセルアレイ15dがメモリセルアレイ15c内に設けられている点において、第1実施形態と異なっている。以下、第1実施形態と異なる構成について説明する。
以下、本発明の第3実施形態について説明する。本実施形態の半導体記憶装置10は、2T2Cセルアレイ15eが設けられている点において、上記各実施形態と異なっている。以下、上記各実施形態と異なる構成について説明する。
15c…メモリセルアレイ
15d…ECCセルアレイ
15e…2T2Cセルアレイ
16…リフレッシュ制御部
17…ECC制御部
18…2T2C制御部
Claims (6)
- pSRAMである半導体記憶装置であって、
外部から入力された所定のコマンドに含まれるメモリセルのリフレッシュ間隔に関する情報に基づいて前記メモリセルのリフレッシュ間隔を設定する第1制御部と、
HyperBus(商標)インタフェースを用いたpSRAMの第1構成レジスタであって、前記所定のコマンドを受信する第1構成レジスタと、
アレイ状に配置された複数のメモリセルを含むメモリセルアレイが複数のブロックに分割されている場合に、前記複数のブロックのうち何れかのブロックを選択する第2制御部であって、選択されたブロック内の複数のメモリセルに記憶されるデータに対して生成された誤り訂正符号内の検査データを所定の記憶領域に記憶する第2制御部と、
複数のスイッチをそれぞれ有するスイッチ部と、を備え、
前記第2制御部は、前記スイッチ部を制御して、前記選択されたブロックを前記所定の記憶領域に接続し、
前記第2制御部は、前記外部から入力された所定のコマンドに含まれる選択ブロックに関する情報に基づいて、前記複数のブロックのうち何れかのブロックを選択する、
半導体記憶装置。 - 前記所定のコマンドは、前記半導体記憶装置の機能を設定するためのコマンドである、請求項1に記載の半導体記憶装置。
- 前記第1制御部は、前記所定のコマンドが外部から入力される毎に、前記所定のコマンドに含まれるメモリセルのリフレッシュ間隔に関する情報に基づいて前記メモリセルのリフレッシュ間隔を設定する、請求項1又は2に記載の半導体記憶装置。
- 前記所定の記憶領域は、前記メモリセルアレイとは異なる他のメモリセルアレイに設けられている、請求項1に記載の半導体記憶装置。
- 前記所定の記憶領域は、前記複数のブロックのうち選択されたブロックとは異なる他のブロックに設けられている、請求項1に記載の半導体記憶装置。
- アレイ状に配置された1T1C型の複数のメモリセルを含むメモリセルアレイが複数のブロックに分割されている場合に、前記複数のブロックのうち何れかのブロックを選択する第2制御部であって、選択されたブロック内の複数のメモリセルに記憶されるデータを、2T2C型のメモリセルで構成された所定の記憶領域に記憶する第2制御部を備える、請求項1~5の何れかに記載の半導体記憶装置。
Priority Applications (3)
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JP2021029784A JP7143463B2 (ja) | 2021-02-26 | 2021-02-26 | 半導体記憶装置 |
CN202111069368.XA CN114974347B (zh) | 2021-02-26 | 2021-09-13 | 半导体存储装置 |
US17/575,117 US11715510B2 (en) | 2021-02-26 | 2022-01-13 | Semiconductor memory device having control unit which sets the refresh interval of the memory cell |
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JP2021029784A JP7143463B2 (ja) | 2021-02-26 | 2021-02-26 | 半導体記憶装置 |
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JP2022131054A JP2022131054A (ja) | 2022-09-07 |
JP7143463B2 true JP7143463B2 (ja) | 2022-09-28 |
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Citations (6)
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JP2000137995A (ja) | 1998-10-30 | 2000-05-16 | Nec Kyushu Ltd | 記憶装置 |
JP2002373489A (ja) | 2001-06-15 | 2002-12-26 | Mitsubishi Electric Corp | 半導体記憶装置 |
JP2008084426A (ja) | 2006-09-27 | 2008-04-10 | Fujitsu Ltd | 半導体メモリおよびシステム |
JP2008084052A (ja) | 2006-09-28 | 2008-04-10 | Nec Electronics Corp | 半導体記憶装置 |
JP2017045391A (ja) | 2015-08-28 | 2017-03-02 | 株式会社東芝 | メモリシステム |
JP2020177646A (ja) | 2019-04-17 | 2020-10-29 | エスケーハイニックス株式会社SK hynix Inc. | データ処理システム及びその動作方法 |
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2021
- 2021-02-26 JP JP2021029784A patent/JP7143463B2/ja active Active
- 2021-09-13 CN CN202111069368.XA patent/CN114974347B/zh active Active
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2022
- 2022-01-13 US US17/575,117 patent/US11715510B2/en active Active
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JP2000137995A (ja) | 1998-10-30 | 2000-05-16 | Nec Kyushu Ltd | 記憶装置 |
JP2002373489A (ja) | 2001-06-15 | 2002-12-26 | Mitsubishi Electric Corp | 半導体記憶装置 |
JP2008084426A (ja) | 2006-09-27 | 2008-04-10 | Fujitsu Ltd | 半導体メモリおよびシステム |
JP2008084052A (ja) | 2006-09-28 | 2008-04-10 | Nec Electronics Corp | 半導体記憶装置 |
JP2017045391A (ja) | 2015-08-28 | 2017-03-02 | 株式会社東芝 | メモリシステム |
JP2020177646A (ja) | 2019-04-17 | 2020-10-29 | エスケーハイニックス株式会社SK hynix Inc. | データ処理システム及びその動作方法 |
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US20220277786A1 (en) | 2022-09-01 |
CN114974347B (zh) | 2024-08-06 |
US11715510B2 (en) | 2023-08-01 |
JP2022131054A (ja) | 2022-09-07 |
CN114974347A (zh) | 2022-08-30 |
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