TW559696B - Error correction code circuits - Google Patents

Abstract

This invention discloses a method for changing a configuring of an error correction code (ECC) logic circuit for performing an error-check of a changed data-width. The method includes the steps of: (A) sequentially interconnecting a set of N1 identical error-check blocks where N1 is a first positive integer. And, the method further includes a step (B) of reconfiguring the ECC logic circuit by changing the ECC logic circuit to a set of N2 sequentially interconnected circuits comprising N2 of the identical error-check blocks where N2 is a second positive number. In a preferred embodiment, the step of sequentially interconnecting a set of N1 identical error-check blocks is a step of interconnecting the N1 error-check blocks only between sequentially neighboring blocks for transmitting signals only between the neighboring error-check blocks. And, the step of reconfiguring the ECC logic circuit by changing the ECC logic circuit to a set of N2 sequentially interconnected circuits is a step of interconnecting the N2 error-check blocks only between sequentially neighboring blocks for transmitting signals only between the neighboring error-check blocks.

Description

559696 V. Description of the invention (1) The present invention relates to error correction Γ I for wide sound with variable data. In particular, the present invention relates to applications and applications. In addition, the device of the ECC circuit for error correction applies error correction circuits. 6 | ) 2 Correction of materials is to improve the application of data storage devices. It is widely used in communication systems or information systems. Block diagrams can be used to solve ECC computer instances. I have a fixed number of bits. The ECC computer calculates the data packet. It is transmitted from the predefined data tree structure (the bits in the ^ 丨 ^ ^) to a plurality of the same bits of the same data subset. Each data has a $ -like structure) to calculate the packet data bits, and the-/, ^ subsets include about half of the data partially overlapping. The data generated in the ^ solid subset is combined with the unprocessed assets in the other subsets or stored (f:: ^ f $, ECC bits). There is an error in the unprocessed data to be transmitted. The way of set is, such as ψ ^ λ, n., Day, then θ is calculated by the same parity == original ECC bit to identify the wrong bit. The ECC mechanism provided by Advanced Technology provides excellent data integrity but brings many technical difficulties. ECC counts and puts in a large parity tree structure, and each parity tree is put; the parity subset of I performs the parity calculation without asking. Such complex wiring makes ECC circuits slow and complicated. == 算 所 = Performance degradation usually limits its application. Each type of 弁 ... calculation is caused by a specific data size;:. : Qiao == both mechanisms I ’it must reset the Ecc mechanism. Test is another =

Page 5 559696 559696 V. Description of the invention (2) The size of the ECC computer is increased. The use of the ECC circuit is increased because it has a total error of 275 < 2 72). Therefore, the non-elasticity of the ECC computer of the present invention is high. The speed E C C circuit that supports several ECC circuits at the same speed is provided by the invention. The rotating circuit block is provided in the present invention to simplify the electricity, so that the function can be further described in detail. Due to the error, the description will be based on a mechanism. For example, D3 and D24, the speed from g to g is extremely dependent on the input data mode, and it will definitely slow down its speed significantly. For example, one of the complex wiring is related to 5 2 = technical error coverage needs to be large * (such as the second defect = vector, so the detection of the problem is extremely difficult. ^ No, I want to develop a simple structure but have ECC mechanism is incapable. The main purpose of this article is to provide a simplified ECC computer that can be used. ^: A data packet of any size. Another; the primary purpose of the present invention is to use The new secondary application that is too suitable for practical products is a novel secondary purpose of the present invention, which is to provide a way to achieve by eight correlations. The generated ECC electric two == = material width can be extended at will. Higher performance road structure to achieve. The review committee understands and understands the structural features of the present invention, and I would like to describe the following with the preferred embodiment and configuration: The complexity of the correction mechanism. In the following discussion, the array used in the C programming language The symbol D [3: 2] [4: l] is a set of 8 symbols D34, D33, D32, D2 3, D2 2 and D21. The symbol rm〇d ”represents the adjustment of the remainder of the method difference (m 〇 (juiati〇n)

559696

V. Description of the invention (3) Calculate. For example, [(k + 3) mod 8] is equal to 2 when k = 7, and [(k-3) mod 8] is equal to 6 when k = 1. The "mod" function is implemented by the rotation correlation in the input connection of the actual circuit. In U.S. Patent No. 6, 2 1 6, 246, the inventor published an ECC computer as shown in Fig. 2 (a). The ECC computer in this example uses 64 inputs 〇) [7: 0] [7: 0]). It contains 8 identical parity circuit blocks (P 7-P 0). Figure 2 (b) shows a block diagram of a parity circuit block. Each parity circuit block (P7-P0) includes 19 exclusive-or (X0R) gates, an exclusive-nor and an inverter. The parity circuit block P [k] uses data D [k] [7:

And stored ECC bits Ck as input, where k is an integer between 0 and 7. It transmits four outputs (NΠ, N22, N33, N41) to the parity circuit 'above it and receives corresponding outputs (N11B, N22B, N33B, N41B) from the parity circuit below it. It also transmits two rounds (ie, N24, N32, and N42) to the peer circuits below it, and receives corresponding outputs (ie, N2 4T, N24T, and N42T) from the peer circuits below it. It also outputs a correction factor Fk. The output logic function of the k-th parity circuit (P [k]) can be written as follows: Only 1! = Parity {Ck, DkO} (la), N23 ^ Parity {Dk3, Dk4, Dk7} ( lb), N33 = Parity {N23B, Dk2, Dk5, Dk6} (lc), N41-Parity {N33B, N24T, Dkl, Dk4, Dk5} (Id), N24 = parity {Dk4, Dk5, Dk6, Dk7} ( le),

Page 7 559696 V. Description of the invention (4) N32 = Parity {DkO, Dkl, Dk2, Dk3, Dk4, Dk5,

Dk6, Dk7} (If), N42-Parity {N32T, N11B: DkO.Dkl, Dk2, Dk3,

Dk4, Dk5} (lg), and

Fk = Par {ty {N42T, N41B} (lh), where “Parity {}” means the parity value of all inputs included in the “{} " notation. Inputs provided by nearby circuits (N11B, N22B, N33B, N41B, N24T, N32T, N42T) can be determined according to the fact that these homotopic circuits are exactly the same. For example, the following function correlation can be established from equation (1 a): N11B = Parity {C [(k + l) mod 8], D [(k + 1) mod 8] 〇l (2) where C [(k + 1) mod 8] is the stored ECC bit, and D [(k + 1) mod 8] 〇 is The first data connected to the same circuit below it. All other inputs (N22B, N33B, N41B, N24T, N32T, N42T) can be determined in a similar way. According to the connection shown in Figure 2 (b) And equation (la-1 h), the following calculations can be performed:

Fk = Parity {Ck, D [(k ~ 2) raod8] [7: 0], D [(kl) mod 8] [5: 0], D [k] [7: 4, 0], D [( k + l) mod 8] [5, 4, 1], D [(k + 2) mod 8] [6,5,2], D [(k + 3) mod 8] [7, 4, 3] } (3) where 1 ^ (0,1,2,3,4,5,6,7). If there is no error in the input data, the (F k) signals are all zero. If there is no error in the input data D [7 ·· 0] [7: 0], the way to identify the error bit is to use the ECC decoder shown in Figure 2 (c) to check

Page 8 559696 V. Description of the invention (5) Correction factor (F0-Fk). This ECC decoder consists of 8 ECC decoders, group f (CB0-CB7). These 8 ECC decoding blocks have exactly the same logical work: ′ As shown in the schematic diagram in Figure 2 (d). The only difference is the connection of the Flail F team numbers. Again, there is a rotation correlation in Fk connections. For example, F1 of cB 1 is equal to F0 of CBO, and F2 of CB2 of CB2 is also F0. The output of these ECC decoding blocks (CB0-CB7) (CR [7: 0] [7: 0] # ) Refers to the position of the error bit. If CRi j # is a low level, it means that the Dkj value should be reversed 'where k = (0, 1, 2, 3, 4, 5, 6, 7) and j = (〇, 1, 2, 3, 4, 5, 6, 7) The same circuit in Figure 2 (a) can be used to calculate the ECC bits of the unprocessed data set; a zero value will be assigned to all Ck inputs, and the resulting Fk will be the ECC bits shown below Meta ECC (k) = Parity {D [(k-2) mod 8] [7: 0], D [(kl) mod 8] [5: 0], D [k] [7: 4,0], D [(k + l) mod 8] [5, 4, 1], D [(k + 2) mod 8] [6, 5, 2], D [(k + 3) mod 8] [7, 4 , 3]} (4) where ECC (k) is the ECC bit value, and k = (0, i, 2,3,4,5,6,7).

The parity calculation rotation correlation of the ECC mechanism shown in Figures 2 (a) to 2 (d) is a novel mechanism; the parity calculation of C [k + 1] is the result of simple rotation of c [k] . This rotation correlation also applies to the Ecc correction circuit. In the present invention, such an ECC circuit is called a "rotary Ecg computer (REC)". Differences between REC circuits and other prior art ECC circuits

559696 V. Description of the invention (6) Including: (1) The prior art ECC circuit uses different ECC tree structures to calculate different ECC bits, which results in circuits that require complicated wiring connections to duplicate. Rotational associativity allows the REC to use exactly the same building blocks to support all logical calculations. Design reproduction is dramatically simplified. (2) Each input data in the prior art ECC must travel a long distance to reach the multiple parity tree structure. For REC, each input data only needs to travel to one parity circuit block. This dramatic simplification reduces the routing complexity of the input signal, resulting in a significant improvement in speed. (3) The intermediate logic signals (NU, N22, N33, N41, N24, N32, N42) only need to travel to the nearby parity circuit block. There is no longer any long signal lines or complicated wiring in any part of the entire rEC circuit. This is the main reason why RECs must be significantly faster than prior art ECC computers. (4) Due to the rotational symmetry, the speed of the REC circuit is almost independent of the input data mode, and the testing, debugging, and optimization procedures are significantly improved. An important feature of REC is that it supports the input data of different sizes using the same repeating circuit. The circuit block used in the REC circuit shown in Figure 3 is exactly the same as the circuit block shown in Figure 2 (a) to support variable-length input data. The ECC computer in this example uses N input data (D [(N-1): 0] [7: 0]), where N is an arbitrary integer. It contains N identical parity circuit blocks (PN-1-P0) connected in a rotational correlation manner, as shown in Figure 3 (a). The logic functions of these parity circuit block (PN-1-P0) are the same as the logic function of the parity circuit block shown in Figure 2 (b).

Page 10 559696 V. Description of Invention (7) It is the same. The equation (la-h) still applies, except that k may be any number between 0 and N-1. Equation (2-4) must be rewritten as shown below

NllB = Parity {C [(k + l) mod N], D [(k + l) mod N] 〇} (5) Fk = Parity {Ck, D [(k-2) mod N] [7: 0 ], D [(k-1) mod N] [5: 0], D [k] [7: 4, 0], D [(k + 1) mod N] [5,4, l], D [ (k + 2) mod N] [6,5,2], D [(k + 3) mod N] [7,4, 3]} (6) ECC (k) = Parity {D [(k-2 ) mod N] [7: 0], D [(k-1) mod N] [5: 0], D [k] [7: 4,0], D [(k + l) mod N] [5 , 4, l], D [(k + 2) mod N] [6,5,2], D [(k + 3) mod N] [7, 4, 3]} (7) where ECC (k) Is the ECC bit value, and k, "i,-, u ^ Factory specifically, the REC circuit shown in Figure 2 (ad) is just a special case of (n = 8). The REC circuit can be extended to support any The number of input data sets' is implemented by implementing the same repeated rEC building block as shown in Figure 3 (a). The resulting circuit will have exactly the same speed and the same circuit Ϊ 2. Without reducing the input data The width of the set. No need to redesign the ECC counter to support different data widths. For different types of applications, it can also be used. 2 2t Closed loop shown in Figure 3 (b) to expand the application of the invention > Consider FIG. 3 (b), the alternative preferred embodiment shown in the figure is suitable

559696 V. Description of the invention (8) It is used to continuously receive a long incoming data stream that starts and ends with a predefined data (for example, a title record). This is a situation often encountered in data communication systems. As shown in Figure 3 (b), instead of using the closed loop REC circuit as shown above, a serial rotation error correction circuit is implemented to continuously receive and process the data stream to ensure the correction of data transmission. An artificial wrap around logic circuit (AWALC) is implemented in which the error code calculation is performed by feeding a simplified bit pattern (such as all one or all zeros) to the REC computer block at the beginning and end. In the case where a fixed bit pattern is input to these chunks, the error code calculation is performed similarly to the closed loop REC. Open-loop coiled ECC computers are easily controlled or reset to handle variable-length data streams by first transmitting the length of the data record and then supplying the corresponding number of ECC blocks to perform error code calculations. Although specific embodiments of the invention have been described herein, it will be apparent to those skilled in the art that other changes and modifications can be made. For example, equations (1-7) can be modified to different forms while still maintaining rotational correlation. The parity block can take different input numbers other than 8 and output different numbers of ECC bits and intermediate signals. The novel element of the correction mechanism of the present invention is the rotation correlation that enforces the ECC mechanism parity calculation. Depending on the rotation associativity, repeated circuit designs can be used to simplify the design of the finished product. Higher performance is also achieved by reducing wiring complexity. According to the foregoing description, the present invention discloses a method for changing the configuration of an error correction code (ECC) logic circuit to perform error checking of a changed data width. The method includes the following steps: A) consecutively interconnecting a group

Page 12 559696 V. Description of the invention (9) N1 identical error checking groups and 'This method further includes steps ^ J: N1 is the-positive integer into a group of N2 consecutively connected to each other) From, ... in the preferred embodiment of package 23 :: continued :: even i: N2 is the same as the king of the error checking block, the steps are to connect only p 魬 N1 checking blocks to each other The N1 errors ^ 2 of the wrong pigeon are transmitted only between adjacent error-checking blocks as a number, two: steps, using this ECC logic circuit to change into a group of N2 connections ^ ς ^ Xiang by the new The configuration of the ECC logic circuit is 0, and the necessary circuits are used to prepare the interconnections between the blocks; errors and errors 4 are checked to transmit signals between adjacent error-checking blocks. The last step is to use only the system that prepares the aforementioned ECC protection mechanism will require additional and later storage resources. These additional f-source requirements can reduce system cost. In fact, the Ecc protection mechanism usually helps to reduce the overall cost of Erjiao supplements. These discussions will be explained in the following discussion. The example used by Wu Beiguan, the first example is about the application of floating gate device.帛: ί The symmetrical structure of the transistor. This transistor contains source (s) less than = (D) and gate (G), just like common transistors. The difference is that the first one is the floating gate (FG) between the gate and the channel area. ^ There are ^ works Ϊ Ϊ Ϊ I will isolate the floating room ^ 'Programming or erasing work " ° s From the ", carrier mechanism or tunneling mechanism, the charge is injected into the floating electrode or the electricity in the floating gate is removed. The conductivity of the floating gate is the floating gate

559696 V. Function of the total charge intercepted in the description of the invention (ίο) (FG). Therefore, by changing the total amount of charge intercepted in the floating gate, data can be stored in the floating gate. Many commercial products such as EPROM, EEPROM and FLASH have been built on floating gate devices. The most difficult reliability problems of floating gate devices are charge loss (QL) problems and programming cycle (pe) cycle induction errors. QL is usually caused by manufacturing defects near the insulator surrounding the floating gate. Manufacturing defects will cause small floating gates: leakage, so that the device intercepts electricity lost due to losses.

No data can be maintained. QL problems usually do not cause permanent damage to the floating gate device; if data is rewritten to the failed device, it will maintain function for a period of time until the charge it intercepts gradually leaks. PE # ring-sensing errors are usually permanent. When a user executes a program to erase the floating gate device multiple times, the high-energy charge flowing through the floating gate device can cause damage to nearby components, so that the device will fail after a PE cycle. General floating gate devices must have excellent fault tolerance to meet QL and PE cycle requirements; faults are usually caused by manufacturing defects. Current technology floating gate products contain millions of memory cells, and QL and PE # ring fault tolerance are determined by the worst bit of a million delta memory cells. Therefore, using ECC to protect floating gate products can significantly improve reliability. Protected by ECC = The reliability characteristics of the device are no longer determined by the worst bit in the device. Rather, it depends on the nature of the device; the resulting product is often sinful. When the stored data is wrong, the ECC circuit can also know the correction data. Therefore, it is possible to fix the source of the problem, not just the output. ^ 5 shows the flowchart of the ECC self-healing procedure. This self-healing process can be initiated by an external system such as computer software. It can also start internally

Page 14 559696 V. Description of the invention (π), but the external user does not know that it can be called by a program during the start-up cycle, or use ^: 1 in the initial sequence of startup. It is assumed that the ECC bit and the unprocessed data have been used to trigger the program. In starting the self-healing procedure: ;;; and the associated ECC bit. The ECC circuit is used to check; whether there are any errors. If there is no error, the error checking operation proceeds to the next data set until the procedure is completed. If an error is found and the ecc helmet correction is incorrect, the device sends a warning signal to the system. If the problem can be corrected, the corrected data bits will be written back to a problem caused by a soft error such as a charge loss problem in a floating interpolar device, or a problem caused by "particles. The problem can be solved by writing the correct information back to the memory pack [. The incorrect data should be read and checked again. If the issue is resolved ’, the error code check operation can now proceed to the next data set. If the problem cannot be solved by writing back the correct data, a programmable redundant circuit can be implemented to solve the problem caused by incorrectly recording 7 hidden units. If the redundant circuit can solve the problem, check the error and proceed to the next data set. If the redundant circuit does not solve the problem, the & product can still work normally, because the user can get the correct data after the ECC correction. However, if the ECC corrects a large number of errors, it is likely that serious failures will soon occur. A counter can be implemented to count the number of corrected errors ^. If the quantity is greater than a predefined value, a warning signal is generated to notify the system user. The foregoing self-repair procedure is not limited to the use of the REC circuit of the present invention. In any case, even prior art ECC circuits may be able to perform similar functions, the advantage of the REC of the present invention is that the ecc power is significantly reduced and increased.

Page 15 559696 V. Description of the invention (12) The area required for the road and increase the speed of error code checking operation. According to the foregoing description, the present invention further discloses a method for operating a memory device including a plurality of memory units. The method includes step ^ to perform error checking of the memory units. And, step B) repairing a wrong memory unit storing a wrong data bit by mistake. In a preferred embodiment, the step of repairing an erroneous memory unit further includes the step of automatically repairing the erroneous memory unit by writing a correct bit ^ to the erroneous memory unit, although the application by a skilled artist may not complex. The survivability is detected under tight conditions. E.g . Any storage is not limited to implementation due to improved cost-effective information. The total number of charges is expected to be two. The clerk in this article should be changed from using writes to adopting their potential conditions. Potential 'may be stored in floating ECC yield and benefits. Also for example, so bit, has been explained Bai Kejin I repaired it back to repair other types of errors, with lower or system gate protection or self / or available using definition IV now available instead of the line of the invention other The fine mechanism of the program, other repairs, self-healing and implementation at this voltage or less can be implemented. I repair machine High reliability Reliability change An analogy uses only a single bit Specific implementation changes and modifications. Section. For example, one application might be timing adjustment. Procedure to perform the above method in case of errors caused by high temperature. For example, but can be used for different applications without redundancy to repair another problem that may work normally. Fix it before I fix the procedure. The method of this method will require additional resources, but 'the resulting product may be better on the same device. The medium carrier is more accurate to indicate the memory cell intercepted by the floating gate to store binary data. Figure 2 (a) shows this multiple

5. Description of the invention on page 16 (13) Predicated ί:] 枓! Mdie ievei duitai —a; mldd) The table first defines the value (Q3) (:, J pole f centered 2 has intercepted the charge ⑻ greater than 3 < Q1, will store binary 'material-carry data (0, 1); if it is related to the sensing circuit trigger level I), among which deduction, 92 and Q1 > Qi. … Methods =; pre-sensing value H > Q2 can store double the amount of data. At this time, when D is compared earlier, this method 2 protects this class by correcting errors; method 3: degree increases Four times. ECC errors can make the present invention self-repair 1. Consistent value. There is a problem by fixing the MLDD notation of =. Such as ^ Shi reliable. The data stored in Figure 2 (a) is (1,0), and the device is ready for Q3 > Q > Q2. The original data will change to (〇1) \% of some charge is lost to Q2 > Q has two binary bit changes'. ECC has only a small amount of charge loss, which may result in j. Two separate ECC circuits are required and must be able to correct two bits. Therefore, both methods require multiple paths to separate The protection of these two bits f is defined as the table shown in Figure 2 (a) if the two-bit MLDD representation is required. For each higher two 7 ^ method, the upper bits of this resource can be reduced. Therefore, the second, second, and third data will never be changed. One method can be applied to Figure 6 (:) to repair the small charge loss in the second method. The class and the 16-bit quasi-four bits in Figure 6 (d) * 8-bit quasi 3-bit example, shown in Figure 6 (e). The circuit shown in Figure 6) is used to implement the analog re-export. The comparator (651) converts the analog signal.

559696 V. Description of the invention (14) (Q) Compare the predefined values (Q3, Q2, Q1). For example, if Q > Q1, the output of the first comparator (CP 1) is 1, and if Q < Q, the output is 0; if Q > Q2, then the output of the second comparator (CP2) The output is 1, and if Q < Q2, its output is 0; if Q > Q3, the output of the third comparator (CP3) is 1, and if Q < Q3, its output is 0. The outputs of the comparators (CP3, CP2, CP1) are passed to the decoder (6 5 2) circuit. The encoder (6 5 2) provides two digit output bits (D 1, D 0). If CP3 = CP2 = CP1 = 1, then the (Dl, DO) value is (1, 0); if CP3 = 〇, and CP2 = CP1 = 1, Beij (Dl, D0) value is (1, 1) 'If 〇? 3 = 〇? 2 = 0 and 〇 卩 1 = 1, then (1) 1, 1) 0) value

Is (0, 1); if CP3 = CP2 = CP1 = 0, the value of (D1, D0) is (0, 〇). The tables shown in Figs. 6 (C) and 6 (d) can each be implemented in a similar way. According to the previous circuit for storing the charge, the same storage error-multiple bit charge bit carry bit-at least one of the multiple bits further reveals that a plurality of cells have a Incorrectly connected to other memory units, the memory device is moved to the gate. At least the memory device in the supply unit is further stored in the floats. The memory sheets are stored according to the memory sheet to check the logic. The completed data steps include at least two two The second step includes the moving gate device, and the floating gate detects the error. At the calibration voltage, use. The two kinds of electricity in the present invention are relatively accurate. The inspection logic checks the block specific device, which indicates that the specific sensing load level is a memory memory editing circuit, which is used in the embodiment to store in this embodiment, and is used to detect a further including a connection. Check the memory, the float memory, etc.

Page 18 559696

At least of the elements, the multiple bit is used to generate a one-bit device based on the second bit, wherein the second bit is different from the second bit of the generation. Two-bit binary quasi-charge sensing multiple-level electrical mode. The basis for a further charge is provided in a further continuous phase mode. Bit. In another device, further sensing is performed to set one item each having the charge level level adjacent to the first item. The first item preferably includes a body to apply a row of towels to generate one. The bit mode only has the charge level in the first embodiment of the mode device. The bit mode pattern sequence has a single-bit two-charge level, although those skilled in the art should understand that the present invention can be performed. Other charges that can be applied using other types of parameters can be any charge such as voltage or current. The device is not necessarily a specific embodiment of the float, but is well-known for changes and modifications. Previous method Other types of devices. For example, Q can be an analog parameter, not necessarily an intercepting gate device.

m f: An implementation example is an application related to content addressable memory (CAM). The basic structure of the prior art CAM device is shown. Two types of lean materials are stored in the CAM device—general-purpose digital data stored in a typical random access memory (RAM) array (703), and addressing data stored in (: Dragon Array (701)) (in the IC industry) (Referred to as "TAG"). Figure 7 (b) shows a schematic diagram of a typical memory cell in a RAM array (703). This memory cell uses four

Transistors (MpO, Mpl, MnO, Mnl) to form a bistable locker for storing data, and two transistors (M w, M w #) for selecting memory through a word line (WL) unit. Figure 7 (c) shows a schematic diagram of a typical memory cell in a CAM array (701). This memory cell is similar to a RAM cell, except that it has four additional transistors (Mc0, Mel, McO #, Mcl #) to construct

559696

Shape an XOR gate to compare the new tag on the bit line (BL, BL #) with the stored data (cc, cc #). If the stored data and bit line values are different, the level of the unpointed line (MISS #) will be pulled down. Each column in the CAM array (701) includes a plurality of CAM cells, and the MISS # lines of these CAM cells are connected together. § When any bit in one of the stored TAG columns is different from the queried TAG, the M I SS # line will be at a low level. The MI line (705) of each TAG column is used to control a word line (WL) corresponding to a RAM column. Only when the TAG stored in the selected row is the same as the query TAG, the stored data can be read from the RAM array. The CAM device shown in Fig. 7 (a) is a powerful device. It can query a large number of storage addresses at the same time and read out the required data using the correct address. This is done by this parallel query operation, so the prior art CAM has no ECC protection. To ensure that the TAG query result is correct, during the query processing procedure, it must be ensured that the entire TAG array is free of any wrong bits. Therefore, each column of the CAM array requires an Ecc computer, which is too costly and the ECC guarantee is not practical. Therefore, prior art products often fail due to reliability issues, such as alpha particle sensing soft errors. However, based on the practical purpose of providing ECC protection in CAM query jobs, it is not necessary to implement ECC protection for all columns in the CAM at the same time. Moreover, because subsequent operations use only matching data bit streams, only the columns that match during the CAM query need to be protected. Figure 8 (a) shows a block diagram of an ECC protected CAM. This CAM device still has the same CAM array (801) for TAG query and the same RAM array (803) for storing data. The structure and memory unit used in the CAM array (801) and the RAM array (803) are completely the same as those shown in Figures 7 (a), 7 (b), and 7 (c). the same

Page 559 696

. For each TAG data set, the ECC circuit calculates it in the CAM array (80 7). The two ECC CA bits are stored in the "list" separately or combined. 8 (M picture shows the flow chart of the CAM query procedure of = 7 and = CAM array. During the query period, the ECC bit in Figure 8 (a) is not displayed. If there is no match, the TAG and its result are compared by the system as usual. A TAG matches and its ECC bits also match ,,,,, and = to notify the operation. For example, the data transmission of the data. If there is a TAG, then the matching is performed as usual ', which means that this is an incorrect match. This must notify the "bit Mismatch Mismatch 'and treat it as a mismatch. Decidable two: = item: The method is to write and ask the ECC array to determine the correct value. If more than one TAG match is found in the array, then ^ array. If The TAG is a true match. Only the correct data will be transmitted. The CC matched TAG matches the error TAG operation, and the Chuan Fan stream will be notified. Error repair and correction events will also be performed. The RAM array is also standardized to inform the data protection.料 料. Another example is in the _ array element: instead of being stored in the CAM array, such as the second storage ECC bit, and

Figure 8 (d). During the TAG query period, the picture is not good. If the query procedure is matched, as usual, the system executes and finds no matching general comparison TAG. If there is no match, the data will be read from the RAM array ^: If there is a TAG to protect both. After ECC calculation, if; AECC calculation, to ensure that error 1 must be notified to the system. If _zhentest is considered not to be a match. Can be used to solve the problem; item: mismatch, and J Jie Wu ’the way is to ECC array

559696 V. Description of the invention (18) The column determines that the correct value is written back. The resource used is less than the number of multiple domains found in the TAG array. Which match is directly based on the multiple memory single allocations of the memory (CAM) device capacity. An array error check logic circuit takes errors. In an example of a memory cell array with an error code storage device and a memory cell array, a data access error code storage device of an error code detection array generated by each memory list is an error checking logic circuit. (ECC) bit, error. In summary, the present invention, in particular, the device of the present invention is suitable for ECC circuits, which is progressive, and available. It is related to errors and applications with variable data. Therefore, users in the industry should use CAM and RAM arrays. The example shown in Fig. 8 (c) uses the resources shown in the conventional example shown in Fig. 8 (a) ^ If the matching is repeated, the structure shown in Fig. 8 (c) cannot be matched accurately. The present invention further discloses that a content-addressable CAM memory device includes a memory array for storing an array, and is used for accessing data based on a frame of content with the array. The CAM device pushes water from the memory to check each memory single bank. In the embodiment, the CAM device further includes a code-per-check (ECC) for storing the error-checking logic circuit. In order to check the wrong block per shell. In another preferred embodiment, the inspection logic circuit: (EfC) bit is used to check each memory unit. In another preferred embodiment, the fault machine accesses the memory (RAM ) The device 'is used to store an error code of each memory cell array used in order to check the data access correction code (ECC) of each memory cell array. The width of the error correction of the invention is indeed a novel invention that complies with the provisions of the Chinese Patent Law 559696. 5. The patent application requirements of the invention description (19) are undoubted. I have filed an application for an invention patent according to the law. . However, the above is only a preferred embodiment of the present invention, and is not intended to limit the scope of implementation of the present invention. For example, changes in shape, structure, characteristics, and spirit according to the scope of the patent application for the present invention are equivalent. Modifications shall all be included in the scope of patent application of the present invention. Brief description of drawing number: 6 5 1 comparator 6 5 2 decoder 701 CAM array 703 RAM array 705 MISS # line 801 TAG CAM array 803 RAM array 807 ECC CAM array

Page 559696 Brief description of the diagrams Figure 1: Block diagram showing ECC circuit of the prior art; Figure 2 (a): Principle diagram showing rotation correlation between ECC blocks implementing the present invention; Figure 2 (b) Figure: shows the principle diagram of the ECC block shown in Figure 2 (a); Figure 2 (c): shows the structure of the ECC decoder of the present invention; Figure 2 (d): shows the location shown in Figure 2 (c) Schematic diagram of the ECC decoder block shown; Figure 3 (a): shows the variable-width ECC computer of the present invention; Figure 3 (b): · Shows the processing of data streams of different incoming data widths that allow continuous processing Variable-width ECC computer; Figure 4: shows the structure of the floating gate device of the prior art; Figure 5: a flowchart showing the ECC self-healing procedure of the method of the present invention; Figures 6a to 6d: shows the use of a Different methods of analog signals to represent multi-bit digital data; Figure 6 (e): a block diagram showing a circuit for implementing analog-to-digital data translation according to the table shown in Figure 6 (b); Figures 7a to 7 Figure 7c: shows the structure of the addressable memory and its associated memory unit of the prior art content; and Figure 8a Through FIG. 8d: ECC shows an example of the protection means about CAM.

Page 24

Claims (1)

559696 VI. Scope of Patent Application 1 · A method for changing the configuration of an error correction code (ECC) logic circuit to perform an error check of a changed data width, the method includes the following steps: A group of N1 pieces are continuously connected to each other Exactly the same error-checking block, where N1 is the first positive integer; and the ECC logic circuit is reconfigured by changing the ECC logic circuit to a set of N2 continuous interconnected circuits that includes N 2 identical The error checking chunk, where N2 is the second positive integer. 2 · The method as described in the first item of the patent application scope, where: · The steps of consecutively connecting a group of N 1 identical error-checking blocks are to connect each other only between consecutively adjacent error-checking blocks 4 This Steps of waiting N 1 error checking blocks for transmitting signals only between adjacent error checking blocks; and reconfiguring ECC by changing the ECC logic circuit into a set of N 2 consecutive interconnected circuits The step of the logic circuit is a step of connecting the N 2 error-checking blocks to each other only between consecutive adjacent error-checking blocks to transmit signals only between the adjacent error-checking blocks. 3. A method for operating a memory device including a plurality of memory cells, the method including the following steps: performing an error check on the memory cells; and repairing an error memory cell storing an erroneous data bit. 4. The method according to item 3 of the scope of patent application, wherein the step of repairing an incorrect memory unit further includes, by Page 25 559696 VI. Scope of patent application Steps for confirming that the bit is written to the wrong memory unit to automatically repair the wrong memory unit. 5. A memory device including a plurality of memory cells, wherein each memory cell has a floating gate for storing a plurality of charges, the memory device further includes: an error check logic circuit, the error check logic circuit includes Continuous-an interconnected set of identical error-checking blocks for checking data storage errors in these memory cells. 6 · If the memory device according to item 5 of the scope of patent application, the memory device further includes: a multi-level voltage device for supplying to the floating gates to at least two charge levels of f to indicate storage in the Wait for at least two binary bits in the memory unit. 7 · If the memory device according to item 6 of the patent application scope, the memory device further comprises: a multi-level charge sensing device for detecting at least two charge levels stored in the floating gates, so as to Detecting at least two binary bits stored in the memory cells. 8. The memory device according to item 7 of the scope of patent application, wherein the multi-level charge sensing device further includes a bit mode device for determining the charge level based on the multi-level charge sensing device. To generate a one-bit pattern. 9 · The memory device according to item 7 of the patent application scope, wherein: the bit mode device further provides for generating a voltage according to the charge level. Page 26 559696 VI. Patent application bit pattern sequence, in which each bit pattern according to a first charge level differs by only a single bit from a second charge representing a consecutive adjacent first charge level Level of the second bit pattern. I 〇 · — A memory device including a plurality of memory units, wherein each memory ^ unit has at least two characteristics of the memory unit, each state represents a one-bit mode stored in the memory unit, the memory device is One step includes: An error checking logic circuit, which includes a set of identical error checking blocks that are continuously connected to each other to check data storage errors in the memory units. II · A content addressable memory (CAM) device including a plurality of memory cell arrays ji for storing an array content, for providing data access to an array according to a match with the content of the array, the CAM The device further includes: an error checking logic circuit for checking data access errors of each memory cell array. 1 2 · If the content of claim 11 of the patent application addressable memory (CAM) device, the CAM device further includes: an error code storage device for storing each memory cell array used by the error checking logic circuit An error code check (ECC) bit is used to check data access errors of each memory cell array. 1 3 · Addressable memory (CAM) device as described in item 11 of the scope of patent application, where: each memory cell array further stores the error check logic circuit product 559696 VI. Scope of patent application A single bit pattern of a meta pattern is different from another bit pattern representing an adjacent signal level. liB Page 29