TWI729786B - Memory storage device and automatic error repair method thereof - Google Patents

Abstract

The disclosure is directed to a memory storage device and an automatic error repair method thereof. In an aspect, the memory storage device includes a connection interface configured to receive a write command and a word line address associated with the write command, a memory array including a memory bank which contains an error correction code (ECC) detector, a plurality of memory cells controlled by a word line address, and a plurality of redundant memory cells controlled by a redundant word line address, a fuse blowing controller configured to receive the word line address to blow an electrical fuse of the word line address to enable the plurality of redundant memory cells, and a memory control circuit configured to transfer data from the plurality of memory cells through a bit line into the plurality of redundant memory cells in response to the electrical fuse having been blown.

Description

Memory storage device and its automatic error repairing method

The invention relates to a memory storage device with an automatic error repair mechanism and an automatic error repair method used by the memory storage device.

Currently, since user data stored in memory storage devices are expected to be highly reliable, typical memory storage devices use specific error correction code (ECC) technology to detect bit failures and subsequent Restore the data associated with the bit failure. If the unit in the memory storage device is damaged or becomes weaker, the memory bits stored in the damaged unit can be detected by ECC. However, it may not be possible to repair physically damaged or worn out cells through ECC, and thus the storage bits stored on these damaged cells will likely continue to fail. In addition, ECC can only repair a predetermined number of bits. If one or more extra bits in the same row address or column address except for the predetermined number of bits fail, the data cannot be repaired by ECC.

Since any ECC technology has limitations on repairing the stored storage bits, such as cell to cell short (cell to cell short), word line direction failure (for example, floating word line, word line short-circuit to bit line, etc. ), etc., the memory storage device may experience irreparable errors. After the memory storage device has been sold to the customer and is in normal operation, the bit failure must be automatically repaired within the specified time period predetermined by its product specifications, and the bit failure may not exceed the maximum capacity of the ECC scheme used . Such problems can be fatal for memory storage devices that require high reliability. Therefore, once the memory storage device is in normal operation after being sold to the user, if the faulty bit can be automatically detected and physically repaired, the probability of the fault can be greatly reduced.

One way to repair fault bits is to use redundant memory blocks to store data and addresses after a failure attempt. However, such solutions will often involve reading data and/or writing data through the data line. When integrated into an existing architecture, this type of solution will have difficulties because the data line is not only used by redundant storage blocks, but also used by normal operations whenever a write command is received.

In view of this, the present invention provides a memory storage device with an automatic error repair mechanism and an automatic error repair method used by the memory storage device.

In an embodiment of the present invention, a memory storage device is provided, which includes a connection interface, a memory array, a fuse blowing controller, and a memory control circuit. The connection interface is configured to receive a write command and a word line address associated with the write command. The memory array includes a memory bank, and the memory bank includes an ECC detector, a plurality of memory cells controlled by a word line address, and a plurality of redundant memory cells controlled by a redundant word line address. The fuse blowing controller is configured to receive the word line address to blow the electric fuse of the word line address to activate a plurality of redundant memory cells. The memory control circuit is coupled to the connection interface, the memory array, and the fuse blowing controller, and is configured to: in response to receiving a write command or a read command, perform a write operation or a read operation on a plurality of memory cells; Upon detecting an error from a write operation or a read operation, receive a fault indication from the ECC detector; in response to receiving the fault indication, blow the electric fuse of the word line address to activate a plurality of redundant memory cells; and respond Since the electric fuse has been blown, the data is transmitted from the multiple memory cells to the multiple redundant memory cells through the bit line.

In an embodiment of the present invention, an automatic error repair method used by a memory storage device is provided. The method will include: receiving a write command and a word line address associated with the write command; in response to receiving a write command or a read command, controlling the word line address of the memory array of the memory storage device A plurality of memory cells perform write operations or read operations, where the memory array includes a memory bank, the memory bank includes an ECC detector, a plurality of memory cells, and a plurality of memory cells controlled by redundant word line addresses Redundant memory unit; in response to detecting an error from a write operation or a read operation, a fault indication is received from the ECC detector; in response to receiving a fault indication, the electric fuse of the word line address is blown to activate multiple redundant The remaining memory cells; and in response to the electric fuse has been blown, the data is transmitted from the multiple memory cells to the multiple redundant memory cells through the bit line.

Based on the above, the embodiments of the present disclosure can automatically repair errors without receiving any external commands from the user, and operate independently of any normal function of the memory storage device, so that the automatic error repair mechanism will not generate additional operating time And it will not cause a decrease in memory performance.

In order to make the above-mentioned features and advantages of the present disclosure more obvious and understandable, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

Reference will now be made in detail to the current exemplary embodiment of the present invention, examples of which are shown in the accompanying drawings.

In order to solve the aforementioned problems, the present invention provides a memory storage device with an automatic error repair mechanism and an automatic error repair method. The automatic error repair method will automatically repair physical errors in a seamless manner without the user's knowledge. Increase the reliability of memory storage devices. The memory storage device will use the ECC scheme to perform fault detection and error correction. However, the ECC scheme cannot be used to repair hardware defects, and therefore as long as the failure is due to a physical failure, the failure bit will still exist. After a physical error is detected in one or more units associated with the fault address of the memory storage device, the error can be automatically repaired by using electrical fuse technology without any user Input and user awareness. In addition, the data from the cell at the faulty address will be automatically copied to the redundant cell through the bit line without passing through the data line. In this way, the copy operation will not interfere with the normal operation of the memory storage device. It is worth noting that the bit line refers to the electrical path connected to the unit of the memory storage device, and the data line refers to the electrical path that can gather multiple bit lines and form a data connection between multiple pages.

FIG. 1 shows an exemplary memory storage device 100. The memory storage device 100 may be any rewritable non-volatile memory. The memory storage device 100 includes, but is not limited to, a memory control circuit 130 electrically connected to the connection interface 110, a memory array 150 having an ECC detector, and a fuse blowing controller 170.

In one embodiment, the connection interface 110 is configured to be coupled to components of a host system (not shown) through the Serial Advanced Technology Attachment (SATA) standard. However, the present invention is not limited to this. Thus, the connection interface 110 is configured to receive external input (such as a write command and a word line address associated with the write command).

The memory array 150 includes one or more memory banks, and each memory bank may include an ECC detector 151 and a plurality of memory cells controlled by word line addresses. The memory cell of the word line address may have a plurality of redundant memory cells controlled by the redundant word line address. The fuse blowing controller 170 is configured to receive the word line address to blow the electric fuse of the word line address to activate a plurality of redundant memory cells. The memory control circuit 130 will coordinate among the connection interface 110, the memory array 150, and the fuse blowing controller 170 to perform functions of the memory storage device 100 such as a write operation.

After receiving the write command or the read command, the memory control circuit 130 can coordinate the hardware of the memory storage device to perform a write operation or a read operation on a plurality of memory cells. The ECC detector will then detect whether the write operation or the read operation generates an error. When detecting an error, the ECC detector will send a fault indication to indicate that an error from a write operation or a read operation has been detected. The failure indication is used to trigger an automatic error repair mechanism, and the failure indication may be an ECC failure flag (ECC failure flag). After one or more ECC failures, the ECC detector may send an ECC failure flag. The ECC failure flag can be latched, and the memory control circuit and the fuse blowing controller are activated to implement an automatic error repair mechanism.

Then, the memory control circuit can coordinate the fuse blow controller 170 to blow the electric fuse of the word line address, so as to activate a plurality of redundant memory cells after receiving the fault indication. Subsequently, after the electric fuse has been blown, the memory control circuit 130 can coordinate the data transmission from the multiple memory cells to the multiple redundant memory cells through the bit line. The fusing controller 170 may send a fuse fusing flag indicating that the fusing of the electric fuse of the word line address has been completed. The memory control circuit 130 may then wait for the automatic update command or the self-update command in response to receiving the fusion fuse flag and the ECC failure flag. The memory control circuit 130 can update a plurality of redundant memory cells in response to receiving an automatic update command or a self-update command.

In the case of not transmitting data through the data line, the data is transmitted from multiple memory cells to multiple redundant memories via bit lines. In this way, since another write operation or another read operation may potentially use the same character line, the memory storage device can operate independently of any normal function of the memory storage device, and will not interact with other Operation conflict. After the automatic update command or the self-update command has been detected, the memory control circuit 130 will transfer the data from the multiple memory cells through the word line by directly copying the data from the sense amplifier to the multiple redundant memory cells. Send to multiple redundant memory cells, thereby bypassing the use of data lines.

The present invention also provides an automatic error repair method that is not limited to the steps shown in FIG. 2. Referring to FIG. 2, in step S201, the memory storage device will receive not limited to an active command or a write command and the word line address associated with the write command. The start command or the write command can include a column address, a row address, or a block address. The start command can include a column address or a block address. The write command or the read command may further include a row address. In step S203, the memory storage device will perform a write operation on a plurality of memory cells controlled by the word line addresses of the memory array. In step S205, in response to detecting an error from the write operation, the memory storage device will receive a failure indication from the ECC detector. For example, according to the Joint Electron Tube Engineering Council (JEDEC) standard, the ECC detector will perform ECC operations that may occur during a read operation or a write operation. In addition, the column address can be inserted before the write operation, or the read operation can be accompanied by the column address. In step S207, the memory storage device blows the electric fuse of the word line address to activate a plurality of redundant memory cells. In step S209, the memory storage device will transmit data from the multiple memory cells to the multiple redundant memory cells via bit lines.

In order to further clarify the concept of the present invention as described in FIGS. 1 and 2 and its corresponding written description, the present invention provides several examples to describe the concept of the present invention in more detail. Referring to FIG. 3, in step S301, the memory storage device 100 will receive a read command or a write command to write user data into the location of the memory 150. The write command can include a column address, a row address, or a block address. For example, according to an exemplary embodiment, the write command may be a “start” command that includes a column address to write to a memory cell in a specific column, followed by a row address to write to a specific row of a specific column The'write' command of the memory cell.

In step S302, user data may be encoded under a specific ECC scheme, and then the ECC detector 151 may apply an algorithm of the specific ECC scheme to detect errors. In step S303, assuming that the ECC detector 151 has detected an error after one or more detection attempts, the ECC detector may send a failure indication to the memory control circuit 130. The fault indication can be an ECC fault flag. Alternatively, after the ECC detector 151 has detected an error, one or more writing attempts with a higher writing voltage or a longer writing time may be attempted. If no error is detected, then in step S304, the memory storage device 100 will continue to perform normal operations. However, once the ECC detector 151 has sent a fault indication to the memory control circuit 130, an automatic error repair mechanism will be triggered.

In step S305, assuming that the write operation fails at the row trying to store user data and the address of the memory bank, the memory array 150 will send the fault address from the ECC detector 151. The fault address will be latched by the fault address latch. In step S306, the fault address latch sends the fault address to the fuse blow controller, and in step S311, the fault address latch also sends the fault address to the update address latch. In step S307, the memory control circuit 130 can check whether there are any redundant memory cells that can be used to replace the memory cells of the faulty address. According to an exemplary embodiment, there may be a spare row of redundant memory cells for each existing memory cell. Alternatively, there may be a spare memory bank containing multiple rows of redundant memory cells to potentially replace damaged cell rows. The exact number of spare memory banks or spare rows of redundant memory cells is flexible and can be adjusted based on design considerations.

Assuming that there is no redundant memory unit available for the fault address, in step S312, the memory control circuit 130 will reset the repair function or can resort to alternative solutions to handle the error. Assuming that no redundant memory cell is available for the fault address, in step S308, the fuse blow controller 170 can reset all repair-related actions and return to normal operation. For example, if the failed block does not have any more repair units (for example, redundant columns, redundant blocks, etc.) available, there will be no repair action, so that the repair can be abandoned to allow the memory device to return to its Normal operation. However, if the next failure in another block has been detected by the ECC detector and the repair unit is available, the subsequent repair action will be performed by copying the memory unit from the failed address to the memory corresponding to the redundant word line address Unit to continue.

According to an exemplary embodiment, the fault address is a word line address of a memory cell row that has been determined to contain one or more physical errors, and the memory cell of the word line address is to be replaced with another redundant word The redundant memory unit of the meta-line address. However, after the replacement, the physical address of the redundant word line address will remain the same as the replaced word line address. After the fuse blow controller 170 has blown the fuse of the fault location, the fuse blow controller 170 will send a fuse blow flag indicating that the fuse has blown.

In response to receiving the ECC fault flag and the fuse blown flag, in step S309, the memory control circuit 130 will wait and detect the next automatic update command or self-update command, and the fault address can also be updated through the address generator. Come latch. In step S310, after the automatic update command or the self-update command has been received, the failed address will serve as the update address because the redundant memory unit will undergo an update operation. During this period, the memory previously stored at the failed address The user data in the cell (ie, the word line address) will be copied to the redundant memory cell. According to an exemplary embodiment, assuming that the fault address is a memory cell row controlled by a word line, the user data will be copied from the memory cell row corresponding to the fault address to the redundancy controlled by another word line. The remaining memory cells are in the new row. In other words, during the automatic update command or the self-update command, the data from the faulty word line address is copied to the redundant word line address. After receiving the automatic update command or the self-update command, the ECC failure flag and the fuse blown flag will be disabled. Then, the repair action will be completed.

Based on the provided mechanism, the memory storage device 100 will be able to perform fault detection and automatic error repair simultaneously and continuously, because the repair operation will not occupy the data line. In this way, the memory storage device 100 will be able to operate normally without affecting the normal operation of the memory storage device 100.

Figure 4 and its corresponding written description provide further details of the copy operation. The memory array 150 may have at least but not limited to a plurality of storage blocks 400, wherein a sense amplifier (SA) is connected to each storage block, and each storage block may include one or more memory cell rows. Assuming that the ECC detector 151 has determined that the error occurred in the memory cell controlled by the word line address WL(i) 402 in the storage block 1 401, it is stored in the memory cell corresponding to the word line address WL(i) 402 The user data in the memory cell of will be copied to the memory cell corresponding to the word line address WL(j) 403. The copy operation from a cell controlled by one word line to a redundant cell controlled by another word line is completed by each of the corresponding bit lines, without passing through the data line.

According to an exemplary embodiment, the copy operation may be completed during the automatic update operation or the self-update operation. Generally, during the automatic update operation or the self-update operation, the user data stored in the memory cell controlled by the character line can be first stored in the sense amplifier, and then the user data can be copied back from the sense amplifier The memory cell controlled by the word line to complete the automatic update operation or the self-update operation. However, in this exemplary embodiment, stored in the memory cell corresponding to the word line address WL(i) 402 can be stored in the sense amplifier and then copied to the corresponding word line address WL( j) 403 redundant memory unit. In this way, user data can be copied from a cell controlled by one word line through each of the corresponding bit lines to a redundant cell controlled by another word line, without passing through the data line, enabling error recovery The mechanism will not interfere with the normal operation of the memory storage device 100.

As an example, FIG. 5 shows a timing diagram for copying the data "1" from the address of the defective word line to the redundant word line. As seen in FIG. 5, after the failure has been detected by the ECC detector 151, the voltage of the word line WL(i) corresponding to Cell(y) will be pulled up. Subsequently, when the voltage is pulled high, the sense amplifier S1 and the sense amplifier S2 corresponding to the word line WL(i) and the redundant word line WL(j) will be activated. Since the bit line (BL) voltage 501 at S1 is greater than the bit line bar (BLB) voltage 502, the data to be copied is '1'. After the fuse blowing controller 170 has completed blowing the fuses of the fault address, when the voltage 503 of the redundant word line WL(j) is pulled high, the redundant word line WL(j) is activated. Then, the original storage data 504 stored in the cell controlled by the word line WL(i) is copied to the redundancy controlled by the redundant word line WL(j) through the bit line BL and the bit line sense amplifier BLSA Cell, the redundant cell may be a memory cell corresponding to Cell(y), as the redundant storage data 505 that will also have a value of '1'. Basically after a failure is detected during a read operation or a write operation. After the fault has been detected and repaired, the data copy operation will be performed during the next automatic update operation or self-update operation.

FIG. 6 shows a similar example for copying the data "0" from the address of the defective word line to the redundant word line. As seen in FIG. 6, after the failure has been detected by the ECC detector 151, the voltage of the word line WL(i) corresponding to Cell(x) will be pulled high. Subsequently, when the voltage is pulled high, the sense amplifier S1 and the sense amplifier S2 corresponding to the word line WL(i) and the redundant word line WL(j) will be activated. Since the bit line (BLB) voltage 601 at S1 is greater than the bit line (BL) voltage 602, the data to be copied is '0'. After the fuse blowing controller 170 has completed blowing the fuse of the fault address, when the WL(j) voltage 603 is pulled high, the redundant word line WL(j) is activated. Then, the original storage data 604 stored in the cell controlled by the word line WL(i) is copied to the redundant cell controlled by the redundant word line WL(j) through the bit line and bit line sense amplifier, The redundant cell may be a memory cell corresponding to Cell(x), as the redundant storage data 605 that will also have a value of '0'. After a failure is detected during a read operation or a write operation as described above. After the fault has been detected and repaired, the data copy operation will be performed during the next automatic update operation or self-update operation.

Figure 7 further illustrates the automatic error repair mechanism from the perspective of the hardware diagram. Referring to FIG. 7, the command decoder 702 will receive the'start' command, the'start' command is a write command for the column address, and the address buffer 701 will receive the user data to write the user data to the memory array 704 The column address in one of the columns of the memory bank, the memory array 704 is an example of the memory array 150 described previously. The column address latch 703 will then receive the column address write command from the command decoder 702 and the column address from the address buffer 701. Then, the row address will be sent to the memory array 704 to write the user data into the row address.

Assuming that one of the ECC detectors of the memory array 704 has detected an error in the user data stored in one or more cells of the corresponding row address, after one or more detection attempts, the ECC detector can The ECC fault flag is sent to include address buffer 701, command decoder 702, column address latch 703, fault address latch 705, update address latch 707, update address counter 708, and automatic update or self-update The update address latch 707 of the memory control circuit 130 of the control circuit 709. Alternatively, one or more write attempts with higher write voltage or longer write time can be tried to fix the error. If the error cannot be repaired, it may mean that the error is of a physical nature and therefore cannot be repaired. When one of the ECC detectors sends an ECC failure flag to trigger the automatic error repair mechanism, the ECC detector will also send the failure address to the failure address latch 705. In response to receiving the fault address, the fault address latch 705 will send the fault address to the update address latch 707 and the fuse blow controller 706 (ie 170) to blow the electric fuse corresponding to the fault address. After the fuse blow controller 170 has blown the fuse of the fault location, the fuse blow controller 170 will send a fuse blow flag indicating that the fuse has blown.

In response to receiving the ECC failure flag and the fuse blown flag, the update address latch 707 will wait and detect the next automatic update command or self-update command, which may occur at regular intervals determined by the update address counter 708, Or it may appear after receiving the update command from the command decoder 702 to the automatic update or self-update control circuit 709. After the automatic update or self-update command from the update address counter 708 has been received by the update address latch 707, the redundant memory cell will undergo an update operation. Address) the user data in the memory unit will be copied to the redundant memory unit. Since it is assumed that the fault address is the memory cell row controlled by the word line, the user data will be copied from the memory cell row controlled by the word line to the redundant memory cell row controlled by the redundant word line . After receiving the automatic update command or the self-update command, the ECC failure flag and the fuse blown flag will be disabled.

FIG. 8 shows that a data copy operation during a bulk data movement (backup) operation is used to copy data from block 1 to a redundant memory location (for example, backup 01/12). As shown in FIG. 8, block 1 includes at least three columns of word lines WL(i), redundant word lines WL(j), word lines WL(k), and redundant word lines WL(1). Of multiple memory cells. The data of each row of the multiple memory cells can be output through the bit line connected to the sense amplifier. Assuming that the ECC detector has detected a defective memory cell controlled by the word line WL(i) as a fault detection WL during a read operation or a write operation, the fuse controller will activate the redundant memory cell as a repair WL The column of memory cells controlled by the remaining word line WL(1). In the future, the data of the memory cell controlled by the free word line WL(i) will be copied to the memory cell controlled by WL(1). After the fault has been detected and repaired, the data copy operation will be performed during the next automatic update operation or self-update operation.

It is worth noting that although an automatic error repair mechanism is provided on a row basis as an example, the present invention is not limited to repair on a per column basis, because the automatic error repair mechanism can also be used for each row (column) Repair on a basis or on a block basis.

In summary, the present invention is suitable for implementation of memory storage devices such as dynamic random access memory (DRAM), can automatically repair errors without receiving any external commands from the user, and is independent of any memory storage device. Normal function operation, so that the automatic error repair mechanism will not generate additional operating time and will not cause memory performance degradation.

It will be apparent to those skilled in the art that various modifications and changes can be made to the structure of the disclosed embodiments without departing from the scope or spirit of the present invention. In view of the foregoing, it is hoped that the present invention covers the modifications and changes of the present invention that fall within the scope of the appended claims and their equivalents.

100: Memory storage device 110: Connection interface 130: Memory control circuit 150, 704: memory array 151: ECC detector 170, 706: Fuse blown controller 400: storage block 501, 602: bit line voltage 502, 601: bit line voltage 503, 603: WL(j) voltage 504, 604: Original storage data 505, 605: Redundant storage of data 701: address buffer 702: Command Decoder 703: column address latch 705: Fault address latch 707: update address latch 708: update address counter 709: Automatic update or self-update control circuit 401: Storage Block 1 402: Character line address WL(i) 403: Character line address WL(j) S1, S2, SA: sense amplifier WL(i), WL(k): character line WL(j), WL(1): Redundant character line BL: bit line BLB: bit line BLSA: bit line sense amplifier S201, S203, S205, S207, S209, S301, S302, S303, S304, S305, S306, S307, S308, S309, S310, S311, S312, S313, S314, S315, S316, S317, S318, S319: steps

FIG. 1 is a block diagram of a memory storage device with an automatic error repair mechanism in this embodiment. FIG. 2 is a flowchart of the automatic error repair method used by the memory storage device in this embodiment. FIG. 3 is a flowchart showing the automatic error repair method in further detail in this embodiment FIG. 4 is an example of damage repair through electric fuse technology in this embodiment. FIG. 5 is a timing diagram of the copy function of copying data "1" from the faulty word line address to the redundant word line address in this embodiment. FIG. 6 is a timing diagram of the copy function of copying data "0" from the faulty word line address to the redundant word line address in this embodiment. FIG. 7 is a block diagram of a memory storage device with an automatic error repair mechanism in this embodiment. FIG. 8 shows the transfer of data from the memory cell controlled by the word line (each of which has been detected as a fault through the perspective of the bit lines) in the present embodiment to the redundant memory controlled by the redundant word line Examples in the unit.

S201, S203, S205, S207, S209: steps

Claims (11)

A memory storage device includes: A connection interface configured to receive a write command or a read command and a character line address associated with the write command or the read command; The memory array includes a memory bank including an error correction code (ECC) detector, a plurality of memory cells controlled by a word line address, and a plurality of memory cells controlled by a redundant word line address Redundant memory unit; A fuse blowing controller configured to receive the word line address to blow the electric fuse of the word line address to activate the plurality of redundant memory cells, and A memory control circuit, coupled to the connection interface, the memory array, and the fuse blowing controller, and configured to: In response to receiving the write command or the read command, perform a write operation or a read operation on the plurality of memory cells; In response to detecting an error from the write operation or the read operation, receiving a failure indication from the error correction code detector; In response to receiving the failure indication, blowing the electric fuse of the word line address to activate the plurality of redundant memory cells; and In response to the electric fuse being blown, data is transmitted from the plurality of memory cells to the plurality of redundant memory cells through a bit line. The memory storage device according to claim 1, wherein transmitting the data from the plurality of memory cells to the plurality of redundant memory cells through the bit line includes: Detect automatic update commands; and By copying the data from the sense amplifier to the plurality of redundant memory cells, the data is transferred from the plurality of memory cells to the plurality of redundant memory cells through the bit line . The memory storage device according to claim 2, wherein transmitting the data from the plurality of memory cells to the plurality of redundant memory cells through the bit line further includes: The data is transmitted from the plurality of memory cells to the plurality of redundant memory cells through the bit line without transmitting the data through a data line. The memory storage device according to claim 1, wherein the error correction code detector is configured to: Perform error correction code check; In response to the error correction code check failure, repair the word line associated with the word line address; and In response to the failure to repair the data, the failure indication is sent to the memory control circuit. The memory storage device according to claim 4, wherein sending the failure indication to the memory control circuit in response to failure to repair the data includes: In response to failure to repair the data, the word line address and error correction code failure flag are sent to the memory control circuit. The memory storage device according to claim 5, wherein the fuse blowing controller is further configured to: Sending a fuse blowing flag indicating that blowing of the electric fuse of the word line address has been completed. The memory storage device according to claim 6, wherein the memory control circuit is further configured to: In response to receiving the fuse blown flag and the error correction code failure flag, waiting for an automatic update command or a self-update command. The memory storage device according to claim 7, wherein the memory control circuit is further configured to: In response to receiving the automatic update command or the self-update command, the plurality of redundant memory cells are updated. The memory storage device according to claim 5, wherein the memory control circuit further includes: The update address latch is configured to receive the error correction code failure flag and the word line address for performing the update operation of the plurality of redundant memory cells. The memory storage device according to claim 1, wherein the plurality of redundant memory cells and the plurality of memory cells have the same column address. An automatic error repair method used by a memory storage device, the method comprising: Receiving a write command or a read command and a word line address associated with the write command or the read command; In response to receiving the write command or the read command, a write operation or a read operation is performed on a plurality of memory cells controlled by the word line address of the memory array of the memory storage device, wherein the The memory array includes a memory bank, the memory bank including an error correction code (ECC) detector, the plurality of memory cells, and a plurality of redundant memory cells controlled by redundant word line addresses; In response to detecting an error from the write operation or the read operation, receiving a failure indication from the error correction code detector; In response to receiving the failure indication, blowing the electric fuse of the word line address to activate the plurality of redundant memory cells; and In response to the electric fuse being blown, data is transmitted from the plurality of memory cells to the plurality of redundant memory cells through a bit line.

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