DE60228809D1 - Speicherschaltung mit komprimierter Testfunktion - Google Patents

Speicherschaltung mit komprimierter Testfunktion

Info

Publication number
DE60228809D1
DE60228809D1 DE60228809T DE60228809T DE60228809D1 DE 60228809 D1 DE60228809 D1 DE 60228809D1 DE 60228809 T DE60228809 T DE 60228809T DE 60228809 T DE60228809 T DE 60228809T DE 60228809 D1 DE60228809 D1 DE 60228809D1
Authority
DE
Germany
Prior art keywords
memory circuit
test function
compressed test
compressed
function
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60228809T
Other languages
English (en)
Inventor
Shinya Fujioka
Waichiro Fujieda
Kota Hara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Semiconductor Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE60228809D1 publication Critical patent/DE60228809D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/40—Response verification devices using compression techniques
DE60228809T 2001-11-29 2002-10-21 Speicherschaltung mit komprimierter Testfunktion Expired - Lifetime DE60228809D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001363871A JP3874653B2 (ja) 2001-11-29 2001-11-29 圧縮テスト機能を有するメモリ回路

Publications (1)

Publication Number Publication Date
DE60228809D1 true DE60228809D1 (de) 2008-10-23

Family

ID=19174137

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60228809T Expired - Lifetime DE60228809D1 (de) 2001-11-29 2002-10-21 Speicherschaltung mit komprimierter Testfunktion

Country Status (7)

Country Link
US (1) US6731553B2 (de)
EP (1) EP1316966B1 (de)
JP (1) JP3874653B2 (de)
KR (1) KR100822980B1 (de)
CN (1) CN1252730C (de)
DE (1) DE60228809D1 (de)
TW (1) TW594777B (de)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100527535B1 (ko) * 2003-04-17 2005-11-09 주식회사 하이닉스반도체 입출력 압축 회로
KR100541048B1 (ko) * 2003-06-16 2006-01-11 삼성전자주식회사 반도체 메모리 장치 및 이 장치의 테스트 방법
JP2005332446A (ja) * 2004-05-18 2005-12-02 Fujitsu Ltd 半導体メモリ
US7308598B2 (en) * 2004-11-04 2007-12-11 International Business Machines Corporation Algorithm to encode and compress array redundancy data
US7420847B2 (en) * 2004-12-14 2008-09-02 Sandisk Corporation Multi-state memory having data recovery after program fail
US7120051B2 (en) * 2004-12-14 2006-10-10 Sandisk Corporation Pipelined programming of non-volatile memories using early data
JP5011818B2 (ja) 2006-05-19 2012-08-29 富士通セミコンダクター株式会社 半導体記憶装置及びその試験方法
US7596729B2 (en) * 2006-06-30 2009-09-29 Micron Technology, Inc. Memory device testing system and method using compressed fail data
JP2008097715A (ja) * 2006-10-12 2008-04-24 Elpida Memory Inc 半導体メモリ及びメモリモジュール
JP5181698B2 (ja) 2008-01-30 2013-04-10 富士通セミコンダクター株式会社 半導体メモリおよび半導体メモリの製造方法
JP2009266317A (ja) 2008-04-25 2009-11-12 Elpida Memory Inc 半導体記憶装置、およびデータ縮約テスト方法
JP2012038377A (ja) 2010-08-05 2012-02-23 Elpida Memory Inc 半導体装置及びその試験方法
US8811101B2 (en) * 2011-02-21 2014-08-19 SK Hynix Inc. SIP semiconductor system
US10720197B2 (en) * 2017-11-21 2020-07-21 Samsung Electronics Co., Ltd. Memory device for supporting command bus training mode and method of operating the same

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2974219B2 (ja) * 1990-08-02 1999-11-10 三菱電機株式会社 半導体記憶装置のテスト回路
JPH04328399A (ja) 1991-04-26 1992-11-17 Nippon Telegr & Teleph Corp <Ntt> テスト機能を有する半導体メモリ
JP3753190B2 (ja) * 1995-04-26 2006-03-08 三菱電機株式会社 半導体装置
JP3774500B2 (ja) * 1995-05-12 2006-05-17 株式会社ルネサステクノロジ 半導体記憶装置
KR100319887B1 (ko) * 1999-05-04 2002-01-10 윤종용 프로그래머블 출력핀 지정 수단을 구비하는 반도체 메모리장치 및 이의 테스트 모드시의 독출방법
JP3945939B2 (ja) * 1999-05-31 2007-07-18 富士通株式会社 圧縮テスト可能なメモリ回路
US6324087B1 (en) * 2000-06-08 2001-11-27 Netlogic Microsystems, Inc. Method and apparatus for partitioning a content addressable memory device
JP2001297600A (ja) * 2000-04-11 2001-10-26 Mitsubishi Electric Corp 半導体集積回路およびそのテスト方法

Also Published As

Publication number Publication date
TW594777B (en) 2004-06-21
JP3874653B2 (ja) 2007-01-31
KR100822980B1 (ko) 2008-04-16
CN1252730C (zh) 2006-04-19
EP1316966B1 (de) 2008-09-10
EP1316966A3 (de) 2006-03-22
US20030099143A1 (en) 2003-05-29
EP1316966A2 (de) 2003-06-04
US6731553B2 (en) 2004-05-04
KR20030044782A (ko) 2003-06-09
CN1421868A (zh) 2003-06-04
JP2003168299A (ja) 2003-06-13

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Legal Events

Date Code Title Description
8327 Change in the person/name/address of the patent owner

Owner name: FUJITSU MICROELECTRONICS LTD., TOKYO, JP

8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: FUJITSU SEMICONDUCTOR LTD., YOKOHAMA, KANAGAWA, JP

8328 Change in the person/name/address of the agent

Representative=s name: SEEGER SEEGER LINDNER PARTNERSCHAFT PATENTANWAELTE