DE60204749D1 - Abtast- und Halteschaltung - Google Patents

Abtast- und Halteschaltung

Info

Publication number
DE60204749D1
DE60204749D1 DE60204749T DE60204749T DE60204749D1 DE 60204749 D1 DE60204749 D1 DE 60204749D1 DE 60204749 T DE60204749 T DE 60204749T DE 60204749 T DE60204749 T DE 60204749T DE 60204749 D1 DE60204749 D1 DE 60204749D1
Authority
DE
Germany
Prior art keywords
sample
hold circuit
hold
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60204749T
Other languages
English (en)
Other versions
DE60204749T2 (de
Inventor
Shoji Kawahito
Daisuke Miyazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Technology Academic Research Center
Original Assignee
Semiconductor Technology Academic Research Center
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Technology Academic Research Center filed Critical Semiconductor Technology Academic Research Center
Application granted granted Critical
Publication of DE60204749D1 publication Critical patent/DE60204749D1/de
Publication of DE60204749T2 publication Critical patent/DE60204749T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/05—Digital input using the sampling of an analogue quantity at regular intervals of time, input from a/d converter or output to d/a converter
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C27/00—Electric analogue stores, e.g. for storing instantaneous values
    • G11C27/02—Sample-and-hold arrangements
    • G11C27/024—Sample-and-hold arrangements using a capacitive memory element
    • G11C27/026—Sample-and-hold arrangements using a capacitive memory element associated with an amplifier
DE60204749T 2001-11-21 2002-11-18 Abtast- und Halteschaltung Expired - Lifetime DE60204749T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2001356081A JP3497495B2 (ja) 2001-11-21 2001-11-21 サンプルホールド回路
JP2001356081 2001-11-21

Publications (2)

Publication Number Publication Date
DE60204749D1 true DE60204749D1 (de) 2005-07-28
DE60204749T2 DE60204749T2 (de) 2006-04-27

Family

ID=19167669

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60204749T Expired - Lifetime DE60204749T2 (de) 2001-11-21 2002-11-18 Abtast- und Halteschaltung

Country Status (6)

Country Link
US (1) US6700417B2 (de)
EP (1) EP1315172B1 (de)
JP (1) JP3497495B2 (de)
KR (1) KR100494273B1 (de)
DE (1) DE60204749T2 (de)
TW (1) TW578158B (de)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2395895A1 (en) * 2002-08-12 2004-02-12 Ralph Dickson Mason Method for increased input isolation in sampling gates
KR100606557B1 (ko) 2004-06-05 2006-07-31 고려대학교 산학협력단 정궤환 증폭기를 안정화시키기 위한 샘플-앤-홀드 증폭기
US7167029B2 (en) * 2005-01-19 2007-01-23 Atmel Corporation Sampling and level shifting circuit
US7759902B2 (en) 2005-01-19 2010-07-20 Atmel Corporation Single chip microcontroller including battery management and protection
US7113116B2 (en) * 2005-01-26 2006-09-26 Analog Devices, Inc. Sample and hold apparatus
US7319574B2 (en) * 2005-05-23 2008-01-15 Eaton Corporation Arc fault detection apparatus, method and system for an underground electrical conductor
US7598896B2 (en) 2005-09-07 2009-10-06 National University Corporation Shizuoka University A/D converter with noise cancel function
DE102006014925B3 (de) * 2006-03-30 2007-09-27 Infineon Technologies Ag Schaltungsanordnung mit einer Abtast-Halte-Einrichtung und Verfahren zur Signalverarbeitung in einer Abtast-Halte-Einrichtung
US7724042B2 (en) * 2007-07-06 2010-05-25 Texas Instruments Incorporated Reducing power consumption in an amplification stage driving a sample and hold circuit while maintaining linearity
KR100893392B1 (ko) * 2007-10-18 2009-04-17 (주)엠씨테크놀로지 전압 증폭 출력 회로 및 이를 이용하는 액정 표시 장치의구동 장치
JP4505027B2 (ja) 2008-05-08 2010-07-14 株式会社半導体理工学研究センター サンプルホールド回路及びａ／ｄ変換装置
JP5054064B2 (ja) * 2009-05-08 2012-10-24 株式会社豊田中央研究所 ホールド回路
EP2541213B1 (de) * 2011-07-01 2017-03-08 EM Microelectronic-Marin SA Verfahren zur Reduzierung der Nichtlinearität beim Messen eines physikalischen Parameters, und elektronischer Schaltkreis zu dessen Umsetzung
US8816887B2 (en) 2012-09-21 2014-08-26 Analog Devices, Inc. Sampling circuit, a method of reducing distortion in a sampling circuit, and an analog to digital converter including such a sampling circuit
JP6675882B2 (ja) * 2016-02-29 2020-04-08 エイブリック株式会社 スイッチドキャパシタ入力回路及びスイッチドキャパシタアンプ及びスイッチドキャパシタ電圧比較器
KR101731032B1 (ko) * 2016-06-14 2017-04-27 주식회사 이노액시스 고속 충방전이 가능한 소스 드라이버
CN111512557B (zh) * 2017-12-22 2023-11-03 瑞典爱立信有限公司 时间交错模数转换器
US11936346B2 (en) * 2021-04-15 2024-03-19 Texas Instruments Incorporated Programmable gain low noise amplifier

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0721958B2 (ja) * 1988-05-02 1995-03-08 日本電気株式会社 サンプル・ホールド増幅回路
US5298801A (en) * 1991-09-11 1994-03-29 U.S. Philips Corporation Track-and-hold circuit
US5689201A (en) * 1995-08-08 1997-11-18 Oregon State University Track-and-hold circuit utilizing a negative of the input signal for tracking
KR100190530B1 (ko) * 1996-10-09 1999-06-01 윤종용 아날로그-디지탈 변환장치의 샘플앤드홀드회로
US5914638A (en) * 1997-06-06 1999-06-22 Omnivision Technologies, Inc. Method and apparatus for adjusting the common-mode output voltage of a sample-and-hold amplifier
KR100284024B1 (ko) * 1997-07-29 2001-03-02 윤종용 저전압 씨모오스 연산 증폭기 회로 및 그것을 구비한 샘플 앤드 홀드 회로
KR20000028306A (ko) * 1998-10-30 2000-05-25 윤종용 셀프 바이어스된 연산 증폭기 회로 및 그것을 구비한 샘플 앤드홀드 회로
US6215337B1 (en) * 1999-01-12 2001-04-10 Qualcomm Incorporated Linear sampling switch
JP2001006384A (ja) * 1999-06-16 2001-01-12 Sharp Corp サンプル／ホールド回路とこれを用いた基準電圧発生回路

Also Published As

Publication number Publication date
JP2003158432A (ja) 2003-05-30
KR100494273B1 (ko) 2005-06-13
KR20030041848A (ko) 2003-05-27
TW578158B (en) 2004-03-01
DE60204749T2 (de) 2006-04-27
US20030122592A1 (en) 2003-07-03
EP1315172A1 (de) 2003-05-28
JP3497495B2 (ja) 2004-02-16
US6700417B2 (en) 2004-03-02
EP1315172B1 (de) 2005-06-22
TW200300557A (en) 2003-06-01

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