DE60030391D1 - Halbleiterschaltung mit Prüfungsfähigkeit - Google Patents

Halbleiterschaltung mit Prüfungsfähigkeit

Info

Publication number
DE60030391D1
DE60030391D1 DE60030391T DE60030391T DE60030391D1 DE 60030391 D1 DE60030391 D1 DE 60030391D1 DE 60030391 T DE60030391 T DE 60030391T DE 60030391 T DE60030391 T DE 60030391T DE 60030391 D1 DE60030391 D1 DE 60030391D1
Authority
DE
Germany
Prior art keywords
semiconductor circuit
testing capability
capability
testing
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60030391T
Other languages
English (en)
Other versions
DE60030391T2 (de
Inventor
Kumi Miyachi
Toshifumi Yamashita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Application granted granted Critical
Publication of DE60030391D1 publication Critical patent/DE60030391D1/de
Publication of DE60030391T2 publication Critical patent/DE60030391T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318536—Scan chain arrangements, e.g. connections, test bus, analog signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318505—Test of Modular systems, e.g. Wafers, MCM's
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
DE60030391T 1999-11-09 2000-07-06 Halbleiterschaltung mit Prüfungsfähigkeit Expired - Lifetime DE60030391T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP31848599A JP3763385B2 (ja) 1999-11-09 1999-11-09 半導体装置
JP31848599 1999-11-09

Publications (2)

Publication Number Publication Date
DE60030391D1 true DE60030391D1 (de) 2006-10-12
DE60030391T2 DE60030391T2 (de) 2007-08-30

Family

ID=18099655

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60030391T Expired - Lifetime DE60030391T2 (de) 1999-11-09 2000-07-06 Halbleiterschaltung mit Prüfungsfähigkeit

Country Status (6)

Country Link
US (1) US7036058B1 (de)
EP (1) EP1099953B1 (de)
JP (1) JP3763385B2 (de)
KR (1) KR100392300B1 (de)
DE (1) DE60030391T2 (de)
TW (1) TW472154B (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004264057A (ja) * 2003-02-12 2004-09-24 Sharp Corp バウンダリスキャンコントローラ、半導体装置、半導体装置の半導体回路チップ識別方法、半導体装置の半導体回路チップ制御方法
CN100427964C (zh) * 2003-08-04 2008-10-22 华为技术有限公司 一种电路板的边界扫描测试方法
DE60314525T2 (de) * 2003-12-17 2008-02-28 Stmicroelectronics Ltd., Almondsbury TAP Zeitmultiplexen mit Abtasttest
EP1706752B1 (de) * 2004-01-13 2008-05-07 Nxp B.V. Jtag-testarchitektur für ein mehrchip-pack
JP4525125B2 (ja) * 2004-03-24 2010-08-18 ソニー株式会社 マルチチップ型半導体装置
KR100630716B1 (ko) 2004-11-11 2006-10-02 삼성전자주식회사 다양한 패턴 데이터를 쓸 수 있는 반도체 메모리 소자 및그 전기적 검사방법
US7650542B2 (en) * 2004-12-16 2010-01-19 Broadcom Corporation Method and system of using a single EJTAG interface for multiple tap controllers
KR100850208B1 (ko) 2007-01-09 2008-08-04 삼성전자주식회사 Ｐｂｔ 장치 및 그 방법
US8621301B2 (en) * 2009-03-04 2013-12-31 Alcatel Lucent Method and apparatus for virtual in-circuit emulation
KR102566994B1 (ko) 2015-12-14 2023-08-14 삼성전자주식회사 멀티 칩 디버깅 방법 및 이를 적용하는 멀티 칩 시스템

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55111151A (en) 1979-02-20 1980-08-27 Nec Corp Integrated circuit device
JP2874248B2 (ja) 1990-02-26 1999-03-24 日本電気株式会社 診断用スキャンパス付き電子回路
JP2627464B2 (ja) 1990-03-29 1997-07-09 三菱電機株式会社 集積回路装置
US5068886A (en) * 1990-06-28 1991-11-26 Monica Lavia Catheter or cannula position indicator for use in hemodynamic monitoring and the like
JPH05322988A (ja) 1992-05-18 1993-12-07 Sony Corp 電子装置の検査方法
US5627842A (en) * 1993-01-21 1997-05-06 Digital Equipment Corporation Architecture for system-wide standardized intra-module and inter-module fault testing
US5621740A (en) * 1993-05-14 1997-04-15 Matsushita Electric Industrial Co., Ltd. Output pad circuit for detecting short faults in integrated circuits
US6006343A (en) * 1993-07-30 1999-12-21 Texas Instruments Incorporated Method and apparatus for streamlined testing of electrical circuits
JP3479653B2 (ja) * 1993-10-15 2003-12-15 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ テスト装置
US5448525A (en) * 1994-03-10 1995-09-05 Intel Corporation Apparatus for configuring a subset of an integrated circuit having boundary scan circuitry connected in series and a method thereof
US6058602A (en) * 1998-09-21 2000-05-09 Integrated Packaging Assembly Corporation Method for encapsulating IC packages with diamond substrate
JPH09186418A (ja) 1995-12-28 1997-07-15 Oki Electric Ind Co Ltd バウンダリスキャンテストにおけるプリント配線板の接続構造
US5808877A (en) * 1996-09-19 1998-09-15 Samsung Electronics Co., Ltd. Multichip package having exposed common pads
US6260165B1 (en) * 1996-10-18 2001-07-10 Texas Instruments Incorporated Accelerating scan test by re-using response data as stimulus data
US6199182B1 (en) * 1997-03-27 2001-03-06 Texas Instruments Incorporated Probeless testing of pad buffers on wafer
US6000051A (en) * 1997-10-10 1999-12-07 Logic Vision, Inc. Method and apparatus for high-speed interconnect testing
US6163867A (en) * 1998-08-28 2000-12-19 Hewlett-Packard Company Input-output pad testing using bi-directional pads

Also Published As

Publication number Publication date
KR20010049778A (ko) 2001-06-15
KR100392300B1 (ko) 2003-07-22
US7036058B1 (en) 2006-04-25
JP3763385B2 (ja) 2006-04-05
DE60030391T2 (de) 2007-08-30
TW472154B (en) 2002-01-11
EP1099953A3 (de) 2001-05-23
EP1099953B1 (de) 2006-08-30
EP1099953A2 (de) 2001-05-16
JP2001135786A (ja) 2001-05-18

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