EP1576672B1 - Transistors mos de puissance en carbure de silicium et procedes de fabrication - Google Patents

Transistors mos de puissance en carbure de silicium et procedes de fabrication Download PDF

Info

Publication number
EP1576672B1
EP1576672B1 EP03799873.9A EP03799873A EP1576672B1 EP 1576672 B1 EP1576672 B1 EP 1576672B1 EP 03799873 A EP03799873 A EP 03799873A EP 1576672 B1 EP1576672 B1 EP 1576672B1
Authority
EP
European Patent Office
Prior art keywords
silicon carbide
region
type
type silicon
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP03799873.9A
Other languages
German (de)
English (en)
Other versions
EP1576672A2 (fr
Inventor
Sei-Hyung Ryu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wolfspeed Inc
Original Assignee
Cree Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cree Inc filed Critical Cree Inc
Priority to EP11167910.6A priority Critical patent/EP2383787B1/fr
Publication of EP1576672A2 publication Critical patent/EP1576672A2/fr
Application granted granted Critical
Publication of EP1576672B1 publication Critical patent/EP1576672B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/8213—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using SiC technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H01L29/7828—Vertical transistors without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide

Definitions

  • the present invention relates to semiconductor devices and the fabrication of semiconductor devices and more particularly, to silicon carbide (SiC) metal-oxide semiconductor field effect transistors (MOSFETs) and the fabrication of such MOSFETs.
  • SiC silicon carbide
  • MOSFETs metal-oxide semiconductor field effect transistors
  • a power MOSFET structure may involve additional processing including, for example, anneals at temperatures of greater than 1500° C for the activation of p-type dopants, for example, p-well/p+ contact/p-Junction Termination Extension (JTE) implants. Such anneals may have detrimental impact on the performance of power MOSFETs fabricated using such techniques.
  • JTE Joint Termination Extension
  • the existing SiC structures can, generally, be divided into three categories: (1) Trench or UMOSFET, (2) Vertical Doubly Implanted MOSFET (DIMOSFET), and ' (3) Lateral Diffused MOSFET (LDMOSFET).
  • the vertical DIMOSFET structure illustrated in Figure 1 , is a variation of the diffused (DMOSFET) structure employed in silicon technology.
  • the p-wells are implanted with A1 or Boron
  • the source regions (n + ) are implanted with nitrogen or phosphorus
  • the p + regions are usually implanted with Al.
  • the implants are activated at temperatures between 1400°C - 1700°C.
  • the contacts to n + layers are made with nickel (Ni) and annealed and the contacts to p + are made by Ni, Ti or Ti/Al. Both contacts are annealed at high temperatures.
  • the gate dielectric is, typically, either thermally grown (Thermal SiO 2 ) or deposited using Low Pressure Chemical Vapor Deposition (LPCVD) technique and subsequently annealed in various ambients.
  • the deposited dielectric may, for example, be SiO 2 or an Oxide/Nitride/Oxide (ONO) stack.
  • the interface states near the conduction band edge tend to trap the otherwise free electrons from the inversion layer leaving a relatively small number of free electrons in the inversion layer. Also the trapped electrons may create negatively charged states at the interface which coulomb scatter the free electrons. The reduced number of free electrons and the increased scattering may reduce the conduction of current from source to drain, which may result in low effective mobility of electrons and a high on-resistance.
  • Several factors have been attributed to the high density of states near the conduction band edge: (1) carbon or silicon dangling bonds, (2) carbon clusters, and (3) Si-Si bonds creating a thin amorphous silicon layer at the interface. See S. T.
  • a further difficulty with DIMOSFETS may be associated with the "JFET" region of the device.
  • a depletion region may be formed in the n drift region around the p-well. This depletion region may effectively make the channel length longer than the p-well junction depth as current flow is provided around the depletion region.
  • a spacer implant be introduced between the p-well regions to alleviate this problem. See Vathulya et al., "A Novel 6H-SiC DMOSFET With Implanted P-Well Spacer", IEEE Electron Device Letters, Vol. 20, No. 7, p. 354, July 1999 .
  • This spacer implant does not extend past the p-well regions and does not significantly reduce the JFET resistance if the depletion region formed at the p-well and the n - drift region interface extends deep into the n - drift region.
  • JP-3034466 relates to a vertical-type double diffused MOSFET.
  • An n-type epitaxial layer is constructed of two layers, with the second layer having a higher impurity concentration than the first.
  • a p-type channel forming region is formed in the second epitaxial layer.
  • US-4,884,113 relates to a double-diffused insulated-gate field effect transistor. Depletion layer preventing regions are formed within a n-type layer. Within these, a p-type impurity layer is formed and n + -type source regions are formed in this layer.
  • a silicon carbide MOSFET unit cell according to the present invention is set out in claim 1, a corresponding method of fabrication is set out in claim 15.
  • a Silicon Carbide MOSFET according to the present invention is set out in claim 13, a corresponding method of fabrication is defined in claim 27.
  • a silicon carbide metal-oxide semiconductor field effect transistor unit cell comprising:
  • the first p-type silicon carbide region is implanted with aluminium.
  • the n-type depletion layer reducing region is provided by an epitaxial layer of silicon carbide on the n-type silicon carbide drift layer.
  • the first p-type region is provided in but not through the epitaxial layer of silicon carbide.
  • the n-type depletion layer reducing region is provided by an implanted n-type region in the drift layer.
  • the n-type depletion layer reducing region has a thickness of from 0.5 ⁇ m.
  • the n-type limiting region has a carrier concentration of from 1 x 10 15 to 5 x 10 17 cm -3 .
  • an n-type epitaxial layer is provided on the first p-type region and a portion of the first n-type region.
  • the epitaxial layer is between the first n-type silicon carbide region and the first p-type silicon carbide region and the oxide layer.
  • a second p-type silicon carbide region is provided within the first p-type silicon carbide region and adjacent the first n-type silicon carbide region.
  • a silicon carbide device in the form of a MOSFET is formed of unit cells as defined above.
  • the first regions of p-type silicon carbide are spaced apart and have peripheral edges that define a region of n-type silicon carbide therebetween.
  • First regions of n-type silicon carbide having a carrier concentration greater than a carrier concentration of the drift layer are provided in the first regions of p-type silicon carbide and are spaced apart from the peripheral edges of the first regions of p-type silicon carbide.
  • an epitaxial layer of silicon carbide is provided on the first p-type regions.
  • an n-type silicon carbide layer with a higher carrier concentration than the drift layer is provided between the drift layer and the drain contact.
  • the n-type silicon carbide layer may be an n-type silicon carbide substrate.
  • second p-type silicon carbide regions are provided within the first p-type silicon carbide regions.
  • the depletion layer reducing regions of n-type silicon carbide have a thickness of from about 0.5 ⁇ m to about 1.5 ⁇ m and a carrier concentration of from about 1x 10 15 to about 5 x 10 17 cm -3 .
  • Embodiments of the present invention provide silicon carbide MOSFETs and/or methods of fabricating silicon carbide MOSFETs which may reduce on-state resistance of a device. While the inventors do not wish to be bound by any theory of operation, it is believed that by reducing the depletion region beneath the p-well of the MOSFET, the length of the current path may be reduced and, therefore, the on-state resistance of the device may be reduced over that of a similarly sized conventional MOSFET. Furthermore, by reducing the depletion region in the JFET gap, device areas may be reduced by reducing the size of the JFET gap.
  • n - drift layer 12 of silicon carbide is on an optional n + layer 10 of silicon carbide.
  • the n - drift layer 12 may be a substrate or an epitaxial layer of silicon carbide and may, for example, be 4H polytype silicon carbide.
  • the n - drift layer 12 has a carrier concentration of from about 10 14 to about 5 ⁇ 10 16 cm -3 .
  • the drift layer 12 has a thickness of from about 5 ⁇ m to about 150 ⁇ m.
  • the n + layer 10 may be an implanted layer or region, an epitaxial layer or a substrate.
  • the n + layer has a carrier concentration of from about 10 18 to about 10 21 cm -3 .
  • a region of higher carrier concentration n-type silicon carbide 26 is provided on the drift layer 12 .
  • the region 26 has a higher carrier concentration than the carrier concentration of the drift layer 12 and provides an embodiment of a JFET depletion layer reducing region 26a between a floor 20a of the p-wells 20 and the drift layer 12 .
  • the region 26 may be provided by epitaxial growth or by implantation. In certain embodiments of the present invention, the region 26 has thickness of from about 0.5 ⁇ m to about 1.5 ⁇ m. Also, the region 26 may have a carrier concentration of from about 10 15 to about 5 ⁇ 10 17 cm -3 . The region 26 may have a uniform carrier concentration or a nonuniform carrier concentration.
  • spaced apart regions of p-type silicon carbide provide p-wells 20 in the region 26 .
  • the p-wells 20 are implanted so as to extend into but not through the region 26 such that a region of higher carrier concentration n-type silicon carbide 26a is provided between a floor 20a of the p-wells 20 and the drift layer 12 .
  • the portion of the region 26 in the gap 21 between the p-wells 20 has a higher carrier concentration than the drift layer 12 .
  • the portion of the region 26 in the gap 21 between the p-wells 20 has the same carrier concentration as the drift layer 12 .
  • the portion of the region 26 adjacent the sidewalls of the p-wells 20 may have the same or higher carrier concentration than the drift layer 12 while the portion 26a of the region 26 adjacent the floor 20a of the p-wells 20 has a higher carrier concentration than the drift layer 12 .
  • the p-wells 20 have a carrier concentration of from about 10 16 to about 10 19 cm -3 .
  • the p-wells 20 may provide a junction depth of from about 0.3 ⁇ m to about 1.2 ⁇ m.
  • FIG. 2B An example of embodiments of the present invention where the gap 21 and the area beneath the p-wells 20 have different carrier concentrations is illustrated in Figure 2B .
  • regions 26' are provided beneath the floor of the p-wells 20 and between the p-wells 20 and the drift layer 12 to provide the JFET depletion layer reducing regions.
  • the drift layer 12 is provided in the gap 21 between the p-wells 20 .
  • the regions 26' may be provided, for example, by implanting n-type regions 26' in the drift layer 12 using a mask and implanting the p-wells 20 so that the depth of the p-wells 20 in the drift layer 12 is less than the greatest depth of the regions 26' in the drift layer 12 .
  • an n-well could be formed in the drift layer 12 and the p-wells 20 formed in the n-well.
  • the p-wells 20 are implanted with A1 and annealed at a temperature of at least about 1500°C.
  • suitable p-type dopant may be utilized in providing the p-wells 20 .
  • the doping profile of the p-wells 20 may be a substantially uniform profile, a retrograde profile (increasing doping with depth) or the p-wells may be totally buried (with some n-type silicon carbide above the p-wells 20 ).
  • the p-wells 20 may have carrier concentrations of from about 1x10 16 to about 1x10 19 cm -3 and may extend into the region 26 or the n - drift layer 12 from about 0.3 ⁇ m to about 1.2 ⁇ m. While various p-type dopants may be utilized, A1 is utilized in some embodiments because Boron tends to diffuse over several microns when annealed at temperatures exceeding 1500°C. Therefore, it may be difficult to control the precise gap between the p-wells 20 (the region which may be referred to as the JFET region 21 ) and/or the depth of the p-wells 20 . If this gap is too high, the field in the gate oxide can become too high when the device is in the blocking state.
  • gaps of from about 1 ⁇ m to about 10 ⁇ m are preferred.
  • the particular gap utilized for a given device may depend upon the desired blocking voltage and on-state resistance of the device.
  • Regions of n + silicon carbide 24 and, optionally, regions of p + silicon carbide 22 are disposed within the p-wells 20 .
  • the regions of n + silicon carbide 24 are spaced from about 0.5 ⁇ m to about 5 ⁇ m from the edge of the p-wells 20 adjacent the JFET region 21 .
  • the regions of n + silicon carbide 24 may have a doping concentration of from about 5 ⁇ 10 18 cm -3 to about 10 21 cm -3 and may extend to a depth of from about 0.1 ⁇ m to about 0.8 ⁇ m into the p-wells 20 but are shallower than the depth of the p-wells 20 .
  • Suitable n-type dopants include phosphorous and nitrogen or other n-type dopants known to those of skill in the art.
  • the optional regions of p + silicon carbide 22 may be adjacent the regions of n + silicon carbide 24 and opposite the edge of the p-wells 20 .
  • the regions of p + silicon carbide 22 may have a doping concentration of from about 5 X 10 18 cm -3 to about 10 21 cm -3 and may extend to a depth of from about 0.2 ⁇ m to about 1.2 pm into the p-wells 20 but are shallower than the depth of the p-wells 20.
  • the gate oxide 28 extends at least between the n + regions of silicon carbide 24 and has a gate contact 32 thereon.
  • the gate oxide 28 may be either a thermally grown oxide with an NO or N 2 O anneal or Oxide/Nitride/Oxide (ONO) where the first oxide is a thermal oxide followed by an NO or N 2 O anneal.
  • the gate contact material may be any suitable contact material.
  • the gate contact material is molybdenum or p-type polysilicon. P-type polysilicon may be suitable in some embodiments because of its high work function.
  • the thickness of the gate oxide 28 may depend on the work function of the material of the gate contact 32 . However, in general, thicknesses of from about 100 ⁇ to about 5000 ⁇ are preferred.
  • Source contacts 30 are formed of nickel (Ni), titanium (Ti), platinum (Pt) or aluminum (Al), combinations thereof and/or other suitable contact materials and may be annealed at temperatures of from about 600 °C to about 1000 °C, for example, 825 °C, so as to provide an ohmic contact to both the p + regions 22 and the n + regions 24 .
  • the drain contact 34 may be Ni or Ti or other such suitable material for forming an ohmic contact to n-type silicon carbide.
  • differing or the same contact materials may be utilized to contact the p + regions 22 and the n + regions 24 .
  • one or more metal overlayers may be provided on one or more of the contacts. Techniques and materials for providing metal overlayers are known to those of skill in the art and, therefore, are not discussed further herein.
  • Figure 3 illustrates further alternative embodiments of the present invention which utilize a re-grown epitaxial layer.
  • a thin layer of silicon carbide 27 is re-grown on the p-wells 20 after implanting and annealing the p-wells and extends across the region 26 in the JFET region.
  • Embodiments such as illustrated in Figure 2B may also be modified to include such a re-grown epitaxial layer that is re-grown on the p-wells 20 after implanting and annealing the p-wells and extends across the drift layer 12 in the JFET region.
  • the n + regions of silicon carbide 24 may be formed through the re-grown silicon carbide layer 27 and/or prior to re-growth.
  • the re-grown silicon carbide layer 27 may have a thickness of from about 0.05 ⁇ m to about 1 ⁇ m in come embodiments.
  • the re-grown silicon carbide layer 27 may be n-type silicon carbide.
  • the re-grown silicon carbide layer 27 has a doping of from about 5 X 10 14 cm -3 to about 5 X 10 17 cm -3 .
  • a contact window is provided through the silicon carbide layer 27 to provide a contact 30' to the optional p + regions 22 or to the p-wells 20 if the p + regions 22 are not present.
  • the contact 30' may be made of any suitable material for forming an ohmic contact as described above.
  • Figures 2A, 2B and 3 illustrate embodiments of the present invention as discrete devices, as will be appreciated by those of skill in the art, Figures 2A, 2B and 3 may be considered unit cells of devices having multiple cells. Thus, for example, additional unit cells may be incorporated into the devices illustrated in Figures 2A, 2B and 3 by dividing the device along its central axis (illustrated as the vertical axis in Figures 2A, 2B and 3 ) and rotating the divided device about an axis of the periphery of the devices illustrated in Figures 2A, 2B and 3 (the vertical edges of the devices illustrated in Figures 2A, 2B and 3 ). Accordingly, embodiments of the present invention include devices such as those illustrated in Figures 2A, 2B and 3 as well as devices having a plurality of unit cells incorporating the JFET depletion layer reducing regions illustrated in Figures 2A, 2B and 3 .
  • an n-type silicon carbide epitaxial layer 26 is formed on the drift layer 12.
  • the n-type epitaxial layer 26 may be formed to the thickness and doping levels described above.
  • a mask 100 is formed and patterned on the n-type epitaxial layer 26 and impurities are implanted into the n-type epitaxial layer 26 to provide the p-wells 20.
  • the implanted impurities may be implanted to the depths described above and to provide the desired carrier concentrations when activated.
  • the drift layer 12 may be provided on an n + silicon carbide substrate. In such embodiments, the n + layer described below may be provided by the substrate.
  • the mask 100 is removed and a mask 104 is formed and patterned and n-type impurities are implanted utilizing the mask 104 to provide the n + regions 24 .
  • the mask 104 is formed to provide the desired spacing between the periphery of the p-wells 20 and the n + regions 24 that defines the channel length of the shorting channels 26 .
  • Suitable n-type impurities include nitrogen and phosphorous.
  • the impurities may be implanted to provide the dimensions and carrier concentrations of the n + regions 24 described herein.
  • Figure 4D illustrates the formation of the optional p + regions.
  • the mask 104 is removed and a mask 106 is formed and patterned and p-type impurities are implanted utilizing the mask 106 to provide the p + regions 22 .
  • the p-type impurities may be implanted to provide the dimensions and carrier concentrations of the p + regions 22 described herein.
  • the p-type impurity is aluminum, however, other suitable p-type impurities may also be utilized.
  • Figure 4E illustrates the removal of the mask 106 as well as the creation of the n + layer 10, which may be formed by a backside implant of n-type impurities in a substrate or may be an epitaxial layer or the substrate itself and may be formed prior to Figure 4A .
  • the structure is also annealed at a temperature of from about 1200 °C to about 1800 °C for durations from about 30 seconds to about 24 hours to activate the implanted p-type and n-type impurities.
  • the structure may be capped with a dielectric layer, such as SiO 2 or Si 3 N 4 , to protection the structure during annealing.
  • the gate oxide is annealed after formation to improve the SiC/SiO 2 interface, the activation of such impurities may be provided by such anneal.
  • Figure 4F illustrates the formation of the gate oxide 28 .
  • the gate oxide may be thermally grown and may be a nitrided oxide and/or may be other oxides.
  • the nitrided oxide may be any suitable gate oxide, however, in certain embodiments, SiO 2 , oxynitride or ONO are utilized. Formation of the gate oxide or the initial oxide of an ONO gate dielectric may be followed by an anneal in N 2 O or NO so as to reduce defect density at the SiC/oxide interface.
  • the gate oxide is formed either by thermal growth or deposition and then annealed in an N 2 O environment at a temperature of greater than about 1100 °C and flow rates of from about 2 to about 8 SLM which may provide initial residence times of the N 2 O of from about 11 to about 45 seconds.
  • N 2 O environment at a temperature of greater than about 1100 °C and flow rates of from about 2 to about 8 SLM which may provide initial residence times of the N 2 O of from about 11 to about 45 seconds.
  • Such formation and annealing of an oxide layer on silicon carbide are described in commonly assigned United States Patent Application Serial No. 09/834,283 , entitled “Method of N 2 O Annealing an Oxide Layer on a Silicon Carbide Layer", United States Provisional Application Serial No. 60/237,822 entitled “Method of N 2 O Growth of an oxide layer on a Silicon Carbide Layer” filed May 30, 2001, United States Patent Application Serial No.
  • an N 2 O grown oxide may also be utilized as described in J. P. Xu, P. T. Lai, C. L. Chan, B. Li, and Y. C. Cheng, "Improved Performance and Reliability of N2O-Grown Oxynitride on 6H-SiC," IEEE Electron Device Letters, Vol. 21, No. 6, pp. 298-300, June 2000 . Techniques as described in L. A. Lipkin and J. W. Palmour, "Low interface state density oxides on p-type SiC," Materials Science Forum Vols. 264-268, pp. 853-856, 1998 may also be utilized.
  • a subsequent NO anneal of the thermally grown SiO 2 layer may be provided to reduce the interface trap density as is described in M. K. Das, L. A. Lipkin, J. W. Palmour, G. Y. Chung, J. R. Williams, K. McDonald, and L. C. Feldman, "High Mobility 4H-SiC Inversion Mode MOSFETs Using Thermally Grown, NO Annealed SiO2, IEEE Device Research Conference, Denver, CO, June 19-21, 2000 ; G. Y. Chung, C. C. Tin, J. R. Williams, K. McDonald, R. A. Weller, S. T. Pantelides, L. C. Feldman, M. K. Das, and J. W.
  • Palmour "Improved Inversion Channel Mobility for 4H-SiC MOSFETs Following High Temperature Anneals in Nitric Oxide," IEEE Electron Device Letters accepted for admiri on; and G. Y. Chung, C. C. Tin, J. R. Williams, K. McDonald, M. Di Ventra, S. T. Pantelides, L. C. Feldman, and R. A. Weller, "Effect of nitric oxide annealing on the interface trap densities near the band edges in the 4H polytype of silicon carbide,” Applied Physics Letters, Vol. 76, No. 13, pp. 1713-1715, March 2000 .
  • Oxynitrides may be provided as described in United States Patent Application Serial No. 09/878,442 , entitled “High Voltage, High Temperature Capacitor Structures and Methods of Fabrication” filed June 11, 2001, the disclosure of which is incorporated herein by reference as if set forth fully herein.
  • Figure 4G illustrates formation of the gate contact 32 .
  • the gate contact 32 may be p-type polysilicon and/or may be other suitable contact material and may be formed and patterned utilizing techniques known to those of skill in the art.
  • the oxide 28 of Figure 4F and the gate contact 32 may be formed and patterned together.
  • Figure 4H illustrates formation of the source and drain contacts 30 and 34 respectively, that may be formed by evaporative deposition, sputtering or other such techniques known to those of skill in the art.
  • the source and drain contacts 30 and 34 are nickel which is annealed at about 825 °C after formation so as to improve the quality of the ohmic contact.
  • Figures 5A through 5D illustrate operations in the fabrication of devices according to alternative embodiments of the present invention utilizing a regrown epitaxial layer. Operations for fabrication of the devices are the same as those described above with reference to Figures 4A through 4E and continue with the operations illustrated in Figure 5A .
  • an n-type epitaxial layer 27 is formed on the structure of Figure 4E . Such growth may be provided before or after annealing to activate the implants.
  • the epitaxial layer 27 is patterned to extend between the implanted regions 24 as seen in Figure 5B .
  • Figure 5B also illustrates the formation of the gate oxide 28 .
  • the gate oxide 28 is thermally grown and may be a nitrided oxide.
  • the nitrided oxide may be any suitable gate oxide, however, SiO 2 , oxynitride or ONO may be preferred. Formation of the gate oxide may be carried out as described above with reference to Figure 4F .
  • Figure 5C illustrates formation of source contacts 30'. As seen in Figure 5C , windows are opened in the gate oxide 28 corresponding to the location of the p + regions 22 and/or n + regions 24 . The contacts 30' are then formed in the window.
  • Figure 5D illustrates formation of the gate contact 32 and the source contacts 30' .
  • the oxide 28 of Figure 5D and the gate contact 32 may be formed together.
  • the gate contact may be formed and patterned prior to opening windows for the source contacts.
  • the gate contact 32 may be p-type polysilicon or may be other suitable contact material and may be formed and patterned utilizing techniques known to those of skill in the art.
  • Source contacts 30' may be formed by evaporative deposition, sputtering or other such techniques known to those of skill in the art.
  • Figure 5D also illustrates formation of the drain contact 34 which may be formed by evaporative deposition, sputtering or other such techniques known to those of skill in the art.
  • the source and drain contacts 30' and 34 are nickel which is annealed at temperature of from about 600 °C to about 1000 °C, for example, about 825 °C, after formation so as to improve the quality of the ohmic contact.
  • embodiments of the JFET depletion layer reducing regions may also be provided in DMOSFETs as described in United States Patent Application Serial No. 09/911,995 filed July 24, 2001 and entitled "Silicon Carbide Power Metal-Oxide Semiconductor Field Effect Transistors Having a Shorting Channel and Methods of Fabricating Silicon Carbide Metal-Oxide Semiconductor Field Effect Transistors Having a Shorting Channel," the disclosure of which is incorporated herein as if set forth fully.
  • Figures 6A through 8B are 2D simulation results for various DMOSFET structures illustrating on-state resistance or oxide field strength versus JFET gap distance.
  • Figures 6A and 6B are simulation results for a conventional DMOSFET having a 6 X 10 14 cm -3 and 115 ⁇ m thick drift layer and 10 ⁇ m wide p-wells that extend 0.75 ⁇ m into the drift layer.
  • Figures 7A and 7B are simulation results for a DMOSFET having a 6 X 10 14 cm- 3 and 115 pm thick drift layer, 10 ⁇ m wide p-wells that extend 0.75 ⁇ m into the drift layer and a 5 X 10 15 cm -3 spacer implant that extends 0.75 ⁇ m into the drift layer.
  • Figures 8A and 8B are simulation results for a DMOSFET according to embodiments of the present invention having a 6 X 10 14 cm -3 and 115 ⁇ m thick drift layer, 10 ⁇ m wide p-wells that extend 0.75 ⁇ m into a 5 X 10 15 cm -3 epitaxial layer that is 1.75 ⁇ m thick.
  • embodiments of the present invention may provide narrower JFET gaps for a given maximum oxide field as well as reduced on state resistance.
  • Figure 9A is a measured I-V curve for a DMOSFET without the JFET depletion layer reducing region according to embodiments of the present invention
  • Figure 9B is a measured I-V curve for a DMOSFET with JFET limiting regions according to embodiments of the present invention.
  • the measured on-state resistance is reduced from 266 m ⁇ -cm 2 to 189 m ⁇ -cm 2 .
  • Figure 10A is a measured drain leakage current trace for a DMOSFET without the JFET depletion layer reducing region according to embodiments of the present invention
  • Figure 10B is a measured drain leakage trace for a DMOSFET with JFET depletion layer reducing regions according to embodiments of the present invention. As seen in Figures 10A and 10B , both devices had a breakdown voltage of greater than 3150 V.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Junction Field-Effect Transistors (AREA)

Claims (29)

  1. Cellule unitaire de transistor à effet de champ métal-oxyde-semi-conducteur en carbure de silicium, comprenant :
    une couche de dérive en carbure de silicium de type n (12) ;
    une première région de carbure de silicium de type p (20) adjacente à la couche de dérive ;
    une première région de carbure de silicium de type n (24) dans la première région de carbure de silicium de type p ;
    une couche d'oxyde (28) sur la couche de dérive, la première région de carbure de silicium de type p et la première région de carbure de silicium de type n ; et
    une région de réduction de couche à appauvrissement en carbure de silicium de type n (26) disposée entre la couche de dérive et la première région de carbure de silicium de type p, dans laquelle une région de réduction de couche à appauvrissement de type n comprend une première partie (26a) disposée adjacente à une base de la première région de carbure de silicium de type p et une deuxième partie disposée adjacente à une paroi latérale de la première région de carbure de silicium de type p, dans laquelle la région de réduction de couche à appauvrissement de type n a une concentration de porteurs qui est supérieure à une concentration de porteurs de la couche de dérive, caractérisée en ce que la première partie (26a) de la région de réduction de couche à appauvrissement de type n a une concentration de porteurs supérieure à une concentration de porteurs de la deuxième partie de la région de réduction de couche à appauvrissement de type n.
  2. Cellule unitaire de transistor à effet de champ métal-oxyde-semi-conducteur en carbure de silicium selon la revendication 1, dans laquelle la première partie (26a) de la région de réduction de couche à appauvrissement en carbure de silicium de type n (26) s'étend vers les bords périphériques de la première région de carbure de silicium de type p.
  3. Cellule unitaire de transistor à effet de champ métal-oxyde-semi-conducteur en carbure de silicium selon la revendication 1, dans laquelle de l'aluminium est implanté dans la première région de carbure de silicium de type p (20).
  4. Cellule unitaire de transistor à effet de champ métal-oxyde-semi-conducteur en carbure de silicium selon la revendication 1, comprenant en outre :
    un contact de grille (32) sur la couche d'oxyde (28) ;
    un contact de source (30) sur la première région de carbure de silicium de type n (24) ; et
    un contact de drain (34) sur la couche de dérive (12) opposée à la couche d'oxyde.
  5. Cellule unitaire de transistor à effet de champ métal-oxyde-semi-conducteur en carbure de silicium selon la revendication 4, dans laquelle le contact de grille (32) comprend du silicium polycristallin ou un métal.
  6. Cellule unitaire de transistor à effet de champ métal-oxyde-semi-conducteur en carbure de silicium selon la revendication 4, comprenant en outre un substrat en carbure de silicium de type n (10) disposé entre la couche de dérive (12) et le contact de drain (34).
  7. Cellule unitaire de transistor à effet de champ métal-oxyde-semi-conducteur en carbure de silicium selon la revendication 1, dans laquelle la région de réduction de couche à appauvrissement de type n (26) comprend une couche épitaxiale de carbure de silicium sur la couche de dérive en carbure de silicium de type n (12).
  8. Cellule unitaire de transistor à effet de champ métal-oxyde-semi-conducteur en carbure de silicium selon la revendication 7, dans laquelle la première région de type p (20) est disposée dans la couche épitaxiale en carbure de silicium, mais pas à travers celle-ci.
  9. Cellule unitaire de transistor à effet de champ métal-oxyde-semi-conducteur en carbure de silicium selon la revendication 1, dans laquelle la région de réduction de couche à appauvrissement de type n (26) a une épaisseur de 0,5 µm à 1,5 µm et une concentration de porteurs de 1 x 1015 à 5 x 1017 cm3 .
  10. Cellule de transistor à effet de champ métal-oxyde-semi-conducteur en carbure de silicium selon la revendication 1, comprenant en outre une couche épitaxiale de type n (27) sur la première région de carbure de silicium de type p (20) et une partie de la première région de carbure de silicium de type n (24), et disposée entre la première région de carbure de silicium de type n et la première région de carbure de silicium de type p et la couche d'oxyde (28).
  11. Cellule unitaire de transistor à effet de champ métal oxyde semi-conducteur en carbure de silicium selon la revendication 1, dans laquelle la région de réduction de couche à appauvrissement de type n (26) comprend une région de type n implantée dans la couche de dérive.
  12. Cellule unitaire de transistor à effet de champ métal oxyde semi-conducteur en carbure de silicium selon la revendication 1, comprenant en outre une deuxième région de carbure de silicium de type p (22) disposée dans la première région de carbure de silicium de type p (20) et adjacente à la première région de carbure de silicium de type n (24).
  13. Transistor à effet de champ métal-oxyde-semi-conducteur en carbure de silicium, constitué de cellules unitaires selon l'une quelconque des revendications précédentes, dans lequel les premières régions de carbure de silicium de type n (24) ont une concentration de porteurs supérieure à une concentration de porteurs de la couche de dérive et sont espacées des bords périphériques des premières régions de carbure de silicium de type p.
  14. Transistor à effet de champ métal-oxyde-semi-conducteur en carbure de silicium selon la revendication 13, comprenant en outre une couche de carbure de silicium de type n (10) au-dessous de la couche de dérive (12), dans lequel la couche de carbure de silicium de type n a une concentration de porteurs supérieure à la concentration de porteurs de la couche de dérive.
  15. Procédé de fabrication d'une cellule unitaire de transistor à effet de champ métal oxyde semi-conducteur en carbure de silicium, comprenant :
    la formation d'une couche de dérive en carbure de silicium de type n (12) ;
    la formation d'une première région de carbure de silicium de type p (20) adjacente à la couche de dérive ;
    la formation d'une première région de carbure de silicium de type n (24) dans la première région de carbure de silicium de type p ;
    la formation d'une couche d'oxyde (28) sur la couche de dérive ; et
    la formation d'une région de réduction de couche à appauvrissement en carbure de silicium de type n (26) entre la couche de dérive et la première région de carbure de silicium de type p, dans lequel la région de réduction de couche à appauvrissement de type n comprend une première partie (26a) disposée adjacente à une base de la première région de carbure de silicium de type p et une deuxième partie disposée adjacente à une paroi latérale de la première région de carbure de silicium de type p, dans lequel la région de réduction de couche à appauvrissement de type n a une concentration de porteurs qui est supérieure à une concentration de porteurs de la couche de dérive, caractérisé en ce que la première partie de la région de réduction de couche à appauvrissement a une concentration de porteurs supérieure à la concentration de porteurs de la deuxième partie de la région de réduction de couche à appauvrissement.
  16. Procédé selon la revendication 15, dans lequel la première partie (26a) de la région de réduction de couche à appauvrissement en carbure de silicium de type n (26) s'étend vers les bords périphériques de la première région de carbure de silicium de type p (20).
  17. Procédé selon la revendication 15, dans lequel la formation d'une première région de carbure de silicium de type p (20) comprend en outre :
    l'implantation d'aluminium dans la région de carbure de silicium de type p ; et
    le recuit de la région de carbure de silicium de type p à une température d'au moins 15000 °C.
  18. Procédé selon la revendication 15, comprenant en outre :
    la formation d'un contact de grille (32) sur la couche d'oxyde (28) ;
    la formation d'un contact de source (30) sur la première région de carbure de silicium de type n (24) ; et
    la formation d'un contact de drain (34) sur la couche de dérive (12) opposée à la couche d'oxyde.
  19. Procédé selon la revendication 18, dans lequel le contact de grille (32) comprend du silicium polycristallin ou un métal.
  20. Procédé selon la revendication 18, comprenant en outre la formation d'un substrat en carbure de silicium de type n (10) entre la couche de dérive (12) et le contact de drain (34).
  21. Procédé selon la revendication 15, dans lequel la formation d'une région de réduction de couche à appauvrissement de type n (26) comprend :
    la formation d'une couche épitaxiale de type n de carbure de silicium sur la couche de dérive en carbure de silicium de type n (12) ;
    la formation d'un masque (100) sur la couche épitaxiale ;
    la structuration de la couche épitaxiale pour former la région de réduction de couche à appauvrissement de type n.
  22. Procédé selon la revendication 21, dans lequel la formation d'une première région de type p (20) comprend la formation de la première région de type p dans la couche épitaxiale de carbure de silicium, mais pas à travers celle-ci.
  23. Procédé selon la revendication 15, dans lequel la formation d'une région de réduction de couche à appauvrissement de type n (26) comprend l'implantation de régions de type n dans la couche de dérive.
  24. Procédé selon la revendication 15, dans lequel la région de réduction de couche à appauvrissement de type n (26) est formée à une épaisseur d'environ 0,5 µm à environ 1,5 µm et avec une concentration de porteurs d'environ 1 x 1015 à environ 5 × 1017 cm3.
  25. Procédé selon la revendication 15, comprenant en outre la formation d'une couche épitaxiale de type n (27) sur la première région de carbure de silicium de type p (20) et une partie de la première région de carbure de silicium de type n (24), et entre la première région de type n et la première région de type p et la couche d'oxyde.
  26. Procédé selon la revendication 15, comprenant en outre la formation d'une deuxième région de carbure de silicium de type p (22) dans la première région de carbure de silicium de type p (20) et adjacente à la première région de carbure de silicium de type n (24).
  27. Procédé de fabrication d'un transistor à effet de champ métal-oxyde-semi-conducteur en carbure de silicium comprenant des cellules unitaires formées selon l'une quelconque des revendications 15 à 26, dans lequel les premières régions de carbure de silicium de type n (24) ont une concentration de porteurs supérieure à une concentration de porteurs de la couche de dérive et sont espacées des bords périphériques des premières régions de carbure de silicium de type p (20) ; et
    les deuxièmes parties des régions de réduction de couche à appauvrissement en carbure de silicium de type n (26) sont formées entre les premières régions de carbure de silicium de type p.
  28. Procédé selon la revendication 27, comprenant en outre la formation d'une couche épitaxiale de type n (27) en carbure de silicium sur les premières régions de type p (20) .
  29. Procédé selon la revendication 27, comprenant en outre la formation d'une couche de carbure de silicium de type n (10) au-dessous de la couche de dérive (17), dans lequel la couche de carbure de silicium de type n a une concentration de porteurs supérieure à la concentration de porteurs de la couche de dérive.
EP03799873.9A 2002-12-20 2003-12-04 Transistors mos de puissance en carbure de silicium et procedes de fabrication Expired - Lifetime EP1576672B1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP11167910.6A EP2383787B1 (fr) 2002-12-20 2003-12-04 Transistors MOS de puissance en carbure de silicium

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US43521202P 2002-12-20 2002-12-20
US435212P 2002-12-20
US10/698,170 US7221010B2 (en) 2002-12-20 2003-10-30 Vertical JFET limited silicon carbide power metal-oxide semiconductor field effect transistors
US698170 2003-10-30
PCT/US2003/038490 WO2004061974A2 (fr) 2002-12-20 2003-12-04 Transistors mos de puissance limites, en carbure de silicium, de type jfet vertical, et procedes de fabrication

Related Child Applications (2)

Application Number Title Priority Date Filing Date
EP11167910.6A Division EP2383787B1 (fr) 2002-12-20 2003-12-04 Transistors MOS de puissance en carbure de silicium
EP11167910.6 Division-Into 2011-05-27

Publications (2)

Publication Number Publication Date
EP1576672A2 EP1576672A2 (fr) 2005-09-21
EP1576672B1 true EP1576672B1 (fr) 2013-07-03

Family

ID=32600236

Family Applications (2)

Application Number Title Priority Date Filing Date
EP11167910.6A Expired - Lifetime EP2383787B1 (fr) 2002-12-20 2003-12-04 Transistors MOS de puissance en carbure de silicium
EP03799873.9A Expired - Lifetime EP1576672B1 (fr) 2002-12-20 2003-12-04 Transistors mos de puissance en carbure de silicium et procedes de fabrication

Family Applications Before (1)

Application Number Title Priority Date Filing Date
EP11167910.6A Expired - Lifetime EP2383787B1 (fr) 2002-12-20 2003-12-04 Transistors MOS de puissance en carbure de silicium

Country Status (8)

Country Link
US (3) US7221010B2 (fr)
EP (2) EP2383787B1 (fr)
JP (2) JP5371170B2 (fr)
KR (1) KR101020344B1 (fr)
AU (1) AU2003299587A1 (fr)
CA (1) CA2502850A1 (fr)
TW (1) TWI330894B (fr)
WO (1) WO2004061974A2 (fr)

Families Citing this family (140)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7292723B2 (en) * 2003-02-26 2007-11-06 Walker Digital, Llc System for image analysis in a network that is structured with multiple layers and differentially weighted neurons
US7217954B2 (en) * 2003-03-18 2007-05-15 Matsushita Electric Industrial Co., Ltd. Silicon carbide semiconductor device and method for fabricating the same
US7473929B2 (en) * 2003-07-02 2009-01-06 Panasonic Corporation Semiconductor device and method for fabricating the same
US7198970B2 (en) * 2004-01-23 2007-04-03 The United States Of America As Represented By The Secretary Of The Navy Technique for perfecting the active regions of wide bandgap semiconductor nitride devices
WO2005083796A1 (fr) * 2004-02-27 2005-09-09 Rohm Co., Ltd. Dispositif semi-conducteur et procede de fabrication dudit dispositif
US7118970B2 (en) 2004-06-22 2006-10-10 Cree, Inc. Methods of fabricating silicon carbide devices with hybrid well regions
US7569900B2 (en) * 2004-11-16 2009-08-04 Kabushiki Kaisha Toshiba Silicon carbide high breakdown voltage semiconductor device
JP4761942B2 (ja) * 2004-11-16 2011-08-31 株式会社東芝 半導体装置
JP2006303323A (ja) * 2005-04-22 2006-11-02 Rohm Co Ltd 半導体装置およびその製造方法
US7391057B2 (en) * 2005-05-18 2008-06-24 Cree, Inc. High voltage silicon carbide devices having bi-directional blocking capabilities
US7414268B2 (en) 2005-05-18 2008-08-19 Cree, Inc. High voltage silicon carbide MOS-bipolar devices having bi-directional blocking capabilities
US7615801B2 (en) * 2005-05-18 2009-11-10 Cree, Inc. High voltage silicon carbide devices having bi-directional blocking capabilities
US20060261346A1 (en) * 2005-05-18 2006-11-23 Sei-Hyung Ryu High voltage silicon carbide devices having bi-directional blocking capabilities and methods of fabricating the same
JP4948784B2 (ja) * 2005-05-19 2012-06-06 三菱電機株式会社 半導体装置及びその製造方法
US7528040B2 (en) 2005-05-24 2009-05-05 Cree, Inc. Methods of fabricating silicon carbide devices having smooth channels
JP4903439B2 (ja) * 2005-05-31 2012-03-28 株式会社東芝 電界効果トランジスタ
JP5033316B2 (ja) * 2005-07-05 2012-09-26 日産自動車株式会社 半導体装置の製造方法
US20070126007A1 (en) * 2005-12-07 2007-06-07 Matocha Kevin S SiC semiconductor device and method of fabricating same
US20070134853A1 (en) * 2005-12-09 2007-06-14 Lite-On Semiconductor Corp. Power semiconductor device having reduced on-resistance and method of manufacturing the same
JP4727426B2 (ja) * 2006-01-10 2011-07-20 三菱電機株式会社 半導体装置および半導体装置の製造方法
US8222649B2 (en) * 2006-02-07 2012-07-17 Mitsubishi Electric Corporation Semiconductor device and method of manufacturing the same
US7348228B2 (en) * 2006-05-25 2008-03-25 Texas Instruments Incorporated Deep buried channel junction field effect transistor (DBCJFET)
US7728402B2 (en) 2006-08-01 2010-06-01 Cree, Inc. Semiconductor devices including schottky diodes with controlled breakdown
US8432012B2 (en) 2006-08-01 2013-04-30 Cree, Inc. Semiconductor devices including schottky diodes having overlapping doped regions and methods of fabricating same
CN101501859B (zh) 2006-08-17 2011-05-25 克里公司 高功率绝缘栅双极晶体管
US20080142811A1 (en) * 2006-12-13 2008-06-19 General Electric Company MOSFET devices and methods of fabrication
JP4412335B2 (ja) * 2007-02-23 2010-02-10 株式会社デンソー 炭化珪素半導体装置の製造方法
US8835987B2 (en) * 2007-02-27 2014-09-16 Cree, Inc. Insulated gate bipolar transistors including current suppressing layers
US7629616B2 (en) * 2007-02-28 2009-12-08 Cree, Inc. Silicon carbide self-aligned epitaxial MOSFET for high powered device applications
US7745273B2 (en) * 2007-07-30 2010-06-29 Infineon Technologies Austria Ag Semiconductor device and method for forming same
US7772621B2 (en) * 2007-09-20 2010-08-10 Infineon Technologies Austria Ag Semiconductor device with structured current spread region and method
US7994573B2 (en) * 2007-12-14 2011-08-09 Fairchild Semiconductor Corporation Structure and method for forming power devices with carbon-containing region
US20090159896A1 (en) * 2007-12-20 2009-06-25 General Electric Company Silicon carbide mosfet devices and methods of making
JP5036569B2 (ja) * 2008-01-09 2012-09-26 三菱電機株式会社 炭化珪素半導体装置およびその製造方法
EP2079111A1 (fr) * 2008-01-10 2009-07-15 Khaje Nasir Toosi University of Technology Seyyed Khandan Brdg. Transistor CMOS nanométrique avec substrat intrinsèque
JP2009182271A (ja) * 2008-01-31 2009-08-13 Toshiba Corp 炭化珪素半導体装置
JP4935741B2 (ja) * 2008-04-02 2012-05-23 三菱電機株式会社 炭化珪素半導体装置の製造方法
US8232558B2 (en) 2008-05-21 2012-07-31 Cree, Inc. Junction barrier Schottky diodes with current surge capability
US8530943B2 (en) 2008-08-21 2013-09-10 Panasonic Corporation Semiconductor device
US7943988B2 (en) * 2008-09-05 2011-05-17 Freescale Semiconductor, Inc. Power MOSFET with a gate structure of different material
JP2010087397A (ja) * 2008-10-02 2010-04-15 Sumitomo Electric Ind Ltd 炭化珪素半導体装置
US8217398B2 (en) * 2008-10-15 2012-07-10 General Electric Company Method for the formation of a gate oxide on a SiC substrate and SiC substrates and devices prepared thereby
US8106487B2 (en) 2008-12-23 2012-01-31 Pratt & Whitney Rocketdyne, Inc. Semiconductor device having an inorganic coating layer applied over a junction termination extension
JP2010182762A (ja) * 2009-02-04 2010-08-19 Oki Semiconductor Co Ltd 半導体素子及びこの製造方法
US7829402B2 (en) * 2009-02-10 2010-11-09 General Electric Company MOSFET devices and methods of making
DE112010000882B4 (de) 2009-02-24 2015-03-19 Mitsubishi Electric Corporation Siliziumkarbid-Halbleitervorrichtung
WO2010125819A1 (fr) * 2009-04-30 2010-11-04 パナソニック株式会社 Élément semi-conducteur, dispositif à semi-conducteurs et convertisseur de puissance
JP4918626B2 (ja) * 2009-04-30 2012-04-18 パナソニック株式会社 半導体素子、半導体装置および電力変換器
JP4858791B2 (ja) * 2009-05-22 2012-01-18 住友電気工業株式会社 半導体装置およびその製造方法
US8629509B2 (en) * 2009-06-02 2014-01-14 Cree, Inc. High voltage insulated gate bipolar transistors with minority carrier diverter
US8193848B2 (en) 2009-06-02 2012-06-05 Cree, Inc. Power switching devices having controllable surge current capabilities
US8541787B2 (en) * 2009-07-15 2013-09-24 Cree, Inc. High breakdown voltage wide band-gap MOS-gated bipolar junction transistors with avalanche capability
WO2011010608A1 (fr) * 2009-07-24 2011-01-27 三菱電機株式会社 Procédé de fabrication de dispositif à semi-conducteur en carbure de silicium
US8283973B2 (en) 2009-08-19 2012-10-09 Panasonic Corporation Semiconductor element, semiconductor device, and electric power converter
JP5300658B2 (ja) * 2009-08-26 2013-09-25 三菱電機株式会社 半導体装置及びその製造方法
US8354690B2 (en) 2009-08-31 2013-01-15 Cree, Inc. Solid-state pinch off thyristor circuits
TW201119035A (en) * 2009-11-20 2011-06-01 Wispower Inc Power transistor structure
JP2011165861A (ja) * 2010-02-09 2011-08-25 Mitsubishi Electric Corp 炭化珪素半導体素子
US9117739B2 (en) 2010-03-08 2015-08-25 Cree, Inc. Semiconductor devices with heterojunction barrier regions and methods of fabricating same
US8415671B2 (en) 2010-04-16 2013-04-09 Cree, Inc. Wide band-gap MOSFETs having a heterojunction under gate trenches thereof and related methods of forming such devices
JP5699628B2 (ja) * 2010-07-26 2015-04-15 住友電気工業株式会社 半導体装置
JP5736683B2 (ja) * 2010-07-30 2015-06-17 三菱電機株式会社 電力用半導体素子
US8674439B2 (en) 2010-08-02 2014-03-18 Microsemi Corporation Low loss SiC MOSFET
US8436367B1 (en) 2010-08-02 2013-05-07 Microsemi Corporation SiC power vertical DMOS with increased safe operating area
IT1401756B1 (it) 2010-08-30 2013-08-02 St Microelectronics Srl Dispositivo elettronico integrato con struttura di terminazione di bordo e relativo metodo di fabbricazione.
IT1401754B1 (it) * 2010-08-30 2013-08-02 St Microelectronics Srl Dispositivo elettronico integrato e relativo metodo di fabbricazione.
IT1401755B1 (it) * 2010-08-30 2013-08-02 St Microelectronics Srl Dispositivo elettronico integrato a conduzione verticale e relativo metodo di fabbricazione.
JP5102411B2 (ja) * 2010-09-06 2012-12-19 パナソニック株式会社 半導体装置およびその製造方法
CN105448998B (zh) 2010-10-12 2019-09-03 高通股份有限公司 集成电路芯片和垂直功率器件
US9159825B2 (en) 2010-10-12 2015-10-13 Silanna Semiconductor U.S.A., Inc. Double-sided vertical semiconductor device with thinned substrate
JP2012099601A (ja) 2010-11-01 2012-05-24 Sumitomo Electric Ind Ltd 半導体装置およびその製造方法
JP5574923B2 (ja) * 2010-11-10 2014-08-20 三菱電機株式会社 半導体装置およびその製造方法
JP2012209422A (ja) * 2011-03-30 2012-10-25 Sumitomo Electric Ind Ltd Ｉｇｂｔ
US9184230B2 (en) * 2011-04-08 2015-11-10 Fuji Electric Co., Ltd. Silicon carbide vertical field effect transistor
US9029945B2 (en) 2011-05-06 2015-05-12 Cree, Inc. Field effect transistor devices with low source resistance
US9142662B2 (en) 2011-05-06 2015-09-22 Cree, Inc. Field effect transistor devices with low source resistance
JP2012243966A (ja) * 2011-05-20 2012-12-10 Sumitomo Electric Ind Ltd 半導体装置
JP2012253108A (ja) * 2011-06-01 2012-12-20 Sumitomo Electric Ind Ltd 炭化珪素半導体装置およびその製造方法
US8969912B2 (en) 2011-08-04 2015-03-03 Avogy, Inc. Method and system for a GaN vertical JFET utilizing a regrown channel
US9184305B2 (en) 2011-08-04 2015-11-10 Avogy, Inc. Method and system for a GAN vertical JFET utilizing a regrown gate
US8664665B2 (en) 2011-09-11 2014-03-04 Cree, Inc. Schottky diode employing recesses for elements of junction barrier array
JP2014531752A (ja) 2011-09-11 2014-11-27 クリー インコーポレイテッドＣｒｅｅ Ｉｎｃ． 改善したレイアウトを有するトランジスタを備える高電流密度電力モジュール
US8618582B2 (en) 2011-09-11 2013-12-31 Cree, Inc. Edge termination structure employing recesses for edge termination elements
US9640617B2 (en) 2011-09-11 2017-05-02 Cree, Inc. High performance power module
US8680587B2 (en) 2011-09-11 2014-03-25 Cree, Inc. Schottky diode
US9373617B2 (en) 2011-09-11 2016-06-21 Cree, Inc. High current, low switching loss SiC power module
US9006800B2 (en) 2011-12-14 2015-04-14 Avogy, Inc. Ingan ohmic source contacts for vertical power devices
JP5597217B2 (ja) * 2012-02-29 2014-10-01 株式会社東芝 半導体装置及びその製造方法
JP5481605B2 (ja) * 2012-03-23 2014-04-23 パナソニック株式会社 半導体素子
WO2013147276A1 (fr) * 2012-03-30 2013-10-03 富士電機株式会社 Dispositif semi-conducteur vertical et résistant aux hautes tensions, et procédé de production de dispositif semi-conducteur vertical et résistant aux hautes tensions
JP5646570B2 (ja) * 2012-09-26 2014-12-24 株式会社東芝 半導体装置及びその製造方法
JP6018501B2 (ja) 2012-12-27 2016-11-02 株式会社東芝 半導体装置及びその製造方法
US9530844B2 (en) 2012-12-28 2016-12-27 Cree, Inc. Transistor structures having reduced electrical field at the gate oxide and methods for making same
US10115815B2 (en) 2012-12-28 2018-10-30 Cree, Inc. Transistor structures having a deep recessed P+ junction and methods for making same
EP2874188A4 (fr) 2013-02-13 2016-04-13 Fuji Electric Co Ltd Dispositif semi-conducteur
JP6219044B2 (ja) 2013-03-22 2017-10-25 株式会社東芝 半導体装置およびその製造方法
US8748245B1 (en) 2013-03-27 2014-06-10 Io Semiconductor, Inc. Semiconductor-on-insulator integrated circuit with interconnect below the insulator
US9478507B2 (en) 2013-03-27 2016-10-25 Qualcomm Incorporated Integrated circuit assembly with faraday cage
US9466536B2 (en) 2013-03-27 2016-10-11 Qualcomm Incorporated Semiconductor-on-insulator integrated circuit with back side gate
JP6075185B2 (ja) * 2013-04-26 2017-02-08 住友電気工業株式会社 炭化珪素半導体装置の製造方法
DE112013007095T5 (de) * 2013-06-17 2016-02-25 Hitachi, Ltd. Halbleitervorrichtung und Herstellungsverfahren dafür sowie Leistungsumsetzungsvorrichtung
US9184237B2 (en) * 2013-06-25 2015-11-10 Cree, Inc. Vertical power transistor with built-in gate buffer
TWI611468B (zh) * 2013-07-12 2018-01-11 世界先進積體電路股份有限公司 半導體裝置
US9768259B2 (en) 2013-07-26 2017-09-19 Cree, Inc. Controlled ion implantation into silicon carbide using channeling and devices fabricated using controlled ion implantation into silicon carbide using channeling
JP6189131B2 (ja) * 2013-08-01 2017-08-30 株式会社東芝 半導体装置およびその製造方法
DE112014003637B4 (de) 2013-08-08 2023-07-27 Fuji Electric Co., Ltd. Hochspannungs-Halbleitervorrichtung und Herstellungsverfahren derselben
US9331197B2 (en) * 2013-08-08 2016-05-03 Cree, Inc. Vertical power transistor device
US10600903B2 (en) 2013-09-20 2020-03-24 Cree, Inc. Semiconductor device including a power transistor device and bypass diode
US9214572B2 (en) 2013-09-20 2015-12-15 Monolith Semiconductor Inc. High voltage MOSFET devices and methods of making the devices
US9991376B2 (en) 2013-09-20 2018-06-05 Monolith Semiconductor Inc. High voltage MOSFET devices and methods of making the devices
US10868169B2 (en) 2013-09-20 2020-12-15 Cree, Inc. Monolithically integrated vertical power transistor and bypass diode
US9111919B2 (en) * 2013-10-03 2015-08-18 Cree, Inc. Field effect device with enhanced gate dielectric structure
JP6381101B2 (ja) * 2013-12-09 2018-08-29 富士電機株式会社 炭化珪素半導体装置
US20150263145A1 (en) * 2014-03-14 2015-09-17 Cree, Inc. Igbt structure for wide band-gap semiconductor materials
JP2015057851A (ja) * 2014-11-19 2015-03-26 三菱電機株式会社 半導体装置
US9685550B2 (en) 2014-12-26 2017-06-20 Fairchild Semiconductor Corporation Silicon carbide (SiC) device with improved gate dielectric shielding
US9583482B2 (en) * 2015-02-11 2017-02-28 Monolith Semiconductor Inc. High voltage semiconductor devices and methods of making the devices
US10128340B2 (en) 2015-03-18 2018-11-13 Mitsubishi Electric Corporation Power semiconductor device
WO2017053883A1 (fr) 2015-09-24 2017-03-30 Melior Innovations, Inc. Appareil de dépôt en phase vapeur et techniques faisant intervenir du carbure de silicium dérivé de polymère haute pureté
WO2017081935A1 (fr) 2015-11-12 2017-05-18 三菱電機株式会社 Dispositif à semi-conducteur au carbure de silicium et procédé de fabrication de dispositif à semi-conducteur au carbure de silicium
CN108463871A (zh) * 2016-02-10 2018-08-28 住友电气工业株式会社 碳化硅外延衬底及制造碳化硅半导体器件的方法
US10600871B2 (en) * 2016-05-23 2020-03-24 General Electric Company Electric field shielding in silicon carbide metal-oxide-semiconductor (MOS) device cells using body region extensions
DE102016112016A1 (de) * 2016-06-30 2018-01-04 Infineon Technologies Ag Leistungshalbleiter mit vollständig verarmten Kanalregionen
JP6593294B2 (ja) * 2016-09-28 2019-10-23 トヨタ自動車株式会社 半導体装置
US10861931B2 (en) * 2016-12-08 2020-12-08 Cree, Inc. Power semiconductor devices having gate trenches and buried edge terminations and related methods
JP6289600B2 (ja) * 2016-12-22 2018-03-07 三菱電機株式会社 半導体装置
JP6805074B2 (ja) * 2017-05-12 2020-12-23 株式会社東芝 半導体装置の製造方法
CN108183131A (zh) * 2017-12-05 2018-06-19 中国电子科技集团公司第五十五研究所 一种集成sbd结构的单侧mos型器件制备方法
US11489069B2 (en) 2017-12-21 2022-11-01 Wolfspeed, Inc. Vertical semiconductor device with improved ruggedness
US10615274B2 (en) 2017-12-21 2020-04-07 Cree, Inc. Vertical semiconductor device with improved ruggedness
JP6862381B2 (ja) 2018-03-02 2021-04-21 株式会社東芝 半導体装置
CN108400164B (zh) * 2018-04-23 2021-01-22 广东美的制冷设备有限公司 异质结碳化硅的绝缘栅极晶体管及其制作方法
US10707340B2 (en) * 2018-09-07 2020-07-07 Semiconductor Components Industries, Llc Low turn-on voltage silicon carbide rectifiers
JP7003019B2 (ja) * 2018-09-15 2022-01-20 株式会社東芝 半導体装置
KR102100862B1 (ko) * 2018-12-07 2020-04-16 현대오트론 주식회사 SiC 전력 반도체 소자 및 그 제조방법
CN112447842A (zh) * 2019-08-28 2021-03-05 比亚迪半导体股份有限公司 平面栅mosfet及其制造方法
JP7292233B2 (ja) * 2020-03-11 2023-06-16 株式会社東芝 半導体装置
US11843061B2 (en) * 2020-08-27 2023-12-12 Wolfspeed, Inc. Power silicon carbide based semiconductor devices with improved short circuit capabilities and methods of making such devices
DE102022108492A1 (de) 2022-04-07 2023-10-12 Infineon Technologies Ag Halbleiterdiode und herstellungsverfahren
US20240178269A1 (en) * 2022-11-28 2024-05-30 Semiconductor Components Industries, Llc Semiconductor devices and methods of manufacturing semiconductor devices

Family Cites Families (117)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3629011A (en) 1967-09-11 1971-12-21 Matsushita Electric Ind Co Ltd Method for diffusing an impurity substance into silicon carbide
US3924024A (en) 1973-04-02 1975-12-02 Ncr Co Process for fabricating MNOS non-volatile memories
US4466172A (en) 1979-01-08 1984-08-21 American Microsystems, Inc. Method for fabricating MOS device with self-aligned contacts
JPS5998557A (ja) * 1982-11-27 1984-06-06 Nissan Motor Co Ltd Ｍｏｓトランジスタ
US4469022A (en) 1983-04-01 1984-09-04 Permanent Label Corporation Apparatus and method for decorating articles of non-circular cross-section
JPS61150378A (ja) * 1984-12-25 1986-07-09 Toshiba Corp 電界効果トランジスタ
JPS62115873A (ja) * 1985-11-15 1987-05-27 Matsushita Electronics Corp 縦型ｍｏｓ電界効果トランジスタ
JP2724146B2 (ja) * 1987-05-29 1998-03-09 日産自動車株式会社 縦形ｍｏｓｆｅｔ
US4811065A (en) 1987-06-11 1989-03-07 Siliconix Incorporated Power DMOS transistor with high speed body diode
JPS6449273A (en) * 1987-08-19 1989-02-23 Mitsubishi Electric Corp Semiconductor device and its manufacture
US4875083A (en) 1987-10-26 1989-10-17 North Carolina State University Metal-insulator-semiconductor capacitor formed on silicon carbide
JPH01117363A (ja) 1987-10-30 1989-05-10 Nec Corp 縦型絶縁ゲート電界効果トランジスタ
JPH0237777A (ja) * 1988-07-27 1990-02-07 Nec Corp 縦型電界効果トランジスタ
US5111253A (en) 1989-05-09 1992-05-05 General Electric Company Multicellular FET having a Schottky diode merged therewith
JPH0766971B2 (ja) 1989-06-07 1995-07-19 シャープ株式会社 炭化珪素半導体装置
JPH0334466A (ja) 1989-06-30 1991-02-14 Nippon Telegr & Teleph Corp <Ntt> 縦形二重拡散ｍｏｓｆｅｔ
JPH03157974A (ja) 1989-11-15 1991-07-05 Nec Corp 縦型電界効果トランジスタ
JPH03205832A (ja) * 1990-01-08 1991-09-09 Hitachi Ltd 絶縁ゲート形半導体装置とその製造方法
JP2542448B2 (ja) 1990-05-24 1996-10-09 シャープ株式会社 電界効果トランジスタおよびその製造方法
US5270554A (en) 1991-06-14 1993-12-14 Cree Research, Inc. High power high frequency metal-semiconductor field-effect transistor formed in silicon carbide
JPH0529628A (ja) * 1991-07-19 1993-02-05 Fuji Electric Co Ltd 絶縁ゲート型バイポーラトランジスタ
US5170455A (en) 1991-10-30 1992-12-08 At&T Bell Laboratories Optical connective device
US5242841A (en) 1992-03-25 1993-09-07 Texas Instruments Incorporated Method of making LDMOS transistor with self-aligned source/backgate and photo-aligned gate
US5459107A (en) 1992-06-05 1995-10-17 Cree Research, Inc. Method of obtaining high quality silicon dioxide passivation on silicon carbide and resulting passivated structures
US6344663B1 (en) 1992-06-05 2002-02-05 Cree, Inc. Silicon carbide CMOS devices
US5612260A (en) 1992-06-05 1997-03-18 Cree Research, Inc. Method of obtaining high quality silicon dioxide passivation on silicon carbide and resulting passivated structures
US5726463A (en) 1992-08-07 1998-03-10 General Electric Company Silicon carbide MOSFET having self-aligned gate structure
US5587870A (en) 1992-09-17 1996-12-24 Research Foundation Of State University Of New York Nanocrystalline layer thin film capacitors
JP3146694B2 (ja) 1992-11-12 2001-03-19 富士電機株式会社 炭化けい素ｍｏｓｆｅｔおよび炭化けい素ｍｏｓｆｅｔの製造方法
US5506421A (en) 1992-11-24 1996-04-09 Cree Research, Inc. Power MOSFET in silicon carbide
KR100305123B1 (ko) 1992-12-11 2001-11-22 비센트 비.인그라시아, 알크 엠 아헨 정적랜덤액세스메모리셀및이를포함하는반도체장치
JPH0799312A (ja) 1993-02-22 1995-04-11 Texas Instr Inc <Ti> 半導体装置とその製法
US5479316A (en) 1993-08-24 1995-12-26 Analog Devices, Inc. Integrated circuit metal-oxide-metal capacitor and method of making same
US5510630A (en) 1993-10-18 1996-04-23 Westinghouse Electric Corporation Non-volatile random access memory cell constructed of silicon carbide
US5396085A (en) 1993-12-28 1995-03-07 North Carolina State University Silicon carbide switching device with rectifying-gate
US5385855A (en) 1994-02-24 1995-01-31 General Electric Company Fabrication of silicon carbide integrated circuits
JPH08213607A (ja) 1995-02-08 1996-08-20 Ngk Insulators Ltd 半導体装置およびその製造方法
US5510281A (en) 1995-03-20 1996-04-23 General Electric Company Method of fabricating a self-aligned DMOS transistor device using SiC and spacers
JP3521246B2 (ja) 1995-03-27 2004-04-19 沖電気工業株式会社 電界効果トランジスタおよびその製造方法
US5661312A (en) * 1995-03-30 1997-08-26 Motorola Silicon carbide MOSFET
DE69512021T2 (de) * 1995-03-31 2000-05-04 Cons Ric Microelettronica DMOS-Anordnung-Struktur und Verfahren zur Herstellung
SE9501310D0 (sv) 1995-04-10 1995-04-10 Abb Research Ltd A method for introduction of an impurity dopant in SiC, a semiconductor device formed by the mehtod and a use of a highly doped amorphous layer as a source for dopant diffusion into SiC
US5734180A (en) 1995-06-02 1998-03-31 Texas Instruments Incorporated High-performance high-voltage device structures
FR2738394B1 (fr) 1995-09-06 1998-06-26 Nippon Denso Co Dispositif a semi-conducteur en carbure de silicium, et son procede de fabrication
US6573534B1 (en) 1995-09-06 2003-06-03 Denso Corporation Silicon carbide semiconductor device
JP4001960B2 (ja) 1995-11-03 2007-10-31 フリースケール セミコンダクター インコーポレイテッド 窒化酸化物誘電体層を有する半導体素子の製造方法
US5972801A (en) 1995-11-08 1999-10-26 Cree Research, Inc. Process for reducing defects in oxide layers on silicon carbide
US6136728A (en) 1996-01-05 2000-10-24 Yale University Water vapor annealing process
US6133587A (en) 1996-01-23 2000-10-17 Denso Corporation Silicon carbide semiconductor device and process for manufacturing same
SE9601174D0 (sv) 1996-03-27 1996-03-27 Abb Research Ltd A method for producing a semiconductor device having a semiconductor layer of SiC and such a device
US5877045A (en) 1996-04-10 1999-03-02 Lsi Logic Corporation Method of forming a planar surface during multi-layer interconnect formation by a laser-assisted dielectric deposition
JP3395520B2 (ja) * 1996-06-04 2003-04-14 富士電機株式会社 絶縁ゲートバイポーラトランジスタ
US5763905A (en) 1996-07-09 1998-06-09 Abb Research Ltd. Semiconductor device having a passivation layer
SE9602745D0 (sv) 1996-07-11 1996-07-11 Abb Research Ltd A method for producing a channel region layer in a SiC-layer for a voltage controlled semiconductor device
US5917203A (en) 1996-07-29 1999-06-29 Motorola, Inc. Lateral gate vertical drift region transistor
US5939763A (en) 1996-09-05 1999-08-17 Advanced Micro Devices, Inc. Ultrathin oxynitride structure and process for VLSI applications
US6028012A (en) 1996-12-04 2000-02-22 Yale University Process for forming a gate-quality insulating layer on a silicon carbide substrate
US5837572A (en) 1997-01-10 1998-11-17 Advanced Micro Devices, Inc. CMOS integrated circuit formed by using removable spacers to produce asymmetrical NMOS junctions before asymmetrical PMOS junctions for optimizing thermal diffusivity of dopants implanted therein
US6180958B1 (en) 1997-02-07 2001-01-30 James Albert Cooper, Jr. Structure for increasing the maximum voltage of silicon carbide power transistors
US6570185B1 (en) * 1997-02-07 2003-05-27 Purdue Research Foundation Structure to reduce the on-resistance of power transistors
JP3206727B2 (ja) 1997-02-20 2001-09-10 富士電機株式会社 炭化けい素縦型ｍｏｓｆｅｔおよびその製造方法
DE19809554B4 (de) 1997-03-05 2008-04-03 Denso Corp., Kariya Siliziumkarbidhalbleitervorrichtung
US5877041A (en) 1997-06-30 1999-03-02 Harris Corporation Self-aligned power field effect transistor in silicon carbide
US6063698A (en) 1997-06-30 2000-05-16 Motorola, Inc. Method for manufacturing a high dielectric constant gate oxide for use in semiconductor integrated circuits
US5973356A (en) * 1997-07-08 1999-10-26 Micron Technology, Inc. Ultra high density flash memory
DE19832329A1 (de) 1997-07-31 1999-02-04 Siemens Ag Verfahren zur Strukturierung von Halbleitern mit hoher Präzision, guter Homogenität und Reproduzierbarkeit
JP3180895B2 (ja) 1997-08-18 2001-06-25 富士電機株式会社 炭化けい素半導体装置の製造方法
EP1010204A1 (fr) 1997-08-20 2000-06-21 Siemens Aktiengesellschaft Structure semi-conductrice comportant une zone en carbure de silicium alpha et utilisation de cette structure semi-conductrice
US6239463B1 (en) 1997-08-28 2001-05-29 Siliconix Incorporated Low resistance power MOSFET or other device containing silicon-germanium layer
SE9704150D0 (sv) 1997-11-13 1997-11-13 Abb Research Ltd Semiconductor device of SiC with insulating layer a refractory metal nitride layer
JPH11251592A (ja) 1998-01-05 1999-09-07 Denso Corp 炭化珪素半導体装置
JP3216804B2 (ja) 1998-01-06 2001-10-09 富士電機株式会社 炭化けい素縦形ｆｅｔの製造方法および炭化けい素縦形ｆｅｔ
JPH11266017A (ja) * 1998-01-14 1999-09-28 Denso Corp 炭化珪素半導体装置及びその製造方法
US6100169A (en) 1998-06-08 2000-08-08 Cree, Inc. Methods of fabricating silicon carbide power devices by controlled annealing
US6107142A (en) 1998-06-08 2000-08-22 Cree Research, Inc. Self-aligned methods of fabricating silicon carbide power devices by implantation and lateral diffusion
US5960289A (en) 1998-06-22 1999-09-28 Motorola, Inc. Method for making a dual-thickness gate oxide layer using a nitride/oxide composite region
JP4123636B2 (ja) 1998-06-22 2008-07-23 株式会社デンソー 炭化珪素半導体装置及びその製造方法
US6221700B1 (en) 1998-07-31 2001-04-24 Denso Corporation Method of manufacturing silicon carbide semiconductor device with high activation rate of impurities
JP3959856B2 (ja) 1998-07-31 2007-08-15 株式会社デンソー 炭化珪素半導体装置及びその製造方法
JP2000106371A (ja) 1998-07-31 2000-04-11 Denso Corp 炭化珪素半導体装置の製造方法
US6972436B2 (en) 1998-08-28 2005-12-06 Cree, Inc. High voltage, high temperature capacitor and interconnection structures
US6246076B1 (en) 1998-08-28 2001-06-12 Cree, Inc. Layered dielectric on silicon carbide semiconductor structures
JP2000077663A (ja) * 1998-09-02 2000-03-14 Mitsubishi Electric Corp 電界効果型半導体装置
ATE533178T1 (de) 1998-09-09 2011-11-15 Texas Instruments Inc Integrierter schaltkreis mit kondensator und diesbezügliches herstellungsverfahren
JP4186337B2 (ja) 1998-09-30 2008-11-26 株式会社デンソー 炭化珪素半導体装置及びその製造方法
US6204203B1 (en) 1998-10-14 2001-03-20 Applied Materials, Inc. Post deposition treatment of dielectric films for interface control
US6048766A (en) 1998-10-14 2000-04-11 Advanced Micro Devices Flash memory device having high permittivity stacked dielectric and fabrication thereof
US6190973B1 (en) 1998-12-18 2001-02-20 Zilog Inc. Method of fabricating a high quality thin oxide
US6228720B1 (en) 1999-02-23 2001-05-08 Matsushita Electric Industrial Co., Ltd. Method for making insulated-gate semiconductor element
US6448160B1 (en) 1999-04-01 2002-09-10 Apd Semiconductor, Inc. Method of fabricating power rectifier device to vary operating parameters and resulting device
US6420225B1 (en) 1999-04-01 2002-07-16 Apd Semiconductor, Inc. Method of fabricating power rectifier device
US6399996B1 (en) 1999-04-01 2002-06-04 Apd Semiconductor, Inc. Schottky diode having increased active surface area and method of fabrication
US6238967B1 (en) 1999-04-12 2001-05-29 Motorola, Inc. Method of forming embedded DRAM structure
US6137139A (en) * 1999-06-03 2000-10-24 Intersil Corporation Low voltage dual-well MOS device having high ruggedness, low on-resistance, and improved body diode reverse recovery
JP2000349081A (ja) 1999-06-07 2000-12-15 Sony Corp 酸化膜形成方法
JP4192353B2 (ja) 1999-09-21 2008-12-10 株式会社デンソー 炭化珪素半導体装置及びその製造方法
JP2001119025A (ja) * 1999-10-21 2001-04-27 Matsushita Electric Ind Co Ltd 半導体素子およびその形成方法
US6303508B1 (en) 1999-12-16 2001-10-16 Philips Electronics North America Corporation Superior silicon carbide integrated circuits and method of fabricating
US6429041B1 (en) 2000-07-13 2002-08-06 Cree, Inc. Methods of fabricating silicon carbide inversion channel devices without the need to utilize P-type implantation
DE10036208B4 (de) 2000-07-25 2007-04-19 Siced Electronics Development Gmbh & Co. Kg Halbleiteraufbau mit vergrabenem Inselgebiet und Konaktgebiet
JP4750933B2 (ja) * 2000-09-28 2011-08-17 株式会社東芝 薄型パンチスルー型パワーデバイス
US7067176B2 (en) 2000-10-03 2006-06-27 Cree, Inc. Method of fabricating an oxide layer on a silicon carbide layer utilizing an anneal in a hydrogen environment
US6610366B2 (en) 2000-10-03 2003-08-26 Cree, Inc. Method of N2O annealing an oxide layer on a silicon carbide layer
US6956238B2 (en) 2000-10-03 2005-10-18 Cree, Inc. Silicon carbide power metal-oxide semiconductor field effect transistors having a shorting channel and methods of fabricating silicon carbide metal-oxide semiconductor field effect transistors having a shorting channel
US6767843B2 (en) 2000-10-03 2004-07-27 Cree, Inc. Method of N2O growth of an oxide layer on a silicon carbide layer
US6593620B1 (en) 2000-10-06 2003-07-15 General Semiconductor, Inc. Trench DMOS transistor with embedded trench schottky rectifier
EP1204145B1 (fr) 2000-10-23 2011-12-28 Panasonic Corporation Élément semi-conducteur
JP3881840B2 (ja) 2000-11-14 2007-02-14 独立行政法人産業技術総合研究所 半導体装置
JP4843854B2 (ja) * 2001-03-05 2011-12-21 住友電気工業株式会社 Ｍｏｓデバイス
DE10214150B4 (de) 2001-03-30 2009-06-18 Denso Corporation, Kariya Siliziumkarbidhalbleitervorrichtung und Verfahren zur Herstellung derselben
JP4876321B2 (ja) * 2001-03-30 2012-02-15 株式会社デンソー 炭化珪素半導体装置の製造方法
JP5134746B2 (ja) * 2001-09-20 2013-01-30 新電元工業株式会社 電界効果トランジスタの製造方法
US6620697B1 (en) * 2001-09-24 2003-09-16 Koninklijke Philips Electronics N.V. Silicon carbide lateral metal-oxide semiconductor field-effect transistor having a self-aligned drift region and method for forming the same
US20030209741A1 (en) * 2002-04-26 2003-11-13 Wataru Saitoh Insulated gate semiconductor device
US6700156B2 (en) * 2002-04-26 2004-03-02 Kabushiki Kaisha Toshiba Insulated gate semiconductor device
US6979863B2 (en) 2003-04-24 2005-12-27 Cree, Inc. Silicon carbide MOSFETs with integrated antiparallel junction barrier Schottky free wheeling diodes and methods of fabricating the same
US7074643B2 (en) 2003-04-24 2006-07-11 Cree, Inc. Silicon carbide power devices with self-aligned source and well regions and methods of fabricating same

Also Published As

Publication number Publication date
TW200423415A (en) 2004-11-01
EP2383787B1 (fr) 2015-06-10
JP6095417B2 (ja) 2017-03-15
EP1576672A2 (fr) 2005-09-21
WO2004061974A2 (fr) 2004-07-22
EP2383787A1 (fr) 2011-11-02
US8492827B2 (en) 2013-07-23
AU2003299587A1 (en) 2004-07-29
CA2502850A1 (fr) 2004-07-22
US20040119076A1 (en) 2004-06-24
JP2006511961A (ja) 2006-04-06
WO2004061974A3 (fr) 2004-09-23
JP5371170B2 (ja) 2013-12-18
KR20050085655A (ko) 2005-08-29
US7221010B2 (en) 2007-05-22
US20070158658A1 (en) 2007-07-12
US7923320B2 (en) 2011-04-12
JP2013102245A (ja) 2013-05-23
KR101020344B1 (ko) 2011-03-08
AU2003299587A8 (en) 2004-07-29
US20110254016A1 (en) 2011-10-20
TWI330894B (en) 2010-09-21

Similar Documents

Publication Publication Date Title
EP1576672B1 (fr) Transistors mos de puissance en carbure de silicium et procedes de fabrication
EP2261955B1 (fr) Transistors à effet de champ semi-conducteurs à l&#39;oxyde métallique de puissance au carbure de silicium dotés d&#39;un canal de court-circuit et procédés pour leur fabrication
EP1616347B1 (fr) Dispositifs de puissance en carbure de silicium dotes de regions de source et de puits a alignement automatique, et procedes de fabrication de tels dispositifs
WO2004097944A2 (fr) Silicon carbide mosfets with integrated antiparallel junction barrier schottky diode and methods of fabricating same
CN100544026C (zh) 碳化硅功率mos场效应晶体管及制造方法

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20050623

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LI LU MC NL PT RO SE SI SK TR

AX Request for extension of the european patent

Extension state: AL LT LV MK

DAX Request for extension of the european patent (deleted)
17Q First examination report despatched

Effective date: 20090520

RIC1 Information provided on ipc code assigned before grant

Ipc: H01L 29/78 20060101AFI20121116BHEP

Ipc: H01L 21/336 20060101ALI20121116BHEP

Ipc: H01L 29/16 20060101ALI20121116BHEP

GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

GRAS Grant fee paid

Free format text: ORIGINAL CODE: EPIDOSNIGR3

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LI LU MC NL PT RO SE SI SK TR

REG Reference to a national code

Ref country code: GB

Ref legal event code: FG4D

REG Reference to a national code

Ref country code: CH

Ref legal event code: EP

Ref country code: AT

Ref legal event code: REF

Ref document number: 620193

Country of ref document: AT

Kind code of ref document: T

Effective date: 20130715

REG Reference to a national code

Ref country code: IE

Ref legal event code: FG4D

REG Reference to a national code

Ref country code: DE

Ref legal event code: R096

Ref document number: 60344425

Country of ref document: DE

Effective date: 20130829

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20130703

REG Reference to a national code

Ref country code: NL

Ref legal event code: VDEP

Effective date: 20130703

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: PT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20131104

Ref country code: CY

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20130619

Ref country code: BE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20130703

Ref country code: SE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20130703

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: NL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20130703

Ref country code: FI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20130703

Ref country code: ES

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20131014

Ref country code: GR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20131004

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: CY

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20130703

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: EE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20130703

Ref country code: SK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20130703

Ref country code: CZ

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20130703

Ref country code: DK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20130703

Ref country code: RO

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20130703

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed

Effective date: 20140404

REG Reference to a national code

Ref country code: DE

Ref legal event code: R097

Ref document number: 60344425

Country of ref document: DE

Effective date: 20140404

REG Reference to a national code

Ref country code: CH

Ref legal event code: PL

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 20131204

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: MC

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20130703

Ref country code: LU

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20131204

REG Reference to a national code

Ref country code: IE

Ref legal event code: MM4A

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: CH

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20131231

Ref country code: IE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20131204

Ref country code: LI

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20131231

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20131204

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: TR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20130703

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: HU

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT; INVALID AB INITIO

Effective date: 20031204

Ref country code: BG

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20130703

REG Reference to a national code

Ref country code: FR

Ref legal event code: PLFP

Year of fee payment: 13

REG Reference to a national code

Ref country code: FR

Ref legal event code: PLFP

Year of fee payment: 14

REG Reference to a national code

Ref country code: FR

Ref legal event code: PLFP

Year of fee payment: 15

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 20221227

Year of fee payment: 20

Ref country code: AT

Payment date: 20221121

Year of fee payment: 20

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: IT

Payment date: 20221221

Year of fee payment: 20

Ref country code: DE

Payment date: 20221228

Year of fee payment: 20

REG Reference to a national code

Ref country code: DE

Ref legal event code: R071

Ref document number: 60344425

Country of ref document: DE

REG Reference to a national code

Ref country code: AT

Ref legal event code: MK07

Ref document number: 620193

Country of ref document: AT

Kind code of ref document: T

Effective date: 20231204