DE69818127D1 - Flexible Schmelzsicherungsanordnung in Halbleiterspeicherschaltung mit Redundanz - Google Patents

Flexible Schmelzsicherungsanordnung in Halbleiterspeicherschaltung mit Redundanz

Info

Publication number
DE69818127D1
DE69818127D1 DE69818127T DE69818127T DE69818127D1 DE 69818127 D1 DE69818127 D1 DE 69818127D1 DE 69818127 T DE69818127 T DE 69818127T DE 69818127 T DE69818127 T DE 69818127T DE 69818127 D1 DE69818127 D1 DE 69818127D1
Authority
DE
Germany
Prior art keywords
redundancy
semiconductor memory
memory circuit
fuse arrangement
flexible fuse
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69818127T
Other languages
English (en)
Other versions
DE69818127T2 (de
Inventor
Peter Poechmueller
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qimonda AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of DE69818127D1 publication Critical patent/DE69818127D1/de
Application granted granted Critical
Publication of DE69818127T2 publication Critical patent/DE69818127T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
    • G11C29/789—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes using non-volatile cells or latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/802—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout by encoding redundancy signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/808—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout using a flexible replacement scheme
DE69818127T 1997-03-28 1998-03-03 Flexible Schmelzsicherungsanordnung in Halbleiterspeicherschaltung mit Redundanz Expired - Lifetime DE69818127T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US825312 1997-03-28
US08/825,312 US5859801A (en) 1997-03-28 1997-03-28 Flexible fuse placement in redundant semiconductor memory

Publications (2)

Publication Number Publication Date
DE69818127D1 true DE69818127D1 (de) 2003-10-23
DE69818127T2 DE69818127T2 (de) 2004-05-27

Family

ID=25243679

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69818127T Expired - Lifetime DE69818127T2 (de) 1997-03-28 1998-03-03 Flexible Schmelzsicherungsanordnung in Halbleiterspeicherschaltung mit Redundanz

Country Status (7)

Country Link
US (1) US5859801A (de)
EP (1) EP0867810B1 (de)
JP (1) JP4156067B2 (de)
KR (1) KR100541509B1 (de)
CN (1) CN1129141C (de)
DE (1) DE69818127T2 (de)
TW (1) TW393640B (de)

Families Citing this family (75)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6329712B1 (en) 1998-03-25 2001-12-11 Micron Technology, Inc. High density flip chip memory arrays
JP4260247B2 (ja) * 1998-09-02 2009-04-30 富士通マイクロエレクトロニクス株式会社 半導体記憶装置
US6246615B1 (en) * 1998-12-23 2001-06-12 Micron Technology, Inc. Redundancy mapping in a multichip semiconductor package
US6157583A (en) * 1999-03-02 2000-12-05 Motorola, Inc. Integrated circuit memory having a fuse detect circuit and method therefor
JP2001077322A (ja) * 1999-09-02 2001-03-23 Toshiba Corp 半導体集積回路装置
US6363020B1 (en) * 1999-12-06 2002-03-26 Virage Logic Corp. Architecture with multi-instance redundancy implementation
KR100498610B1 (ko) * 1999-12-22 2005-07-01 주식회사 하이닉스반도체 뱅크 구분없이 휴즈 박스를 사용하는 로우 리던던시 회로
DE10006243A1 (de) * 2000-02-11 2001-08-23 Infineon Technologies Ag Schmelzbrückenanordnung in integrierten Schaltungen
US6166981A (en) * 2000-02-25 2000-12-26 International Business Machines Corporation Method for addressing electrical fuses
US6433405B1 (en) * 2000-03-02 2002-08-13 Hewlett-Packard Company Integrated circuit having provisions for remote storage of chip specific operating parameters
JP2001351396A (ja) * 2000-06-07 2001-12-21 Nec Corp 半導体メモリ及び半導体メモリ搭載ボード
US6570804B1 (en) * 2000-08-29 2003-05-27 Micron Technology, Inc. Fuse read sequence for auto refresh power reduction
US6400292B1 (en) * 2000-09-18 2002-06-04 Mitsubishi Denki Kabushiki Kaisha Semiconductor integrated circuit device
US6426911B1 (en) 2000-10-19 2002-07-30 Infineon Technologies Ag Area efficient method for programming electrical fuses
US6577156B2 (en) * 2000-12-05 2003-06-10 International Business Machines Corporation Method and apparatus for initializing an integrated circuit using compressed data from a remote fusebox
US6396760B1 (en) 2001-03-16 2002-05-28 Virage Logic Corporation Memory having a redundancy scheme to allow one fuse to blow per faulty memory column
US6469949B1 (en) * 2001-05-11 2002-10-22 International Business Machines Corp. Fuse latch array system for an embedded DRAM having a micro-cell architecture
US6519202B1 (en) * 2001-06-29 2003-02-11 Virage Logic Corporation Method and apparatus to change the amount of redundant memory column and fuses associated with a memory device
US6687170B2 (en) * 2001-12-06 2004-02-03 Infineon Technologies Richmond, Lp System and method for storing parity information in fuses
US7093171B2 (en) * 2002-04-03 2006-08-15 International Business Machines Corporation Flexible row redundancy system
US6798272B2 (en) * 2002-07-02 2004-09-28 Infineon Technologies North America Corp. Shift register for sequential fuse latch operation
JP2004063023A (ja) * 2002-07-30 2004-02-26 Renesas Technology Corp 半導体記憶装置
EP1394810B1 (de) * 2002-08-13 2007-10-10 STMicroelectronics S.r.l. Nichtflüchtige Speicheranordnung und Selbstreparatur-Verfahren
US7031218B2 (en) * 2002-11-18 2006-04-18 Infineon Technologies Ag Externally clocked electrical fuse programming with asynchronous fuse selection
US6920072B2 (en) * 2003-02-28 2005-07-19 Union Semiconductor Technology Corporation Apparatus and method for testing redundant memory elements
US6809972B2 (en) * 2003-03-13 2004-10-26 Infineon Technologies Ag Circuit technique for column redundancy fuse latches
US6940773B2 (en) * 2003-04-02 2005-09-06 Infineon Technologies Ag Method and system for manufacturing DRAMs with reduced self-refresh current requirements
US6882583B2 (en) * 2003-04-30 2005-04-19 International Business Machines Corporation Method and apparatus for implementing DRAM redundancy fuse latches using SRAM
KR100557623B1 (ko) 2004-01-06 2006-03-10 주식회사 하이닉스반도체 퓨즈 회로
JP4439950B2 (ja) * 2004-03-10 2010-03-24 富士通マイクロエレクトロニクス株式会社 半導体集積回路
JP2006107590A (ja) * 2004-10-04 2006-04-20 Nec Electronics Corp 半導体集積回路装置及びそのテスト方法
US7215586B2 (en) * 2005-06-29 2007-05-08 Micron Technology, Inc. Apparatus and method for repairing a semiconductor memory
US20070081396A1 (en) * 2005-10-06 2007-04-12 Gordon Tarl S System and method for multi-use eFuse macro
JP4844173B2 (ja) * 2006-03-03 2011-12-28 ソニー株式会社 シリアルデータ転送回路及びシリアルデータ転送方法
JP2010146649A (ja) * 2008-12-19 2010-07-01 Elpida Memory Inc 半導体記憶装置
KR101048795B1 (ko) 2009-07-10 2011-07-15 주식회사 하이닉스반도체 반도체 장치
JP2012069565A (ja) * 2010-09-21 2012-04-05 Renesas Electronics Corp 半導体集積回路及び制御方法
KR101718458B1 (ko) * 2010-11-15 2017-03-22 삼성전자 주식회사 퓨즈 어레이를 갖는 반도체 장치 및 그 동작방법
JP2012109403A (ja) * 2010-11-17 2012-06-07 Elpida Memory Inc 半導体装置及びその制御方法
KR102017724B1 (ko) * 2012-05-31 2019-09-03 삼성전자주식회사 메모리 장치, 이의 동작 방법, 및 이를 포함하는 전자 장치
US8817560B2 (en) * 2012-06-12 2014-08-26 SK Hynix Inc. Semiconductor memory device having redundant fuse circuit
KR101932663B1 (ko) 2012-07-12 2018-12-26 삼성전자 주식회사 리프레쉬 주기 정보를 저장하는 반도체 메모리 장치 및 그 동작방법
US9324398B2 (en) 2013-02-04 2016-04-26 Micron Technology, Inc. Apparatuses and methods for targeted refreshing of memory
US9047978B2 (en) 2013-08-26 2015-06-02 Micron Technology, Inc. Apparatuses and methods for selective row refreshes
CN103916132B (zh) * 2014-03-28 2018-08-21 西安紫光国芯半导体有限公司 一种适用于芯片测试的功能切换电路
CN103916133B (zh) * 2014-03-28 2018-08-21 西安紫光国芯半导体有限公司 一种适用于芯片测试的电路
JP2015219938A (ja) 2014-05-21 2015-12-07 マイクロン テクノロジー， インク． 半導体装置
KR20160006482A (ko) * 2014-07-09 2016-01-19 에스케이하이닉스 주식회사 반도체 장치
JP2017182854A (ja) 2016-03-31 2017-10-05 マイクロン テクノロジー， インク． 半導体装置
US9666307B1 (en) * 2016-09-14 2017-05-30 Micron Technology, Inc. Apparatuses and methods for flexible fuse transmission
CN108242251B (zh) 2016-12-23 2019-08-16 联华电子股份有限公司 动态随机存取存储器
US10522235B2 (en) * 2017-08-25 2019-12-31 Micron Technology, Inc. Repair fuse latches using static random access memory array
US10580475B2 (en) 2018-01-22 2020-03-03 Micron Technology, Inc. Apparatuses and methods for calculating row hammer refresh addresses in a semiconductor device
US11152050B2 (en) 2018-06-19 2021-10-19 Micron Technology, Inc. Apparatuses and methods for multiple row hammer refresh address sequences
JP6804493B2 (ja) 2018-07-19 2020-12-23 華邦電子股▲ふん▼有限公司Ｗｉｎｂｏｎｄ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏｒｐ． メモリデバイス及びメモリ周辺回路
US10770127B2 (en) 2019-02-06 2020-09-08 Micron Technology, Inc. Apparatuses and methods for managing row access counts
US11043254B2 (en) 2019-03-19 2021-06-22 Micron Technology, Inc. Semiconductor device having cam that stores address signals
US11264096B2 (en) 2019-05-14 2022-03-01 Micron Technology, Inc. Apparatuses, systems, and methods for a content addressable memory cell with latch and comparator circuits
US11158364B2 (en) 2019-05-31 2021-10-26 Micron Technology, Inc. Apparatuses and methods for tracking victim rows
US11158373B2 (en) 2019-06-11 2021-10-26 Micron Technology, Inc. Apparatuses, systems, and methods for determining extremum numerical values
US10832792B1 (en) 2019-07-01 2020-11-10 Micron Technology, Inc. Apparatuses and methods for adjusting victim data
US11139015B2 (en) 2019-07-01 2021-10-05 Micron Technology, Inc. Apparatuses and methods for monitoring word line accesses
US11386946B2 (en) 2019-07-16 2022-07-12 Micron Technology, Inc. Apparatuses and methods for tracking row accesses
US10916327B1 (en) * 2019-08-05 2021-02-09 Micron Technology, Inc. Apparatuses and methods for fuse latch and match circuits
US10943636B1 (en) 2019-08-20 2021-03-09 Micron Technology, Inc. Apparatuses and methods for analog row access tracking
US10964378B2 (en) 2019-08-22 2021-03-30 Micron Technology, Inc. Apparatus and method including analog accumulator for determining row access rate and target row address used for refresh operation
US11200942B2 (en) 2019-08-23 2021-12-14 Micron Technology, Inc. Apparatuses and methods for lossy row access counting
US11222682B1 (en) 2020-08-31 2022-01-11 Micron Technology, Inc. Apparatuses and methods for providing refresh addresses
US11462291B2 (en) 2020-11-23 2022-10-04 Micron Technology, Inc. Apparatuses and methods for tracking word line accesses
US11482275B2 (en) 2021-01-20 2022-10-25 Micron Technology, Inc. Apparatuses and methods for dynamically allocated aggressor detection
US11600314B2 (en) 2021-03-15 2023-03-07 Micron Technology, Inc. Apparatuses and methods for sketch circuits for refresh binning
US11664063B2 (en) 2021-08-12 2023-05-30 Micron Technology, Inc. Apparatuses and methods for countering memory attacks
US11688451B2 (en) 2021-11-29 2023-06-27 Micron Technology, Inc. Apparatuses, systems, and methods for main sketch and slim sketch circuit for row address tracking
US11908510B2 (en) * 2022-03-03 2024-02-20 Nanya Technology Corporation Fuse device and operation method thereof
CN114927156B (zh) * 2022-07-21 2022-11-11 浙江力积存储科技有限公司 一种包含冗余存储单元的移位寄存方法及移位寄存结构

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4719601A (en) * 1986-05-02 1988-01-12 International Business Machine Corporation Column redundancy for two port random access memory
JP2622254B2 (ja) * 1987-02-24 1997-06-18 沖電気工業株式会社 半導体記憶装置
JPH02246151A (ja) * 1989-03-20 1990-10-01 Hitachi Ltd 抵抗手段と論理回路、入力回路、ヒューズ切断回路、駆動回路、電源回路、静電保護回路及びこれらを含む半導体記憶装置ならびにそのレイアウト方式及びテスト方式
JP2900451B2 (ja) * 1989-11-30 1999-06-02 ソニー株式会社 メモリ装置
JP2567961B2 (ja) * 1989-12-01 1996-12-25 株式会社日立製作所 半導体装置及びリ−ドフレ−ム
JPH04171860A (ja) * 1990-11-05 1992-06-19 Hitachi Ltd 半導体集積回路装置の製造方法とそれに用いられるレチクル
JPH0831279B2 (ja) * 1990-12-20 1996-03-27 インターナショナル・ビジネス・マシーンズ・コーポレイション 冗長システム
JP3339641B2 (ja) * 1991-05-21 2002-10-28 日本テキサス・インスツルメンツ株式会社 半導体記憶装置
JP2917607B2 (ja) * 1991-10-02 1999-07-12 セイコーエプソン株式会社 半導体装置用リードフレーム
JPH06275094A (ja) * 1993-03-23 1994-09-30 Mitsubishi Electric Corp 半導体装置および半導体メモリ装置
JP3080520B2 (ja) * 1993-09-21 2000-08-28 富士通株式会社 シンクロナスｄｒａｍ
US5402390A (en) * 1993-10-04 1995-03-28 Texas Instruments Inc. Fuse selectable timing signals for internal signal generators
US5569955A (en) * 1994-09-16 1996-10-29 National Semiconductor Corporation High density integrated circuit assembly combining leadframe leads with conductive traces
US5532966A (en) * 1995-06-13 1996-07-02 Alliance Semiconductor Corporation Random access memory redundancy circuit employing fusible links
JP3602939B2 (ja) * 1996-11-19 2004-12-15 松下電器産業株式会社 半導体記憶装置

Also Published As

Publication number Publication date
TW393640B (en) 2000-06-11
EP0867810A2 (de) 1998-09-30
CN1195173A (zh) 1998-10-07
JPH10275494A (ja) 1998-10-13
US5859801A (en) 1999-01-12
KR19980080540A (ko) 1998-11-25
CN1129141C (zh) 2003-11-26
KR100541509B1 (ko) 2006-02-28
EP0867810A3 (de) 1999-10-06
JP4156067B2 (ja) 2008-09-24
EP0867810B1 (de) 2003-09-17
DE69818127T2 (de) 2004-05-27

Similar Documents

Publication Publication Date Title
DE69818127D1 (de) Flexible Schmelzsicherungsanordnung in Halbleiterspeicherschaltung mit Redundanz
DE69810050D1 (de) Halbleiterspeicheranordnung mit Schieberedundanzschaltungen
DE69907997D1 (de) Halbleiterspeicherschaltung mit Redundanz
DE69525421D1 (de) Integrierte Speicherschaltungsanordnung
DE69406074D1 (de) Integrierte Halbleiterspeicherschaltung
DE69521393D1 (de) Integrierte Speicherschaltungsanordnung mit Spannungserhöher
DE69828234D1 (de) Integrierte Halbleiterschaltungsanordnung
DE69830962D1 (de) Integrierte Halbleiterschaltungsanordnung
KR950701125A (ko) 여분구조를 가진 집적 반도체 메모리(integrated semiconductor memory with redundancy arrangement)
DE69830772D1 (de) Integrierte Halbleiterschaltungsanordnung
DE69720158D1 (de) Speicherschaltungen mit eingebautem Selbsttest
DE69125052D1 (de) Halbleiterspeichervorrichtung mit Redundanzschaltung
DE69832348D1 (de) Speicherschaltung
DE69632271T2 (de) Integrierte speicherschaltungsanordnung mit logischer schaltungskompatibler struktur
DE69837135D1 (de) Integrierte Halbleiterschaltungsanordnung
DE69718896D1 (de) Halbleiterspeicheranordnung mit Redundanz
DE69705118D1 (de) Speichervorrichtungsfolgeschaltung
DE69930586D1 (de) Integrierte Halbleiterspeicherschaltung
DE69818325D1 (de) Statische Halbleiterspeicheranordnung mit Zeitgeberschaltung
DE69830878D1 (de) Integrierte Halbleiterschaltungsanordnung
DE69823074D1 (de) Speicherschaltung mit variabler Latenz
DE69828021D1 (de) Halbleiterspeicheranordnung mit mehreren Banken
DE69522545D1 (de) Halbleiterspeicheranordnung mit eingebauten Redundanzspeicherzellen
DE69618928D1 (de) Halbleiterspeichergerät mit Zeilenredundanz
DE69321245D1 (de) Integrierte Programmierschaltung für eine elektrisch programmierbare Halbleiterspeicheranordnung mit Redundanz

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: QIMONDA AG, 81739 MUENCHEN, DE