DE69818127D1 - Flexible Schmelzsicherungsanordnung in Halbleiterspeicherschaltung mit Redundanz - Google Patents

Flexible Schmelzsicherungsanordnung in Halbleiterspeicherschaltung mit Redundanz

Info

Publication number
DE69818127D1
DE69818127D1 DE69818127T DE69818127T DE69818127D1 DE 69818127 D1 DE69818127 D1 DE 69818127D1 DE 69818127 T DE69818127 T DE 69818127T DE 69818127 T DE69818127 T DE 69818127T DE 69818127 D1 DE69818127 D1 DE 69818127D1
Authority
DE
Germany
Prior art keywords
redundancy
semiconductor memory
memory circuit
fuse arrangement
flexible fuse
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69818127T
Other languages
English (en)
Other versions
DE69818127T2 (de
Inventor
Peter Poechmueller
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qimonda AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of DE69818127D1 publication Critical patent/DE69818127D1/de
Application granted granted Critical
Publication of DE69818127T2 publication Critical patent/DE69818127T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
    • G11C29/789—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes using non-volatile cells or latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/802—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout by encoding redundancy signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/808—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout using a flexible replacement scheme
DE69818127T 1997-03-28 1998-03-03 Flexible Schmelzsicherungsanordnung in Halbleiterspeicherschaltung mit Redundanz Expired - Lifetime DE69818127T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US825312 1997-03-28
US08/825,312 US5859801A (en) 1997-03-28 1997-03-28 Flexible fuse placement in redundant semiconductor memory

Publications (2)

Publication Number Publication Date
DE69818127D1 true DE69818127D1 (de) 2003-10-23
DE69818127T2 DE69818127T2 (de) 2004-05-27

Family

ID=25243679

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69818127T Expired - Lifetime DE69818127T2 (de) 1997-03-28 1998-03-03 Flexible Schmelzsicherungsanordnung in Halbleiterspeicherschaltung mit Redundanz

Country Status (7)

Country Link
US (1) US5859801A (de)
EP (1) EP0867810B1 (de)
JP (1) JP4156067B2 (de)
KR (1) KR100541509B1 (de)
CN (1) CN1129141C (de)
DE (1) DE69818127T2 (de)
TW (1) TW393640B (de)

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US7031218B2 (en) * 2002-11-18 2006-04-18 Infineon Technologies Ag Externally clocked electrical fuse programming with asynchronous fuse selection
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KR102017724B1 (ko) * 2012-05-31 2019-09-03 삼성전자주식회사 메모리 장치, 이의 동작 방법, 및 이를 포함하는 전자 장치
US8817560B2 (en) * 2012-06-12 2014-08-26 SK Hynix Inc. Semiconductor memory device having redundant fuse circuit
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CN103916132B (zh) * 2014-03-28 2018-08-21 西安紫光国芯半导体有限公司 一种适用于芯片测试的功能切换电路
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KR20160006482A (ko) * 2014-07-09 2016-01-19 에스케이하이닉스 주식회사 반도체 장치
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US10522235B2 (en) * 2017-08-25 2019-12-31 Micron Technology, Inc. Repair fuse latches using static random access memory array
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Also Published As

Publication number Publication date
CN1129141C (zh) 2003-11-26
EP0867810B1 (de) 2003-09-17
US5859801A (en) 1999-01-12
CN1195173A (zh) 1998-10-07
KR100541509B1 (ko) 2006-02-28
EP0867810A2 (de) 1998-09-30
JPH10275494A (ja) 1998-10-13
KR19980080540A (ko) 1998-11-25
EP0867810A3 (de) 1999-10-06
JP4156067B2 (ja) 2008-09-24
TW393640B (en) 2000-06-11
DE69818127T2 (de) 2004-05-27

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Owner name: QIMONDA AG, 81739 MUENCHEN, DE