DE69818325D1 - Statische Halbleiterspeicheranordnung mit Zeitgeberschaltung - Google Patents

Statische Halbleiterspeicheranordnung mit Zeitgeberschaltung

Info

Publication number
DE69818325D1
DE69818325D1 DE69818325T DE69818325T DE69818325D1 DE 69818325 D1 DE69818325 D1 DE 69818325D1 DE 69818325 T DE69818325 T DE 69818325T DE 69818325 T DE69818325 T DE 69818325T DE 69818325 D1 DE69818325 D1 DE 69818325D1
Authority
DE
Germany
Prior art keywords
memory device
semiconductor memory
timer circuit
static semiconductor
static
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69818325T
Other languages
English (en)
Other versions
DE69818325T2 (de
Inventor
Hideo Inaba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
Original Assignee
NEC Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Electronics Corp filed Critical NEC Electronics Corp
Publication of DE69818325D1 publication Critical patent/DE69818325D1/de
Application granted granted Critical
Publication of DE69818325T2 publication Critical patent/DE69818325T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/18—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using Hall-effect devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/418—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Memories (AREA)
DE69818325T 1997-02-27 1998-02-11 Statische Halbleiterspeicheranordnung mit Zeitgeberschaltung Expired - Fee Related DE69818325T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP04404097A JP3220035B2 (ja) 1997-02-27 1997-02-27 スタチック型半導体記憶装置
JP4404097 1997-02-27

Publications (2)

Publication Number Publication Date
DE69818325D1 true DE69818325D1 (de) 2003-10-30
DE69818325T2 DE69818325T2 (de) 2004-07-01

Family

ID=12680517

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69818325T Expired - Fee Related DE69818325T2 (de) 1997-02-27 1998-02-11 Statische Halbleiterspeicheranordnung mit Zeitgeberschaltung

Country Status (6)

Country Link
US (1) US5936911A (de)
EP (1) EP0862181B1 (de)
JP (1) JP3220035B2 (de)
KR (1) KR100309899B1 (de)
CN (1) CN1192029A (de)
DE (1) DE69818325T2 (de)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6141240A (en) * 1998-09-17 2000-10-31 Texas Instruments Incorporated Apparatus and method for static random access memory array
US6198670B1 (en) 1999-06-22 2001-03-06 Micron Technology, Inc. Bias generator for a four transistor load less memory cell
JP2001067048A (ja) * 1999-08-31 2001-03-16 Hitachi Ltd 液晶表示装置
KR100391152B1 (ko) 2000-11-23 2003-07-12 삼성전자주식회사 조기동작 고전압 발생기를 가지는 반도체 장치 및 그에따른 고전압 공급방법
US6496439B1 (en) * 2001-06-29 2002-12-17 Stmicroelectronics, Inc. Content addressable memory (CAM) with battery back-up and low current, stand-by mode controller
JP4454925B2 (ja) * 2002-10-29 2010-04-21 富士通マイクロエレクトロニクス株式会社 半導体記憶装置
US7046572B2 (en) * 2003-06-16 2006-05-16 International Business Machines Corporation Low power manager for standby operation of memory system
KR100583317B1 (ko) * 2003-12-16 2006-05-25 엘지.필립스 엘시디 주식회사 액정표시장치의 구동장치 및 구동방법
US7411853B2 (en) * 2005-11-17 2008-08-12 Altera Corporation Volatile memory elements with elevated power supply levels for programmable logic device integrated circuits
JP2007164922A (ja) * 2005-12-15 2007-06-28 Matsushita Electric Ind Co Ltd デコーダ回路
KR100776762B1 (ko) * 2006-08-11 2007-11-19 주식회사 하이닉스반도체 반도체 메모리 장치
US7492649B2 (en) * 2006-11-09 2009-02-17 Kabushiki Kaisha Toshiba Systems and methods for improving memory reliability by selectively enabling word line signals
JP5398520B2 (ja) * 2009-12-25 2014-01-29 株式会社東芝 ワード線駆動回路
US9875788B2 (en) * 2010-03-25 2018-01-23 Qualcomm Incorporated Low-power 5T SRAM with improved stability and reduced bitcell size
US8659972B2 (en) 2011-09-12 2014-02-25 Qualcomm Incorporated Adaptive read wordline voltage boosting apparatus and method for multi-port SRAM
CN102760487A (zh) * 2012-08-09 2012-10-31 安徽大学 一种高性能静态随机存储器内部最优分级的方法及其架构
US10026456B2 (en) * 2015-02-23 2018-07-17 Qualcomm Incorporated Bitline positive boost write-assist circuits for memory bit cells employing a P-type Field-Effect transistor (PFET) write port(s), and related systems and methods
CN107591178B (zh) * 2016-07-06 2021-01-15 展讯通信（上海）有限公司 静态随机存储器阵列的字线抬升方法及装置
CN108281165A (zh) * 2017-01-06 2018-07-13 旺宏电子股份有限公司 存储器装置的操作方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63282992A (ja) * 1987-05-15 1988-11-18 Oki Electric Ind Co Ltd 半導体記憶回路
US4896297A (en) * 1987-10-23 1990-01-23 Mitsubishi Denki Kabushiki Kaisha Circuit for generating a boosted signal for a word line
JPH03156795A (ja) * 1989-11-15 1991-07-04 Toshiba Micro Electron Kk 半導体メモリ回路装置
US5132931A (en) * 1990-08-28 1992-07-21 Analog Devices, Inc. Sense enable timing circuit for a random access memory
JPH056675A (ja) * 1991-06-27 1993-01-14 Nec Corp スタテイツク型半導体メモリ装置
KR0135699B1 (ko) * 1994-07-11 1998-04-24 김주용 셀프-리프레쉬 가능한 듀얼포트 동적 캠셀 및 리프레쉬장치
JPH08111094A (ja) * 1994-10-12 1996-04-30 Nec Corp スタチック型半導体記憶装置
JPH09231767A (ja) * 1996-02-28 1997-09-05 Nec Corp スタティック型半導体記憶装置

Also Published As

Publication number Publication date
EP0862181A3 (de) 1999-07-07
KR100309899B1 (ko) 2001-12-12
US5936911A (en) 1999-08-10
KR19980071654A (ko) 1998-10-26
JP3220035B2 (ja) 2001-10-22
EP0862181A2 (de) 1998-09-02
CN1192029A (zh) 1998-09-02
EP0862181B1 (de) 2003-09-24
DE69818325T2 (de) 2004-07-01
JPH10241372A (ja) 1998-09-11

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee