DE69123379D1 - Halbleiterspeichervorrichtung - Google Patents

Halbleiterspeichervorrichtung

Info

Publication number
DE69123379D1
DE69123379D1 DE69123379T DE69123379T DE69123379D1 DE 69123379 D1 DE69123379 D1 DE 69123379D1 DE 69123379 T DE69123379 T DE 69123379T DE 69123379 T DE69123379 T DE 69123379T DE 69123379 D1 DE69123379 D1 DE 69123379D1
Authority
DE
Germany
Prior art keywords
memory device
semiconductor memory
semiconductor
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69123379T
Other languages
English (en)
Other versions
DE69123379T2 (de
Inventor
Tomohisa Wada
Shuji Murakami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Application granted granted Critical
Publication of DE69123379D1 publication Critical patent/DE69123379D1/de
Publication of DE69123379T2 publication Critical patent/DE69123379T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/40—Response verification devices using compression techniques
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/26—Accessing multiple arrays
    • G11C29/28—Dependent multiple arrays, e.g. multi-bit arrays
DE69123379T 1990-03-20 1991-03-19 Halbleiterspeichervorrichtung Expired - Fee Related DE69123379T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7136790 1990-03-20

Publications (2)

Publication Number Publication Date
DE69123379D1 true DE69123379D1 (de) 1997-01-16
DE69123379T2 DE69123379T2 (de) 1997-04-24

Family

ID=13458461

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69123379T Expired - Fee Related DE69123379T2 (de) 1990-03-20 1991-03-19 Halbleiterspeichervorrichtung

Country Status (3)

Country Link
US (1) US5301155A (de)
EP (1) EP0448364B1 (de)
DE (1) DE69123379T2 (de)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IL96808A (en) * 1990-04-18 1996-03-31 Rambus Inc Introductory / Origin Circuit Agreed Using High-Performance Brokerage
JP2687785B2 (ja) * 1991-09-27 1997-12-08 日本電気株式会社 半導体記憶装置
EP0599524A3 (de) * 1992-11-24 1996-04-17 Advanced Micro Devices Inc Selbsttest für integrierte Speichernetzwerke.
JP2845713B2 (ja) * 1993-03-12 1999-01-13 株式会社東芝 並列ビットテストモード内蔵半導体メモリ
JP3293935B2 (ja) * 1993-03-12 2002-06-17 株式会社東芝 並列ビットテストモード内蔵半導体メモリ
US5781756A (en) * 1994-04-01 1998-07-14 Xilinx, Inc. Programmable logic device with partially configurable memory cells and a method for configuration
US5548752A (en) * 1994-08-10 1996-08-20 Motorola, Inc. Method and system for storing data in a memory device
KR0174338B1 (ko) * 1994-11-30 1999-04-01 윌리엄 티. 엘리스 간단하게 테스트할 수 있는 구성을 갖는 랜덤 액세스 메모리
US5619460A (en) * 1995-06-07 1997-04-08 International Business Machines Corporation Method of testing a random access memory
US5872769A (en) 1995-07-19 1999-02-16 Fujitsu Network Communications, Inc. Linked list structures for multiple levels of control in an ATM switch
US5925142A (en) 1995-10-06 1999-07-20 Micron Technology, Inc. Self-test RAM using external synchronous clock
KR0183856B1 (ko) * 1996-05-17 1999-04-15 김광호 반도체 메모리 장치의 번인 스트레스 회로
US5920573A (en) * 1996-07-22 1999-07-06 Texas Istruments Incorporated Method and apparatus for reducing area and pin count required in design for test of wide data path memories
US5966388A (en) 1997-01-06 1999-10-12 Micron Technology, Inc. High-speed test system for a memory device
US6172935B1 (en) 1997-04-25 2001-01-09 Micron Technology, Inc. Synchronous dynamic random access memory device
US6553525B1 (en) * 1999-11-08 2003-04-22 International Business Machines Corporation Method and apparatus for selectively enabling and disabling functions on a per array basis
JP2001297600A (ja) * 2000-04-11 2001-10-26 Mitsubishi Electric Corp 半導体集積回路およびそのテスト方法
DE10050212A1 (de) * 2000-10-11 2002-04-25 Infineon Technologies Ag Verfahren und integrierte Schaltung zum Testen eines Speichers mit mehreren Speicherbänken
US6621755B2 (en) * 2001-08-30 2003-09-16 Micron Technology, Inc. Testmode to increase acceleration in burn-in
KR100527529B1 (ko) * 2002-12-13 2005-11-09 주식회사 하이닉스반도체 입출력 대역폭을 조절할 수 있는 메모리 장치
KR20040066553A (ko) * 2003-01-20 2004-07-27 삼성전자주식회사 멀티칩 패키지의 통합 번인 검사 방법
JP2008269692A (ja) * 2007-04-19 2008-11-06 Matsushita Electric Ind Co Ltd 半導体装置およびその検査方法
WO2012012369A2 (en) * 2010-07-19 2012-01-26 Arizona Board Of Regents For And On Behalf Of Arizona State University Fast parallel test of sram arrays

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS592996B2 (ja) * 1976-05-24 1984-01-21 株式会社日立製作所 半導体記憶回路
JPS5717997A (en) * 1980-07-07 1982-01-29 Matsushita Electric Ind Co Ltd Voice synthesizer
JPS57105897A (en) * 1980-12-23 1982-07-01 Fujitsu Ltd Semiconductor storage device
US4541090A (en) * 1981-06-09 1985-09-10 Matsushita Electric Industrial Co., Ltd. Semiconductor memory device
JPS58211393A (ja) * 1982-06-02 1983-12-08 Mitsubishi Electric Corp 半導体メモリ装置
JPS60261148A (ja) * 1984-06-07 1985-12-24 Mitsubishi Electric Corp 半導体装置
KR900005666B1 (ko) * 1984-08-30 1990-08-03 미쓰비시전기 주식회사 반도체기억장치
US4654849B1 (en) * 1984-08-31 1999-06-22 Texas Instruments Inc High speed concurrent testing of dynamic read/write memory array
JP2523586B2 (ja) * 1987-02-27 1996-08-14 株式会社日立製作所 半導体記憶装置
JPS63244399A (ja) * 1987-03-16 1988-10-11 シーメンス・アクチエンゲゼルシヤフト 半導体メモリの検査方法および回路装置
KR0127680B1 (ko) * 1987-08-07 1998-04-03 미다 가쓰시게 반도체 기억장치
KR910005306B1 (ko) * 1988-12-31 1991-07-24 삼성전자 주식회사 고밀도 메모리의 테스트를 위한 병렬리드회로
JPH06151700A (ja) * 1992-11-11 1994-05-31 Toshiba Corp インテリジェントトランジスタモジュール

Also Published As

Publication number Publication date
EP0448364B1 (de) 1996-12-04
US5301155A (en) 1994-04-05
DE69123379T2 (de) 1997-04-24
EP0448364A2 (de) 1991-09-25
EP0448364A3 (en) 1992-04-29

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee