DE69224315T2 - Halbleiterspeichervorrichtung - Google Patents
HalbleiterspeichervorrichtungInfo
- Publication number
- DE69224315T2 DE69224315T2 DE69224315T DE69224315T DE69224315T2 DE 69224315 T2 DE69224315 T2 DE 69224315T2 DE 69224315 T DE69224315 T DE 69224315T DE 69224315 T DE69224315 T DE 69224315T DE 69224315 T2 DE69224315 T2 DE 69224315T2
- Authority
- DE
- Germany
- Prior art keywords
- memory device
- semiconductor memory
- semiconductor
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9229591 | 1991-04-23 | ||
JP9229491 | 1991-04-23 | ||
JP9725691 | 1991-04-26 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69224315D1 DE69224315D1 (de) | 1998-03-12 |
DE69224315T2 true DE69224315T2 (de) | 1998-06-25 |
Family
ID=27306989
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69224315T Expired - Fee Related DE69224315T2 (de) | 1991-04-23 | 1992-04-22 | Halbleiterspeichervorrichtung |
Country Status (3)
Country | Link |
---|---|
US (3) | US5331197A (de) |
EP (1) | EP0510607B1 (de) |
DE (1) | DE69224315T2 (de) |
Families Citing this family (68)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2994670B2 (ja) * | 1989-12-02 | 1999-12-27 | 忠弘 大見 | 半導体装置及びその製造方法 |
EP0510667B1 (de) * | 1991-04-26 | 1996-09-11 | Canon Kabushiki Kaisha | Halbleitervorrichtung mit verbessertem isoliertem Gate-Transistor |
DE69232432T2 (de) | 1991-11-20 | 2002-07-18 | Canon Kk | Verfahren zur Herstellung einer Halbleiteranordnung |
JPH07263647A (ja) * | 1994-02-04 | 1995-10-13 | Canon Inc | 電子回路装置 |
JP3501416B2 (ja) * | 1994-04-28 | 2004-03-02 | 忠弘 大見 | 半導体装置 |
JP3273582B2 (ja) * | 1994-05-13 | 2002-04-08 | キヤノン株式会社 | 記憶装置 |
JPH08222648A (ja) * | 1995-02-14 | 1996-08-30 | Canon Inc | 記憶装置 |
US6465865B1 (en) * | 1996-01-05 | 2002-10-15 | Micron Technology, Inc. | Isolated structure and method of fabricating such a structure on a substrate |
US6110798A (en) * | 1996-01-05 | 2000-08-29 | Micron Technology, Inc. | Method of fabricating an isolation structure on a semiconductor substrate |
US6005801A (en) * | 1997-08-20 | 1999-12-21 | Micron Technology, Inc. | Reduced leakage DRAM storage unit |
US6157566A (en) * | 1997-08-20 | 2000-12-05 | Micron Technology, Inc. | Reduced leakage DRAM storage unit |
US6355955B1 (en) | 1998-05-14 | 2002-03-12 | Advanced Micro Devices, Inc. | Transistor and a method for forming the transistor with elevated and/or relatively shallow source/drain regions to achieve enhanced gate electrode formation |
US6121651A (en) | 1998-07-30 | 2000-09-19 | International Business Machines Corporation | Dram cell with three-sided-gate transfer device |
TW442837B (en) * | 1998-12-03 | 2001-06-23 | Infineon Technologies Ag | Integrated circuit-arrangement and its production method |
US6403472B1 (en) * | 1999-06-23 | 2002-06-11 | Harris Corporation | Method of forming resistive contacts on intergrated circuits with mobility spoiling ions including high resistive contacts and low resistivity silicide contacts |
US6617226B1 (en) * | 1999-06-30 | 2003-09-09 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing the same |
US20020011612A1 (en) * | 2000-07-31 | 2002-01-31 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing the same |
US7176109B2 (en) * | 2001-03-23 | 2007-02-13 | Micron Technology, Inc. | Method for forming raised structures by controlled selective epitaxial growth of facet using spacer |
TWI230392B (en) | 2001-06-18 | 2005-04-01 | Innovative Silicon Sa | Semiconductor device |
US6784076B2 (en) * | 2002-04-08 | 2004-08-31 | Micron Technology, Inc. | Process for making a silicon-on-insulator ledge by implanting ions from silicon source |
US6888187B2 (en) * | 2002-08-26 | 2005-05-03 | International Business Machines Corporation | DRAM cell with enhanced SER immunity |
JP4427259B2 (ja) * | 2003-02-28 | 2010-03-03 | 株式会社東芝 | 半導体装置及びその製造方法 |
US20040228168A1 (en) | 2003-05-13 | 2004-11-18 | Richard Ferrant | Semiconductor memory device and method of operating same |
US7335934B2 (en) | 2003-07-22 | 2008-02-26 | Innovative Silicon S.A. | Integrated circuit device, and method of fabricating same |
US7388251B2 (en) * | 2004-08-11 | 2008-06-17 | Micron Technology, Inc. | Non-planar flash memory array with shielded floating gates on silicon mesas |
US7606066B2 (en) | 2005-09-07 | 2009-10-20 | Innovative Silicon Isi Sa | Memory cell and memory cell array having an electrically floating body transistor, and methods of operating same |
US7683430B2 (en) | 2005-12-19 | 2010-03-23 | Innovative Silicon Isi Sa | Electrically floating body memory cell and array, and method of operating or controlling same |
JP4528718B2 (ja) * | 2005-12-27 | 2010-08-18 | 株式会社東芝 | 不揮発性半導体メモリの製造方法 |
US7492632B2 (en) | 2006-04-07 | 2009-02-17 | Innovative Silicon Isi Sa | Memory array having a programmable word length, and method of operating same |
US7933142B2 (en) | 2006-05-02 | 2011-04-26 | Micron Technology, Inc. | Semiconductor memory cell and array using punch-through to program and read same |
JP2007305827A (ja) * | 2006-05-12 | 2007-11-22 | Elpida Memory Inc | 半導体装置及びその製造方法 |
US8069377B2 (en) | 2006-06-26 | 2011-11-29 | Micron Technology, Inc. | Integrated circuit having memory array including ECC and column redundancy and method of operating the same |
US7542340B2 (en) | 2006-07-11 | 2009-06-02 | Innovative Silicon Isi Sa | Integrated circuit including memory array having a segmented bit line architecture and method of controlling and/or operating same |
KR101406604B1 (ko) | 2007-01-26 | 2014-06-11 | 마이크론 테크놀로지, 인코포레이티드 | 게이트형 바디 영역으로부터 격리되는 소스/드레인 영역을 포함하는 플로팅-바디 dram 트랜지스터 |
WO2009031052A2 (en) | 2007-03-29 | 2009-03-12 | Innovative Silicon S.A. | Zero-capacitor (floating body) random access memory circuits with polycide word lines and manufacturing methods therefor |
US8064274B2 (en) | 2007-05-30 | 2011-11-22 | Micron Technology, Inc. | Integrated circuit having voltage generation circuitry for memory cell array, and method of operating and/or controlling same |
US8085594B2 (en) | 2007-06-01 | 2011-12-27 | Micron Technology, Inc. | Reading technique for memory cell with electrically floating body transistor |
US8194487B2 (en) | 2007-09-17 | 2012-06-05 | Micron Technology, Inc. | Refreshing data of memory cells with electrically floating body transistors |
US8536628B2 (en) | 2007-11-29 | 2013-09-17 | Micron Technology, Inc. | Integrated circuit having memory cell array including barriers, and method of manufacturing same |
US8349662B2 (en) | 2007-12-11 | 2013-01-08 | Micron Technology, Inc. | Integrated circuit having memory cell array, and method of manufacturing same |
US8773933B2 (en) | 2012-03-16 | 2014-07-08 | Micron Technology, Inc. | Techniques for accessing memory cells |
US8014195B2 (en) | 2008-02-06 | 2011-09-06 | Micron Technology, Inc. | Single transistor memory cell |
US8189376B2 (en) | 2008-02-08 | 2012-05-29 | Micron Technology, Inc. | Integrated circuit having memory cells including gate material having high work function, and method of manufacturing same |
US7957206B2 (en) | 2008-04-04 | 2011-06-07 | Micron Technology, Inc. | Read circuitry for an integrated circuit having memory cells and/or a memory cell array, and method of operating same |
US7947543B2 (en) | 2008-09-25 | 2011-05-24 | Micron Technology, Inc. | Recessed gate silicon-on-insulator floating body device with self-aligned lateral isolation |
US7933140B2 (en) | 2008-10-02 | 2011-04-26 | Micron Technology, Inc. | Techniques for reducing a voltage swing |
US7924630B2 (en) | 2008-10-15 | 2011-04-12 | Micron Technology, Inc. | Techniques for simultaneously driving a plurality of source lines |
US8223574B2 (en) | 2008-11-05 | 2012-07-17 | Micron Technology, Inc. | Techniques for block refreshing a semiconductor memory device |
US8213226B2 (en) | 2008-12-05 | 2012-07-03 | Micron Technology, Inc. | Vertical transistor memory cell and array |
US8319294B2 (en) | 2009-02-18 | 2012-11-27 | Micron Technology, Inc. | Techniques for providing a source line plane |
WO2010102106A2 (en) | 2009-03-04 | 2010-09-10 | Innovative Silicon Isi Sa | Techniques for forming a contact to a buried diffusion layer in a semiconductor memory device |
WO2010114890A1 (en) | 2009-03-31 | 2010-10-07 | Innovative Silicon Isi Sa | Techniques for providing a semiconductor memory device |
US8139418B2 (en) | 2009-04-27 | 2012-03-20 | Micron Technology, Inc. | Techniques for controlling a direct injection semiconductor memory device |
US8508994B2 (en) | 2009-04-30 | 2013-08-13 | Micron Technology, Inc. | Semiconductor device with floating gate and electrically floating body |
US8498157B2 (en) | 2009-05-22 | 2013-07-30 | Micron Technology, Inc. | Techniques for providing a direct injection semiconductor memory device |
US8537610B2 (en) | 2009-07-10 | 2013-09-17 | Micron Technology, Inc. | Techniques for providing a semiconductor memory device |
US9076543B2 (en) | 2009-07-27 | 2015-07-07 | Micron Technology, Inc. | Techniques for providing a direct injection semiconductor memory device |
US8199595B2 (en) | 2009-09-04 | 2012-06-12 | Micron Technology, Inc. | Techniques for sensing a semiconductor memory device |
US8174881B2 (en) | 2009-11-24 | 2012-05-08 | Micron Technology, Inc. | Techniques for reducing disturbance in a semiconductor device |
US8310893B2 (en) | 2009-12-16 | 2012-11-13 | Micron Technology, Inc. | Techniques for reducing impact of array disturbs in a semiconductor memory device |
US8416636B2 (en) | 2010-02-12 | 2013-04-09 | Micron Technology, Inc. | Techniques for controlling a semiconductor memory device |
US8576631B2 (en) | 2010-03-04 | 2013-11-05 | Micron Technology, Inc. | Techniques for sensing a semiconductor memory device |
US8411513B2 (en) | 2010-03-04 | 2013-04-02 | Micron Technology, Inc. | Techniques for providing a semiconductor memory device having hierarchical bit lines |
US8369177B2 (en) | 2010-03-05 | 2013-02-05 | Micron Technology, Inc. | Techniques for reading from and/or writing to a semiconductor memory device |
EP2548227B1 (de) | 2010-03-15 | 2021-07-14 | Micron Technology, Inc. | Verfahren zur bereitstellung einer halbleiterspeichervorrichtung |
US8411524B2 (en) | 2010-05-06 | 2013-04-02 | Micron Technology, Inc. | Techniques for refreshing a semiconductor memory device |
US8531878B2 (en) | 2011-05-17 | 2013-09-10 | Micron Technology, Inc. | Techniques for providing a semiconductor memory device |
US9559216B2 (en) | 2011-06-06 | 2017-01-31 | Micron Technology, Inc. | Semiconductor memory device and method for biasing same |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6319847A (ja) * | 1986-07-14 | 1988-01-27 | Oki Electric Ind Co Ltd | 半導体記憶装置 |
JPS63260166A (ja) * | 1987-04-17 | 1988-10-27 | Oki Electric Ind Co Ltd | 半導体メモリ装置及びその製造方法 |
JP2582794B2 (ja) * | 1987-08-10 | 1997-02-19 | 株式会社東芝 | 半導体装置及びその製造方法 |
JP2655859B2 (ja) * | 1988-02-03 | 1997-09-24 | 株式会社日立製作所 | 半導体記憶装置 |
JPH0214578A (ja) * | 1988-07-01 | 1990-01-18 | Fujitsu Ltd | 半導体装置 |
US5115289A (en) * | 1988-11-21 | 1992-05-19 | Hitachi, Ltd. | Semiconductor device and semiconductor memory device |
JP2768719B2 (ja) * | 1988-11-21 | 1998-06-25 | 株式会社日立製作所 | 半導体装置及び半導体記憶装置 |
US5019878A (en) * | 1989-03-31 | 1991-05-28 | Texas Instruments Incorporated | Programmable interconnect or cell using silicided MOS transistors |
FR2648623B1 (fr) * | 1989-06-19 | 1994-07-08 | France Etat | Structure de transistor mos sur isolant avec prise de caisson reliee a la source et procede de fabrication |
US5163180A (en) * | 1991-01-18 | 1992-11-10 | Actel Corporation | Low voltage programming antifuse and transistor breakdown method for making same |
US5100827A (en) * | 1991-02-27 | 1992-03-31 | At&T Bell Laboratories | Buried antifuse |
-
1992
- 1992-04-17 US US07/870,258 patent/US5331197A/en not_active Expired - Fee Related
- 1992-04-22 DE DE69224315T patent/DE69224315T2/de not_active Expired - Fee Related
- 1992-04-22 EP EP92106874A patent/EP0510607B1/de not_active Expired - Lifetime
-
1994
- 1994-06-21 US US08/263,147 patent/US5567962A/en not_active Expired - Fee Related
-
1995
- 1995-04-06 US US08/417,831 patent/US5595920A/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
EP0510607B1 (de) | 1998-02-04 |
US5567962A (en) | 1996-10-22 |
US5595920A (en) | 1997-01-21 |
US5331197A (en) | 1994-07-19 |
DE69224315D1 (de) | 1998-03-12 |
EP0510607A1 (de) | 1992-10-28 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |