DE69119141D1 - Halbleiterspeicheranordnung - Google Patents

Halbleiterspeicheranordnung

Info

Publication number
DE69119141D1
DE69119141D1 DE69119141T DE69119141T DE69119141D1 DE 69119141 D1 DE69119141 D1 DE 69119141D1 DE 69119141 T DE69119141 T DE 69119141T DE 69119141 T DE69119141 T DE 69119141T DE 69119141 D1 DE69119141 D1 DE 69119141D1
Authority
DE
Germany
Prior art keywords
memory device
semiconductor memory
semiconductor
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69119141T
Other languages
English (en)
Other versions
DE69119141T2 (de
Inventor
Yoshinori Matsui
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Memory Japan Ltd
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE69119141D1 publication Critical patent/DE69119141D1/de
Publication of DE69119141T2 publication Critical patent/DE69119141T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
DE69119141T 1990-06-04 1991-06-04 Halbleiterspeicheranordnung Expired - Fee Related DE69119141T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14571690 1990-06-04

Publications (2)

Publication Number Publication Date
DE69119141D1 true DE69119141D1 (de) 1996-06-05
DE69119141T2 DE69119141T2 (de) 1996-10-31

Family

ID=15391478

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69119141T Expired - Fee Related DE69119141T2 (de) 1990-06-04 1991-06-04 Halbleiterspeicheranordnung

Country Status (4)

Country Link
US (1) US5369613A (de)
EP (1) EP0460619B1 (de)
KR (1) KR950008672B1 (de)
DE (1) DE69119141T2 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0158027B1 (ko) * 1993-12-29 1999-02-01 모리시다 요이치 반도체집적회로
US5475637A (en) * 1994-12-27 1995-12-12 United Microelectronics Corp. Active bit-line clamp circuit for flat cell structure of mask read-only memory
JPH11203870A (ja) * 1998-01-05 1999-07-30 Mitsubishi Electric Corp Ｉ／ｏクランプ回路を備えた半導体装置
US7227804B1 (en) * 2004-04-19 2007-06-05 Cypress Semiconductor Corporation Current source architecture for memory device standby current reduction
US8553472B2 (en) 2011-12-05 2013-10-08 Apple Inc. Memory with a shared I/O including an output data latch having an integrated clamp

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5833635B2 (ja) * 1979-12-25 1983-07-21 富士通株式会社 半導体記憶装置
US4376987A (en) * 1980-08-18 1983-03-15 Mcdonnell Douglas Corporation Threshold referenced MNOS sense amplifier
JPS60140594A (ja) * 1983-12-28 1985-07-25 Fujitsu Ltd センス回路
JPS61239493A (ja) * 1985-04-05 1986-10-24 Fujitsu Ltd 半導体記憶装置
JPS62145595A (ja) * 1985-12-20 1987-06-29 Toshiba Corp 半導体記憶装置
US4785427A (en) * 1987-01-28 1988-11-15 Cypress Semiconductor Corporation Differential bit line clamp
US4825413A (en) * 1987-02-24 1989-04-25 Texas Instruments Incorporated Bipolar-CMOS static ram memory device
JPH0814989B2 (ja) * 1989-05-09 1996-02-14 日本電気株式会社 内部同期型スタティックｒａｍ

Also Published As

Publication number Publication date
KR920001526A (ko) 1992-01-30
EP0460619B1 (de) 1996-05-01
EP0460619A2 (de) 1991-12-11
DE69119141T2 (de) 1996-10-31
KR950008672B1 (ko) 1995-08-04
EP0460619A3 (en) 1993-02-24
US5369613A (en) 1994-11-29

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NEC CORP., TOKIO/TOKYO, JP

Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP

8327 Change in the person/name/address of the patent owner

Owner name: ELPIDA MEMORY, INC., TOKYO, JP

8339 Ceased/non-payment of the annual fee