DE69128819D1 - Halbleiterspeicheranordnung - Google Patents

Halbleiterspeicheranordnung

Info

Publication number
DE69128819D1
DE69128819D1 DE69128819T DE69128819T DE69128819D1 DE 69128819 D1 DE69128819 D1 DE 69128819D1 DE 69128819 T DE69128819 T DE 69128819T DE 69128819 T DE69128819 T DE 69128819T DE 69128819 D1 DE69128819 D1 DE 69128819D1
Authority
DE
Germany
Prior art keywords
memory device
semiconductor memory
semiconductor
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69128819T
Other languages
English (en)
Other versions
DE69128819T2 (de
Inventor
Hisayuki Nagamine
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE69128819D1 publication Critical patent/DE69128819D1/de
Publication of DE69128819T2 publication Critical patent/DE69128819T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/418—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE69128819T 1990-08-13 1991-08-12 Halbleiterspeicheranordnung Expired - Fee Related DE69128819T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21391990 1990-08-13

Publications (2)

Publication Number Publication Date
DE69128819D1 true DE69128819D1 (de) 1998-03-05
DE69128819T2 DE69128819T2 (de) 1998-05-14

Family

ID=16647217

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69128819T Expired - Fee Related DE69128819T2 (de) 1990-08-13 1991-08-12 Halbleiterspeicheranordnung

Country Status (4)

Country Link
US (1) US5534724A (de)
EP (1) EP0471535B1 (de)
KR (1) KR950011645B1 (de)
DE (1) DE69128819T2 (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6212089B1 (en) * 1996-03-19 2001-04-03 Hitachi, Ltd. Semiconductor memory device and defect remedying method thereof
DE69517693T2 (de) * 1995-12-29 2001-03-01 St Microelectronics Srl Standardzellenbibliothek für den Entwurf von integrierten Schaltungen
JP3311244B2 (ja) 1996-07-15 2002-08-05 株式会社東芝 基本セルライブラリ及びその形成方法
TW306054B (en) * 1996-07-16 1997-05-21 Winbond Electronics Corp Bit line pull up circuit of static random access memory
JP2000077609A (ja) 1998-08-28 2000-03-14 Hitachi Ltd 半導体集積回路装置
US6381166B1 (en) * 1998-09-28 2002-04-30 Texas Instruments Incorporated Semiconductor memory device having variable pitch array
KR100291384B1 (ko) * 1998-12-31 2001-07-12 윤종용 반도체장치의레이아웃방법
JP3408466B2 (ja) * 1999-08-23 2003-05-19 エヌイーシーマイクロシステム株式会社 半導体記憶装置
JP2001068635A (ja) * 1999-08-27 2001-03-16 Mitsubishi Electric Corp 半導体装置
JP4068340B2 (ja) * 2001-12-17 2008-03-26 エルピーダメモリ株式会社 半導体集積回路装置
JP4388274B2 (ja) 2002-12-24 2009-12-24 株式会社ルネサステクノロジ 半導体記憶装置
JP4599048B2 (ja) * 2003-10-02 2010-12-15 川崎マイクロエレクトロニクス株式会社 半導体集積回路のレイアウト構造、半導体集積回路のレイアウト方法、およびフォトマスク
JP2007129026A (ja) * 2005-11-02 2007-05-24 Nec Electronics Corp 半導体装置および配線パターン形成方法、マスク配線データ発生方法
CN101673735B (zh) * 2008-09-12 2011-11-16 台湾积体电路制造股份有限公司 默认多晶硅间距设计规则下的混合多晶硅间距单元设计结构及系统
US7932566B2 (en) * 2008-12-31 2011-04-26 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and system of mixing poly pitch cell design under default poly pitch design rules

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58111183A (ja) * 1981-12-25 1983-07-02 Hitachi Ltd ダイナミツクｒａｍ集積回路装置
JPH0658947B2 (ja) * 1984-02-24 1994-08-03 株式会社日立製作所 半導体メモリ装置の製法
US4891792A (en) * 1987-09-04 1990-01-02 Hitachi, Ltd. Static type semiconductor memory with multi-stage sense amplifier
JPH0828467B2 (ja) * 1988-11-15 1996-03-21 株式会社東芝 半導体装置

Also Published As

Publication number Publication date
KR950011645B1 (ko) 1995-10-07
EP0471535A3 (en) 1993-08-18
EP0471535B1 (de) 1998-01-28
KR920005341A (ko) 1992-03-28
DE69128819T2 (de) 1998-05-14
EP0471535A2 (de) 1992-02-19
US5534724A (en) 1996-07-09

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP

8339 Ceased/non-payment of the annual fee