DE69122293D1 - Halbleiterspeicheranordnung - Google Patents

Halbleiterspeicheranordnung

Info

Publication number
DE69122293D1
DE69122293D1 DE69122293T DE69122293T DE69122293D1 DE 69122293 D1 DE69122293 D1 DE 69122293D1 DE 69122293 T DE69122293 T DE 69122293T DE 69122293 T DE69122293 T DE 69122293T DE 69122293 D1 DE69122293 D1 DE 69122293D1
Authority
DE
Germany
Prior art keywords
memory device
semiconductor memory
semiconductor
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69122293T
Other languages
English (en)
Other versions
DE69122293T2 (de
Inventor
Yasuharu Hoshino
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Memory Japan Ltd
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE69122293D1 publication Critical patent/DE69122293D1/de
Publication of DE69122293T2 publication Critical patent/DE69122293T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/106—Data output latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Databases & Information Systems (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
DE69122293T 1990-04-27 1991-04-26 Halbleiterspeicheranordnung Expired - Lifetime DE69122293T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP11241490 1990-04-27
JP11226690 1990-04-28

Publications (2)

Publication Number Publication Date
DE69122293D1 true DE69122293D1 (de) 1996-10-31
DE69122293T2 DE69122293T2 (de) 1997-04-24

Family

ID=26451481

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69122293T Expired - Lifetime DE69122293T2 (de) 1990-04-27 1991-04-26 Halbleiterspeicheranordnung

Country Status (4)

Country Link
US (1) US5463584A (de)
EP (1) EP0454162B1 (de)
KR (1) KR960015210B1 (de)
DE (1) DE69122293T2 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07326192A (ja) * 1994-05-31 1995-12-12 Toshiba Micro Comput Eng Corp 半導体記憶装置
TW358907B (en) * 1994-11-22 1999-05-21 Monolithic System Tech Inc A computer system and a method of using a DRAM array as a next level cache memory
JP3576561B2 (ja) * 1994-11-22 2004-10-13 モノリシック・システム・テクノロジー・インコーポレイテッド 第２レベルのキャシュメモリとしてｄｒａｍアレイを用いる方法及び構成
US6128700A (en) 1995-05-17 2000-10-03 Monolithic System Technology, Inc. System utilizing a DRAM array as a next level cache memory and method for operating same
JP2783214B2 (ja) * 1995-09-18 1998-08-06 日本電気株式会社 半導体メモリ装置
US5745423A (en) * 1996-12-17 1998-04-28 Powerchip Semiconductor Corp. Low power precharge circuit for a dynamic random access memory
JP4191218B2 (ja) * 2006-10-12 2008-12-03 エルピーダメモリ株式会社 メモリ回路及び半導体装置
JP2015032327A (ja) * 2013-07-31 2015-02-16 ルネサスエレクトロニクス株式会社 半導体装置、及びデータ読み出し方法
US9601167B1 (en) 2015-03-02 2017-03-21 Michael C. Stephens, Jr. Semiconductor device having dual-gate transistors and calibration circuitry

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4603403A (en) * 1983-05-17 1986-07-29 Kabushiki Kaisha Toshiba Data output circuit for dynamic memory device
US4577293A (en) * 1984-06-01 1986-03-18 International Business Machines Corporation Distributed, on-chip cache
US4658377A (en) * 1984-07-26 1987-04-14 Texas Instruments Incorporated Dynamic memory array with segmented bit lines
US4764901A (en) * 1984-08-03 1988-08-16 Kabushiki Kaisha Toshiba Semiconductor memory device capable of being accessed before completion of data output
JPS62231495A (ja) * 1986-03-31 1987-10-12 Toshiba Corp 半導体記憶装置
JPS62287497A (ja) * 1986-06-06 1987-12-14 Fujitsu Ltd 半導体記憶装置
JPH0752583B2 (ja) * 1987-11-30 1995-06-05 株式会社東芝 半導体メモリ
JP2591010B2 (ja) * 1988-01-29 1997-03-19 日本電気株式会社 シリアルアクセスメモリ装置
US4954987A (en) * 1989-07-17 1990-09-04 Advanced Micro Devices, Inc. Interleaved sensing system for FIFO and burst-mode memories

Also Published As

Publication number Publication date
DE69122293T2 (de) 1997-04-24
EP0454162A2 (de) 1991-10-30
EP0454162A3 (en) 1993-02-03
US5463584A (en) 1995-10-31
EP0454162B1 (de) 1996-09-25
KR910019057A (ko) 1991-11-30
KR960015210B1 (ko) 1996-11-01

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NEC CORP., TOKIO/TOKYO, JP

Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP

8327 Change in the person/name/address of the patent owner

Owner name: ELPIDA MEMORY, INC., TOKYO, JP