DE69220101D1 - Halbleiterspeichereinrichtung - Google Patents

Halbleiterspeichereinrichtung

Info

Publication number
DE69220101D1
DE69220101D1 DE69220101T DE69220101T DE69220101D1 DE 69220101 D1 DE69220101 D1 DE 69220101D1 DE 69220101 T DE69220101 T DE 69220101T DE 69220101 T DE69220101 T DE 69220101T DE 69220101 D1 DE69220101 D1 DE 69220101D1
Authority
DE
Germany
Prior art keywords
memory device
semiconductor memory
semiconductor
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69220101T
Other languages
English (en)
Other versions
DE69220101T2 (de
Inventor
Tohru Furuyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE69220101D1 publication Critical patent/DE69220101D1/de
Publication of DE69220101T2 publication Critical patent/DE69220101T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/106—Data output latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
DE69220101T 1991-02-13 1992-02-13 Halbleiterspeichereinrichtung Expired - Fee Related DE69220101T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3041315A JP2564046B2 (ja) 1991-02-13 1991-02-13 半導体記憶装置

Publications (2)

Publication Number Publication Date
DE69220101D1 true DE69220101D1 (de) 1997-07-10
DE69220101T2 DE69220101T2 (de) 1997-10-16

Family

ID=12605081

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69220101T Expired - Fee Related DE69220101T2 (de) 1991-02-13 1992-02-13 Halbleiterspeichereinrichtung

Country Status (5)

Country Link
US (2) US5444652A (de)
EP (1) EP0499256B1 (de)
JP (1) JP2564046B2 (de)
KR (1) KR950005515B1 (de)
DE (1) DE69220101T2 (de)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0543613B1 (de) * 1991-11-18 1998-04-08 Kabushiki Kaisha Toshiba Dynamische Halbleiterspeicheranordnung
JP3302726B2 (ja) * 1992-07-31 2002-07-15 株式会社東芝 半導体記憶装置
US5717625A (en) * 1993-12-27 1998-02-10 Kabushiki Kaisha Toshiba Semiconductor memory device
US5596521A (en) * 1994-01-06 1997-01-21 Oki Electric Industry Co., Ltd. Semiconductor memory with built-in cache
US6320778B1 (en) 1994-01-06 2001-11-20 Oki Electric Industry Co., Ltd. Semiconductor memory with built-in cache
EP0681279B1 (de) * 1994-05-03 2001-07-18 Sun Microsystems, Inc. Direktzugriffspeicher und System für Rasterpuffer
US5513148A (en) * 1994-12-01 1996-04-30 Micron Technology Inc. Synchronous NAND DRAM architecture
JP2783271B2 (ja) * 1995-01-30 1998-08-06 日本電気株式会社 半導体記憶装置
US5898856A (en) 1995-09-15 1999-04-27 Intel Corporation Method and apparatus for automatically detecting a selected cache type
US5936874A (en) * 1997-06-19 1999-08-10 Micron Technology, Inc. High density semiconductor memory and method of making
JP3492168B2 (ja) * 1997-10-21 2004-02-03 シャープ株式会社 不揮発性半導体記憶装置
FR2776819B1 (fr) * 1998-03-26 2001-11-02 Sgs Thomson Microelectronics Dram a structure rapide
FR2801410B1 (fr) * 1999-11-24 2003-10-17 St Microelectronics Sa Dispositif de memoire vive dynamique, et procede de lecture correspondant
JP2005340356A (ja) * 2004-05-25 2005-12-08 Hitachi Ltd 半導体記憶装置
US20110128807A1 (en) * 2009-12-01 2011-06-02 Freescale Semiconductor, Inc Memory device and sense circuitry therefor
TWI552150B (zh) * 2011-05-18 2016-10-01 半導體能源研究所股份有限公司 半導體儲存裝置
US9978435B1 (en) * 2017-01-25 2018-05-22 Winbond Electronics Corporation Memory device and operation methods thereof

Family Cites Families (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL6807435A (de) * 1968-05-25 1969-11-27
US3763480A (en) * 1971-10-12 1973-10-02 Rca Corp Digital and analog data handling devices
DE2634089B2 (de) * 1975-08-11 1978-01-05 Schaltungsanordnung zum erfassen schwacher signale
US4225945A (en) * 1976-01-12 1980-09-30 Texas Instruments Incorporated Random access MOS memory cell using double level polysilicon
JPS5848294A (ja) * 1981-09-16 1983-03-22 Mitsubishi Electric Corp Ｍｏｓダイナミツクメモリ
US4669063A (en) * 1982-12-30 1987-05-26 Thomson Components-Mostek Corp. Sense amplifier for a dynamic RAM
JPS60209996A (ja) * 1984-03-31 1985-10-22 Toshiba Corp 半導体記憶装置
JPH0793009B2 (ja) * 1984-12-13 1995-10-09 株式会社東芝 半導体記憶装置
US4648073A (en) * 1984-12-31 1987-03-03 International Business Machines Corporation Sequential shared access lines memory cells
JPS63149900A (ja) * 1986-12-15 1988-06-22 Toshiba Corp 半導体メモリ
US4980863A (en) * 1987-03-31 1990-12-25 Kabushiki Kaisha Toshiba Semiconductor memory device having switching circuit for coupling together two pairs of bit lines
US4903242A (en) * 1987-05-06 1990-02-20 Nec Corporation Serial access memory circuit with improved serial addressing circuit composed of a shift register
JP2582587B2 (ja) * 1987-09-18 1997-02-19 日本テキサス・インスツルメンツ株式会社 半導体記憶装置
JPH01134796A (ja) * 1987-11-19 1989-05-26 Mitsubishi Electric Corp 不揮発性半導体記憶装置
US4943944A (en) * 1987-11-25 1990-07-24 Kabushiki Kaisha Toshiba Semiconductor memory using dynamic ram cells
JPH01204298A (ja) * 1988-02-08 1989-08-16 Fujitsu Ltd 半導体記憶回路
JP2682021B2 (ja) * 1988-06-29 1997-11-26 富士通株式会社 半導体メモリ装置
US5091761A (en) * 1988-08-22 1992-02-25 Hitachi, Ltd. Semiconductor device having an arrangement of IGFETs and capacitors stacked thereover
JP2633645B2 (ja) * 1988-09-13 1997-07-23 株式会社東芝 半導体メモリ装置
JPH0283891A (ja) * 1988-09-20 1990-03-23 Fujitsu Ltd 半導体メモリ
EP0365720B1 (de) * 1988-10-24 1996-04-03 Kabushiki Kaisha Toshiba Programmierbarer Halbleiterspeicher
US5172198A (en) * 1989-02-22 1992-12-15 Kabushiki Kaisha Toshiba MOS type semiconductor device
DE58908918D1 (de) * 1989-03-16 1995-03-02 Siemens Ag Integrierter Halbleiterspeicher vom Typ DRAM und Verfahren zu seinem Testen.
JPH0762955B2 (ja) * 1989-05-15 1995-07-05 株式会社東芝 ダイナミック型ランダムアクセスメモリ
JPH02301097A (ja) * 1989-05-15 1990-12-13 Toshiba Corp ダイナミック型ランダムアクセスメモリ
JPH0358377A (ja) * 1989-07-24 1991-03-13 Mitsubishi Electric Corp ダイナミックｒａｍ用メモリセル回路
JPH0369092A (ja) * 1989-05-16 1991-03-25 Mitsubishi Electric Corp ダイナミックｒａｍ用メモリセル回路
DE4015472C2 (de) * 1989-05-16 1993-12-02 Mitsubishi Electric Corp Speicherzelle und Verfahren zum Herstellen eines dynamischen RAM
US5005158A (en) * 1990-01-12 1991-04-02 Sgs-Thomson Microelectronics, Inc. Redundancy for serial memory
JPH07122989B2 (ja) * 1990-06-27 1995-12-25 株式会社東芝 半導体記憶装置
JP2660111B2 (ja) * 1991-02-13 1997-10-08 株式会社東芝 半導体メモリセル

Also Published As

Publication number Publication date
JP2564046B2 (ja) 1996-12-18
DE69220101T2 (de) 1997-10-16
EP0499256B1 (de) 1997-06-04
US5432733A (en) 1995-07-11
KR920017105A (ko) 1992-09-26
KR950005515B1 (ko) 1995-05-24
US5444652A (en) 1995-08-22
JPH04258878A (ja) 1992-09-14
EP0499256A1 (de) 1992-08-19

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)
8339 Ceased/non-payment of the annual fee