DE69222333T2 - Halbleiterspeicheranordnung - Google Patents

Halbleiterspeicheranordnung

Info

Publication number
DE69222333T2
DE69222333T2 DE69222333T DE69222333T DE69222333T2 DE 69222333 T2 DE69222333 T2 DE 69222333T2 DE 69222333 T DE69222333 T DE 69222333T DE 69222333 T DE69222333 T DE 69222333T DE 69222333 T2 DE69222333 T2 DE 69222333T2
Authority
DE
Germany
Prior art keywords
memory device
semiconductor memory
semiconductor
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69222333T
Other languages
English (en)
Other versions
DE69222333D1 (de
Inventor
Junichi Suyama
Yoshihiro Murashima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Publication of DE69222333D1 publication Critical patent/DE69222333D1/de
Application granted granted Critical
Publication of DE69222333T2 publication Critical patent/DE69222333T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/106—Data output latches
DE69222333T 1991-02-19 1992-02-18 Halbleiterspeicheranordnung Expired - Fee Related DE69222333T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3024736A JP2977296B2 (ja) 1991-02-19 1991-02-19 半導体メモリ装置

Publications (2)

Publication Number Publication Date
DE69222333D1 DE69222333D1 (de) 1997-10-30
DE69222333T2 true DE69222333T2 (de) 1998-04-30

Family

ID=12146436

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69222333T Expired - Fee Related DE69222333T2 (de) 1991-02-19 1992-02-18 Halbleiterspeicheranordnung

Country Status (4)

Country Link
US (1) US5260903A (de)
EP (1) EP0500304B1 (de)
JP (1) JP2977296B2 (de)
DE (1) DE69222333T2 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06334513A (ja) * 1993-05-13 1994-12-02 Intel Corp データ処理装置
JP3317746B2 (ja) * 1993-06-18 2002-08-26 富士通株式会社 半導体記憶装置
US6112284A (en) * 1994-12-30 2000-08-29 Intel Corporation Method and apparatus for latching data from a memory resource at a datapath unit
KR0120592B1 (ko) * 1994-09-09 1997-10-20 김주용 신호 변환 장치를 갖고 있는 어드레스 입력버퍼
US5568429A (en) * 1995-07-05 1996-10-22 Sun Microsystems, Inc. Low power data latch with overdriven clock signals
JP2005092963A (ja) * 2003-09-16 2005-04-07 Renesas Technology Corp 不揮発性記憶装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58169383A (ja) * 1982-03-30 1983-10-05 Fujitsu Ltd 半導体記憶装置
JPS60175293A (ja) * 1984-02-21 1985-09-09 Toshiba Corp 半導体メモリ
US4797573A (en) * 1984-11-21 1989-01-10 Nec Corporation Output circuit with improved timing control circuit
JPH0612632B2 (ja) * 1987-02-27 1994-02-16 日本電気株式会社 メモリ回路
JP2590122B2 (ja) * 1987-08-07 1997-03-12 富士通株式会社 半導体メモリ
DE69023556T2 (de) * 1989-06-26 1996-07-18 Nec Corp Halbleiterspeicher mit einem verbesserten Datenleseschema.
JP2534782B2 (ja) * 1989-11-10 1996-09-18 株式会社東芝 半導体装置

Also Published As

Publication number Publication date
JPH04265598A (ja) 1992-09-21
DE69222333D1 (de) 1997-10-30
EP0500304A3 (en) 1993-07-28
EP0500304B1 (de) 1997-09-24
US5260903A (en) 1993-11-09
JP2977296B2 (ja) 1999-11-15
EP0500304A2 (de) 1992-08-26

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee