DE69223333D1 - Halbleiterspeicheranordnung - Google Patents

Halbleiterspeicheranordnung

Info

Publication number
DE69223333D1
DE69223333D1 DE69223333T DE69223333T DE69223333D1 DE 69223333 D1 DE69223333 D1 DE 69223333D1 DE 69223333 T DE69223333 T DE 69223333T DE 69223333 T DE69223333 T DE 69223333T DE 69223333 D1 DE69223333 D1 DE 69223333D1
Authority
DE
Germany
Prior art keywords
memory device
semiconductor memory
semiconductor
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69223333T
Other languages
English (en)
Other versions
DE69223333T2 (de
Inventor
Yasuhiro Hotta
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Publication of DE69223333D1 publication Critical patent/DE69223333D1/de
Application granted granted Critical
Publication of DE69223333T2 publication Critical patent/DE69223333T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/08—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
    • G11C17/10—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM
    • G11C17/12—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM using field-effect devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)
DE69223333T 1991-02-13 1992-02-13 Halbleiterspeicheranordnung Expired - Fee Related DE69223333T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007891A JP2680936B2 (ja) 1991-02-13 1991-02-13 半導体記憶装置

Publications (2)

Publication Number Publication Date
DE69223333D1 true DE69223333D1 (de) 1998-01-15
DE69223333T2 DE69223333T2 (de) 1998-05-28

Family

ID=12017067

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69223333T Expired - Fee Related DE69223333T2 (de) 1991-02-13 1992-02-13 Halbleiterspeicheranordnung

Country Status (5)

Country Link
US (1) US5291452A (de)
EP (1) EP0499460B1 (de)
JP (1) JP2680936B2 (de)
KR (1) KR950001429B1 (de)
DE (1) DE69223333T2 (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3118472B2 (ja) * 1991-08-09 2000-12-18 富士通株式会社 出力回路
US5455802A (en) * 1992-12-22 1995-10-03 Sgs-Thomson Microelectronics, Inc. Dual dynamic sense amplifiers for a memory array
US6738357B1 (en) * 1993-06-09 2004-05-18 Btg International Inc. Method and apparatus for multiple media digital communication system
KR0172371B1 (ko) * 1995-04-26 1999-03-30 윤종용 반도체 메모리장치의 전원전압 발생회로
GB2304244B (en) * 1995-08-10 2000-01-26 Advanced Risc Mach Ltd Data processing system signal receiving buffers
DE19536486C2 (de) * 1995-09-29 1997-08-07 Siemens Ag Bewerter- und Verstärkerschaltung
JP3219236B2 (ja) * 1996-02-22 2001-10-15 シャープ株式会社 半導体記憶装置
US5668766A (en) * 1996-05-16 1997-09-16 Intel Corporation Method and apparatus for increasing memory read access speed using double-sensing
US5805006A (en) * 1997-04-28 1998-09-08 Marvell Technology Group, Ltd. Controllable integrator
KR100249160B1 (ko) * 1997-08-20 2000-03-15 김영환 반도체 메모리장치
JPH11203881A (ja) * 1998-01-12 1999-07-30 Mitsubishi Electric Corp データ読み出し回路
EP1647989A1 (de) 2004-10-18 2006-04-19 Dialog Semiconductor GmbH Dynamische Anpassung von Speicher-Leseschaltungen
WO2009013814A1 (ja) * 2007-07-24 2009-01-29 Fujitsu Limited 半導体装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5856198B2 (ja) * 1980-09-25 1983-12-13 株式会社東芝 半導体記憶装置
US4907201A (en) * 1986-05-07 1990-03-06 Mitsubishi Denki Kabushiki Kaisha MOS transistor circuit
JPS6386188A (ja) * 1986-09-30 1988-04-16 Toshiba Corp ダイナミツク型半導体記憶装置
JPS63171497A (ja) * 1987-01-08 1988-07-15 Mitsubishi Electric Corp 半導体集積回路装置
JPH0646513B2 (ja) * 1989-07-12 1994-06-15 株式会社東芝 半導体記憶装置のデータ読出回路
US4954987A (en) * 1989-07-17 1990-09-04 Advanced Micro Devices, Inc. Interleaved sensing system for FIFO and burst-mode memories

Also Published As

Publication number Publication date
EP0499460A3 (en) 1993-10-06
JP2680936B2 (ja) 1997-11-19
KR950001429B1 (ko) 1995-02-24
KR920017115A (ko) 1992-09-26
DE69223333T2 (de) 1998-05-28
US5291452A (en) 1994-03-01
EP0499460B1 (de) 1997-12-03
EP0499460A2 (de) 1992-08-19
JPH04258895A (ja) 1992-09-14

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee