WO2009013814A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

Info

Publication number
WO2009013814A1
WO2009013814A1 PCT/JP2007/064523 JP2007064523W WO2009013814A1 WO 2009013814 A1 WO2009013814 A1 WO 2009013814A1 JP 2007064523 W JP2007064523 W JP 2007064523W WO 2009013814 A1 WO2009013814 A1 WO 2009013814A1
Authority
WO
WIPO (PCT)
Prior art keywords
buffer circuit
input signals
transition
signals
semiconductor device
Prior art date
Application number
PCT/JP2007/064523
Other languages
English (en)
French (fr)
Inventor
Yoshiyasu Doi
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to JP2009524341A priority Critical patent/JPWO2009013814A1/ja
Priority to PCT/JP2007/064523 priority patent/WO2009013814A1/ja
Publication of WO2009013814A1 publication Critical patent/WO2009013814A1/ja
Priority to US12/692,185 priority patent/US20100117690A1/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
    • H03K19/018528—Interface arrangements of complementary type, e.g. CMOS with at least one differential stage

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Amplifiers (AREA)
  • Electronic Switches (AREA)

Abstract

　入力信号を伝送する高速動作が可能な第１のバッファ回路と、第１のバッファ回路よりも駆動能力が低くかつ入力信号を伝送する第２のバッファ回路と、入力信号の遷移を検知し信号が遷移している期間は、第１のバッファ回路を活性化する制御回路とを備え、入力信号が遷移したときには第１のバッファ回路により出力信号を変化させ、出力信号の振幅を維持するときには、第１のバッファ回路を不活性状態にして第２のバッファ回路により振幅を維持するようにして、高速動作性能を有しながらも、低周波数動作時には消費電力を削減することができるようにする。
PCT/JP2007/064523 2007-07-24 2007-07-24 半導体装置 WO2009013814A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2009524341A JPWO2009013814A1 (ja) 2007-07-24 2007-07-24 半導体装置
PCT/JP2007/064523 WO2009013814A1 (ja) 2007-07-24 2007-07-24 半導体装置
US12/692,185 US20100117690A1 (en) 2007-07-24 2010-01-22 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/064523 WO2009013814A1 (ja) 2007-07-24 2007-07-24 半導体装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/692,185 Continuation US20100117690A1 (en) 2007-07-24 2010-01-22 Semiconductor device

Publications (1)

Publication Number Publication Date
WO2009013814A1 true WO2009013814A1 (ja) 2009-01-29

Family

ID=40281077

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/064523 WO2009013814A1 (ja) 2007-07-24 2007-07-24 半導体装置

Country Status (3)

Country Link
US (1) US20100117690A1 (ja)
JP (1) JPWO2009013814A1 (ja)
WO (1) WO2009013814A1 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015002408A (ja) * 2013-06-14 2015-01-05 富士通株式会社 伝送回路および出力回路

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US8358156B1 (en) * 2010-05-28 2013-01-22 Xilinx, Inc. Voltage mode line driver and pre-emphasis circuit
KR20140132277A (ko) * 2013-05-07 2014-11-17 포항공과대학교 산학협력단 계수 오류 로버스트 피드포워드등화기
US10009023B2 (en) * 2016-04-04 2018-06-26 Mediatek Inc. Method and apparatus for edge equalization for high speed drivers
KR20190075203A (ko) * 2017-12-21 2019-07-01 에스케이하이닉스 주식회사 하이브리드 버퍼 회로

Citations (5)

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JPH0362723A (ja) * 1989-07-31 1991-03-18 Nec Corp 出力バッファ回路
JPH08335868A (ja) * 1995-06-06 1996-12-17 Fujitsu Ltd バッファ回路
JP2002368600A (ja) * 2001-06-08 2002-12-20 Mitsubishi Electric Corp プリエンファシス回路
JP2004357004A (ja) * 2003-05-29 2004-12-16 Nec Electronics Corp トランスミッタ回路、伝送回路及び駆動装置
JP2005217999A (ja) * 2004-02-02 2005-08-11 Hitachi Ltd デジタルデータ伝送回路

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JP2680936B2 (ja) * 1991-02-13 1997-11-19 シャープ株式会社 半導体記憶装置
DE69334054T2 (de) * 1992-06-15 2006-12-07 Fujitsu Ltd., Kawasaki Integrierte Halbleiterschaltung mit Eingangs/Ausgangschnittstelle geeignet für niedrige Amplituden
JP3444653B2 (ja) * 1994-06-09 2003-09-08 三菱電機株式会社 電力増幅器
JP3157683B2 (ja) * 1994-08-30 2001-04-16 株式会社 沖マイクロデザイン 半導体集積回路の静止時電流測定法、半導体集積回路
US5574401A (en) * 1995-06-02 1996-11-12 Analog Devices, Inc. Large common mode input range CMOS amplifier
KR100190763B1 (ko) * 1995-12-29 1999-06-01 김영환 차동 증폭기
JP2000306382A (ja) * 1999-02-17 2000-11-02 Hitachi Ltd 半導体集積回路装置
US6763470B1 (en) * 1999-05-19 2004-07-13 Globespanvirata, Inc. System and method for dynamically amplifying a delayed analog signal based on amplitude information obtained from its digital representation
US7049857B2 (en) * 2002-01-17 2006-05-23 International Business Machines Corporation Asymmetric comparator for low power applications
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JP2006333060A (ja) * 2005-05-26 2006-12-07 Renesas Technology Corp 高周波電力増幅及びそれを用いた無線通信装置
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JP2008035487A (ja) * 2006-06-19 2008-02-14 Renesas Technology Corp Ｒｆ電力増幅器
US7382197B2 (en) * 2006-09-08 2008-06-03 Intel Corporation Adaptive tuning circuit to maximize output signal amplitude for an amplifier
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Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0362723A (ja) * 1989-07-31 1991-03-18 Nec Corp 出力バッファ回路
JPH08335868A (ja) * 1995-06-06 1996-12-17 Fujitsu Ltd バッファ回路
JP2002368600A (ja) * 2001-06-08 2002-12-20 Mitsubishi Electric Corp プリエンファシス回路
JP2004357004A (ja) * 2003-05-29 2004-12-16 Nec Electronics Corp トランスミッタ回路、伝送回路及び駆動装置
JP2005217999A (ja) * 2004-02-02 2005-08-11 Hitachi Ltd デジタルデータ伝送回路

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015002408A (ja) * 2013-06-14 2015-01-05 富士通株式会社 伝送回路および出力回路

Also Published As

Publication number Publication date
US20100117690A1 (en) 2010-05-13
JPWO2009013814A1 (ja) 2010-09-24

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