DE69121801D1 - Halbleiterspeicheranordnung - Google Patents

Halbleiterspeicheranordnung

Info

Publication number
DE69121801D1
DE69121801D1 DE69121801T DE69121801T DE69121801D1 DE 69121801 D1 DE69121801 D1 DE 69121801D1 DE 69121801 T DE69121801 T DE 69121801T DE 69121801 T DE69121801 T DE 69121801T DE 69121801 D1 DE69121801 D1 DE 69121801D1
Authority
DE
Germany
Prior art keywords
memory device
semiconductor memory
semiconductor
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69121801T
Other languages
English (en)
Other versions
DE69121801T2 (de
Inventor
Tohru Furuyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE69121801D1 publication Critical patent/DE69121801D1/de
Publication of DE69121801T2 publication Critical patent/DE69121801T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/565—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using capacitive charge storage elements

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
  • Semiconductor Memories (AREA)
DE69121801T 1990-06-27 1991-06-26 Halbleiterspeicheranordnung Expired - Lifetime DE69121801T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP16691490 1990-06-27
JP3041316A JPH07122989B2 (ja) 1990-06-27 1991-02-13 半導体記憶装置

Publications (2)

Publication Number Publication Date
DE69121801D1 true DE69121801D1 (de) 1996-10-10
DE69121801T2 DE69121801T2 (de) 1997-02-13

Family

ID=26380902

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69121801T Expired - Lifetime DE69121801T2 (de) 1990-06-27 1991-06-26 Halbleiterspeicheranordnung

Country Status (5)

Country Link
US (2) US5369612A (de)
EP (1) EP0463617B1 (de)
JP (1) JPH07122989B2 (de)
KR (1) KR950009389B1 (de)
DE (1) DE69121801T2 (de)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07122989B2 (ja) * 1990-06-27 1995-12-25 株式会社東芝 半導体記憶装置
JP2564046B2 (ja) * 1991-02-13 1996-12-18 株式会社東芝 半導体記憶装置
DE69222793T2 (de) * 1991-03-14 1998-03-12 Toshiba Kawasaki Kk Halbleiterspeicheranordnung
US5625602A (en) * 1991-11-18 1997-04-29 Kabushiki Kaisha Toshiba NAND-type dynamic RAM having temporary storage register and sense amplifier coupled to multi-open bit lines
JP3464803B2 (ja) * 1991-11-27 2003-11-10 株式会社東芝 半導体メモリセル
JP3253745B2 (ja) * 1993-04-28 2002-02-04 富士通株式会社 半導体記憶装置
JP3237971B2 (ja) * 1993-09-02 2001-12-10 株式会社東芝 半導体記憶装置
JP3272888B2 (ja) * 1993-12-28 2002-04-08 株式会社東芝 半導体記憶装置
US5555203A (en) * 1993-12-28 1996-09-10 Kabushiki Kaisha Toshiba Dynamic semiconductor memory device
US5452244A (en) * 1994-08-10 1995-09-19 Cirrus Logic, Inc. Electronic memory and methods for making and using the same
JPH08167285A (ja) * 1994-12-07 1996-06-25 Toshiba Corp 半導体記憶装置
JP2783271B2 (ja) * 1995-01-30 1998-08-06 日本電気株式会社 半導体記憶装置
US6512257B2 (en) * 1995-11-09 2003-01-28 Hitachi, Inc. System with meshed power and signal buses on cell array
US6831317B2 (en) * 1995-11-09 2004-12-14 Hitachi, Ltd. System with meshed power and signal buses on cell array
US5663916A (en) * 1996-05-21 1997-09-02 Elonex I.P. Holdings, Ltd. Apparatus and method for minimizing DRAM recharge time
US5936874A (en) 1997-06-19 1999-08-10 Micron Technology, Inc. High density semiconductor memory and method of making
FR2773634B1 (fr) * 1998-01-15 2004-01-02 Sgs Thomson Microelectronics Amelioration des memoires a rafraichissement
US6016390A (en) * 1998-01-29 2000-01-18 Artisan Components, Inc. Method and apparatus for eliminating bitline voltage offsets in memory devices
US6990036B2 (en) 2003-12-30 2006-01-24 Intel Corporation Method and apparatus for multiple row caches per bank
US7050351B2 (en) * 2003-12-30 2006-05-23 Intel Corporation Method and apparatus for multiple row caches per bank
JP4832004B2 (ja) * 2005-06-09 2011-12-07 パナソニック株式会社 半導体記憶装置
TWI596769B (zh) * 2011-01-13 2017-08-21 半導體能源研究所股份有限公司 半導體裝置及半導體儲存裝置
US9978435B1 (en) * 2017-01-25 2018-05-22 Winbond Electronics Corporation Memory device and operation methods thereof

Family Cites Families (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL6807435A (de) * 1968-05-25 1969-11-27
US3763480A (en) * 1971-10-12 1973-10-02 Rca Corp Digital and analog data handling devices
DE2634089B2 (de) * 1975-08-11 1978-01-05 Schaltungsanordnung zum erfassen schwacher signale
US4225945A (en) * 1976-01-12 1980-09-30 Texas Instruments Incorporated Random access MOS memory cell using double level polysilicon
JPS5848294A (ja) * 1981-09-16 1983-03-22 Mitsubishi Electric Corp Ｍｏｓダイナミツクメモリ
US4669063A (en) * 1982-12-30 1987-05-26 Thomson Components-Mostek Corp. Sense amplifier for a dynamic RAM
US4583382A (en) * 1983-12-21 1986-04-22 Schlage Lock Company Reversible latch assembly with integrated function
JPS60209996A (ja) * 1984-03-31 1985-10-22 Toshiba Corp 半導体記憶装置
JPH0793009B2 (ja) * 1984-12-13 1995-10-09 株式会社東芝 半導体記憶装置
US4648073A (en) * 1984-12-31 1987-03-03 International Business Machines Corporation Sequential shared access lines memory cells
US4683555A (en) * 1985-01-22 1987-07-28 Texas Instruments Incorporated Serial accessed semiconductor memory with reconfigureable shift registers
JPS63149900A (ja) * 1986-12-15 1988-06-22 Toshiba Corp 半導体メモリ
US4980863A (en) * 1987-03-31 1990-12-25 Kabushiki Kaisha Toshiba Semiconductor memory device having switching circuit for coupling together two pairs of bit lines
JPH01134796A (ja) * 1987-11-19 1989-05-26 Mitsubishi Electric Corp 不揮発性半導体記憶装置
US4943944A (en) * 1987-11-25 1990-07-24 Kabushiki Kaisha Toshiba Semiconductor memory using dynamic ram cells
JPH01204298A (ja) * 1988-02-08 1989-08-16 Fujitsu Ltd 半導体記憶回路
JP2682021B2 (ja) * 1988-06-29 1997-11-26 富士通株式会社 半導体メモリ装置
US5091761A (en) * 1988-08-22 1992-02-25 Hitachi, Ltd. Semiconductor device having an arrangement of IGFETs and capacitors stacked thereover
JP2633645B2 (ja) * 1988-09-13 1997-07-23 株式会社東芝 半導体メモリ装置
EP0365720B1 (de) * 1988-10-24 1996-04-03 Kabushiki Kaisha Toshiba Programmierbarer Halbleiterspeicher
US5172198A (en) * 1989-02-22 1992-12-15 Kabushiki Kaisha Toshiba MOS type semiconductor device
DE58908918D1 (de) * 1989-03-16 1995-03-02 Siemens Ag Integrierter Halbleiterspeicher vom Typ DRAM und Verfahren zu seinem Testen.
JPH0762955B2 (ja) * 1989-05-15 1995-07-05 株式会社東芝 ダイナミック型ランダムアクセスメモリ
JPH02301097A (ja) * 1989-05-15 1990-12-13 Toshiba Corp ダイナミック型ランダムアクセスメモリ
JPH0358377A (ja) * 1989-07-24 1991-03-13 Mitsubishi Electric Corp ダイナミックｒａｍ用メモリセル回路
JPH0369092A (ja) * 1989-05-16 1991-03-25 Mitsubishi Electric Corp ダイナミックｒａｍ用メモリセル回路
DE4015472C2 (de) * 1989-05-16 1993-12-02 Mitsubishi Electric Corp Speicherzelle und Verfahren zum Herstellen eines dynamischen RAM
JPH07122989B2 (ja) * 1990-06-27 1995-12-25 株式会社東芝 半導体記憶装置
JP2660111B2 (ja) * 1991-02-13 1997-10-08 株式会社東芝 半導体メモリセル

Also Published As

Publication number Publication date
US5410505A (en) 1995-04-25
JPH04212780A (ja) 1992-08-04
KR920001536A (ko) 1992-01-30
EP0463617A3 (en) 1993-08-18
US5369612A (en) 1994-11-29
EP0463617A2 (de) 1992-01-02
EP0463617B1 (de) 1996-09-04
DE69121801T2 (de) 1997-02-13
JPH07122989B2 (ja) 1995-12-25
KR950009389B1 (ko) 1995-08-21

Similar Documents

Publication Publication Date Title
DE69133361D1 (de) Halbleiterspeichervorrichtung
DE69132284T2 (de) Halbleiterspeicheranordnung
DE69227723D1 (de) Halbleiterspeicheranordnung
DE69224315D1 (de) Halbleiterspeichervorrichtung
DE69123666D1 (de) Halbleiterspeicheranordnung
DE69125671D1 (de) Halbleiter-Speicherbauteil
DE69125206D1 (de) Halbleiterspeicheranordnung
DE69121801D1 (de) Halbleiterspeicheranordnung
DE69123379D1 (de) Halbleiterspeichervorrichtung
DE69125535D1 (de) Halbleiterspeicheranordnung
DE69127155D1 (de) Halbleiterspeicheranordnung
DE69126559D1 (de) Halbleiterspeicheranordnung
DE69220101D1 (de) Halbleiterspeichereinrichtung
DE69128061D1 (de) Halbleiterspeicheranordnung
DE69125339D1 (de) Halbleiterspeicheranordnung
DE69219518D1 (de) Halbleiterspeicheranordnung
DE69128819D1 (de) Halbleiterspeicheranordnung
DE69222793D1 (de) Halbleiterspeicheranordnung
DE69223333T2 (de) Halbleiterspeicheranordnung
DE69125734D1 (de) Halbleiterspeicheranordnung
DE69123294D1 (de) Halbleiterspeicheranordnung
DE69225298T2 (de) Halbleiterspeichervorrichtung
DE69215555D1 (de) Halbleiterspeicheranordnung
DE69124286D1 (de) Halbleiterspeicheranordnung
DE69122293D1 (de) Halbleiterspeicheranordnung

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)