DE69322725D1 - Halbleiterspeicheranordnung - Google Patents

Halbleiterspeicheranordnung

Info

Publication number
DE69322725D1
DE69322725D1 DE69322725T DE69322725T DE69322725D1 DE 69322725 D1 DE69322725 D1 DE 69322725D1 DE 69322725 T DE69322725 T DE 69322725T DE 69322725 T DE69322725 T DE 69322725T DE 69322725 D1 DE69322725 D1 DE 69322725D1
Authority
DE
Germany
Prior art keywords
memory device
semiconductor memory
semiconductor
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69322725T
Other languages
English (en)
Other versions
DE69322725T2 (de
Inventor
Yuji Nakaoka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE69322725D1 publication Critical patent/DE69322725D1/de
Publication of DE69322725T2 publication Critical patent/DE69322725T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1096—Write circuits, e.g. I/O line write drivers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1045—Read-write mode select circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
DE69322725T 1992-09-30 1993-09-30 Halbleiterspeicheranordnung Expired - Fee Related DE69322725T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4262382A JP2812097B2 (ja) 1992-09-30 1992-09-30 半導体記憶装置

Publications (2)

Publication Number Publication Date
DE69322725D1 true DE69322725D1 (de) 1999-02-04
DE69322725T2 DE69322725T2 (de) 1999-05-06

Family

ID=17374981

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69322725T Expired - Fee Related DE69322725T2 (de) 1992-09-30 1993-09-30 Halbleiterspeicheranordnung

Country Status (5)

Country Link
US (2) US5500820A (de)
EP (1) EP0591850B1 (de)
JP (1) JP2812097B2 (de)
KR (1) KR970000882B1 (de)
DE (1) DE69322725T2 (de)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07334985A (ja) * 1994-06-08 1995-12-22 Mitsubishi Electric Corp 半導体記憶装置
KR100224768B1 (ko) * 1995-12-29 1999-10-15 김영환 외부 데이타의 입력없이 라이트 동작을 수행하는기능을 갖는 반도체 기억장치
JP3230435B2 (ja) * 1996-05-17 2001-11-19 日本電気株式会社 半導体記憶装置
JP3255017B2 (ja) * 1996-05-24 2002-02-12 日本電気株式会社 半導体記憶装置
JPH10162584A (ja) * 1996-12-02 1998-06-19 Mitsubishi Electric Corp 半導体記憶装置
JP3003613B2 (ja) * 1997-01-31 2000-01-31 日本電気株式会社 半導体記憶装置
JP3938808B2 (ja) 1997-12-26 2007-06-27 株式会社ルネサステクノロジ 半導体記憶装置
EP0995195A1 (de) * 1998-02-17 2000-04-26 Microchip Technology Inc. Integrierte überwachungsschaltung mit datenspeicherung und auffindefunktion von systemparametern
JPH11306758A (ja) * 1998-04-27 1999-11-05 Matsushita Electric Ind Co Ltd 半導体記憶装置
DE19828657C2 (de) * 1998-06-26 2001-01-04 Siemens Ag Integrierter Speicher
JP3953206B2 (ja) * 1998-09-24 2007-08-08 富士通株式会社 高速クロックに対応可能な入力バッファを持つ集積回路装置
JP2000132969A (ja) * 1998-10-28 2000-05-12 Nec Corp ダイナミックメモリ装置
JP2000163974A (ja) * 1998-11-30 2000-06-16 Nec Corp 半導体メモリ
JP4216415B2 (ja) * 1999-08-31 2009-01-28 株式会社ルネサステクノロジ 半導体装置
KR100415192B1 (ko) * 2001-04-18 2004-01-16 삼성전자주식회사 반도체 메모리 장치에서 읽기와 쓰기 방법 및 장치
JP3942074B2 (ja) * 2001-07-24 2007-07-11 インターナショナル・ビジネス・マシーンズ・コーポレーション データ入出力装置、メモリ・システム、データ入出力回路およびデータ入出力方法
DE10224742B4 (de) * 2002-06-04 2004-07-08 Infineon Technologies Ag Datenverarbeitungsschaltung und Verfahren zum Übertragen von Daten
US6879524B2 (en) * 2002-09-19 2005-04-12 Lsi Logic Corporation Memory I/O buffer using shared read/write circuitry
JP2005332499A (ja) * 2004-05-20 2005-12-02 Fujitsu Ltd 半導体記憶装置
KR100649351B1 (ko) * 2005-03-31 2006-11-27 주식회사 하이닉스반도체 저전압용 반도체 메모리 장치
JP2011146116A (ja) * 2010-01-18 2011-07-28 Elpida Memory Inc 半導体記憶装置及びその制御方法
US8724360B2 (en) * 2011-12-15 2014-05-13 Micron Technology, Inc. Wiring configuration of a bus system and power wires in a memory chip
WO2017192759A1 (en) * 2016-05-03 2017-11-09 Rambus Inc. Memory component with efficient write operations

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5570993A (en) * 1978-11-24 1980-05-28 Hitachi Ltd Memory circuit
US4791613A (en) * 1983-09-21 1988-12-13 Inmos Corporation Bit line and column circuitry used in a semiconductor memory
JPH0770222B2 (ja) * 1984-06-04 1995-07-31 株式会社日立製作所 Ｍｏｓスタテイツク型ｒａｍ
US4618785A (en) * 1984-09-06 1986-10-21 Thomson Components - Mostek Corporation CMOS sense amplifier with level shifter
EP0257912A3 (de) * 1986-08-29 1989-08-23 Kabushiki Kaisha Toshiba Statische Halbleiterspeicheranordnung
US4961168A (en) * 1987-02-24 1990-10-02 Texas Instruments Incorporated Bipolar-CMOS static random access memory device with bit line bias control
JPH01119982A (ja) * 1987-10-31 1989-05-12 Toshiba Corp スタティック型ランダムアクセスメモリ
US4954992A (en) * 1987-12-24 1990-09-04 Mitsubishi Denki Kabushiki Kaisha Random access memory having separate read out and write in bus lines for reduced access time and operating method therefor
US4866674A (en) * 1988-02-16 1989-09-12 Texas Instruments Incorporated Bitline pull-up circuit for a BiCMOS read/write memory
JP2575449B2 (ja) * 1988-02-18 1997-01-22 株式会社東芝 半導体メモリ装置
KR900003884A (ko) * 1988-08-12 1990-03-27 미다 가쓰시게 대규모 반도체 집적회로 장치
JPH0766945B2 (ja) * 1988-09-06 1995-07-19 株式会社東芝 スタティック型メモリ
US5048838A (en) * 1989-03-15 1991-09-17 Bridgestone Corporation Three-piece solid golf ball
JPH03252988A (ja) * 1990-03-02 1991-11-12 Nec Corp ダイナミック型半導体メモリ
US5115411A (en) * 1990-06-06 1992-05-19 Ncr Corporation Dual port memory system
US5043943A (en) * 1990-06-18 1991-08-27 Motorola, Inc. Cache memory with a parity write control circuit
JPH0589687A (ja) * 1991-09-27 1993-04-09 Nec Corp 不揮発性半導体記憶装置
US5268863A (en) * 1992-07-06 1993-12-07 Motorola, Inc. Memory having a write enable controlled word line
KR950014255B1 (ko) * 1992-12-31 1995-11-23 현대전자산업주식회사 고속동작을 위한 데이타 패스 구조를 갖는 반도체 메모리소자

Also Published As

Publication number Publication date
EP0591850A2 (de) 1994-04-13
DE69322725T2 (de) 1999-05-06
JPH06111575A (ja) 1994-04-22
KR970000882B1 (ko) 1997-01-20
US5500820A (en) 1996-03-19
EP0591850B1 (de) 1998-12-23
KR940007887A (ko) 1994-04-28
USRE36621E (en) 2000-03-21
JP2812097B2 (ja) 1998-10-15
EP0591850A3 (de) 1994-12-21

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NEC CORP., TOKIO/TOKYO, JP

Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP

8327 Change in the person/name/address of the patent owner

Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP

8339 Ceased/non-payment of the annual fee