KR940011024U - 반도체 메모리 장치 - Google Patents
반도체 메모리 장치Info
- Publication number
- KR940011024U KR940011024U KR2019920019241U KR920019241U KR940011024U KR 940011024 U KR940011024 U KR 940011024U KR 2019920019241 U KR2019920019241 U KR 2019920019241U KR 920019241 U KR920019241 U KR 920019241U KR 940011024 U KR940011024 U KR 940011024U
- Authority
- KR
- South Korea
- Prior art keywords
- memory device
- semiconductor memory
- semiconductor
- memory
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
- G11C5/146—Substrate bias generators
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR92019241U KR950006067Y1 (ko) | 1992-10-08 | 1992-10-08 | 반도체 메모리 장치 |
JP25153493A JP3761202B2 (ja) | 1992-10-08 | 1993-10-07 | 半導体メモリ装置のバックバイアス電圧発生回路 |
DE4334263A DE4334263B4 (de) | 1992-10-08 | 1993-10-07 | Generatorschaltung für eine negative Vorspannung für ein Halbleiterspeicherbauelement |
US08/134,040 US5434820A (en) | 1992-10-08 | 1993-10-08 | Back bias voltage generator circuit of a semiconductor memory device |
TW082108359A TW230815B (ko) | 1992-10-08 | 1993-10-08 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR92019241U KR950006067Y1 (ko) | 1992-10-08 | 1992-10-08 | 반도체 메모리 장치 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR940011024U true KR940011024U (ko) | 1994-05-27 |
KR950006067Y1 KR950006067Y1 (ko) | 1995-07-27 |
Family
ID=19341415
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR92019241U KR950006067Y1 (ko) | 1992-10-08 | 1992-10-08 | 반도체 메모리 장치 |
Country Status (5)
Country | Link |
---|---|
US (1) | US5434820A (ko) |
JP (1) | JP3761202B2 (ko) |
KR (1) | KR950006067Y1 (ko) |
DE (1) | DE4334263B4 (ko) |
TW (1) | TW230815B (ko) |
Families Citing this family (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR0157334B1 (ko) * | 1993-11-17 | 1998-10-15 | 김광호 | 반도체 메모리 장치의 전압 승압회로 |
KR0137437B1 (ko) * | 1994-12-29 | 1998-06-01 | 김주용 | 챠지 펌프회로의 출력전압 조절회로 |
JP3497601B2 (ja) * | 1995-04-17 | 2004-02-16 | 松下電器産業株式会社 | 半導体集積回路 |
US6259310B1 (en) * | 1995-05-23 | 2001-07-10 | Texas Instruments Incorporated | Apparatus and method for a variable negative substrate bias generator |
US5612644A (en) * | 1995-08-31 | 1997-03-18 | Cirrus Logic Inc. | Circuits, systems and methods for controlling substrate bias in integrated circuits |
KR0179845B1 (ko) * | 1995-10-12 | 1999-04-15 | 문정환 | 메모리의 기판전압 공급제어회로 |
JP2830807B2 (ja) * | 1995-11-29 | 1998-12-02 | 日本電気株式会社 | 半導体メモリ装置 |
US5715199A (en) * | 1996-12-23 | 1998-02-03 | Hyundai Electronics Industries Co., Ltd. | Back bias voltage generating circuit |
US5907255A (en) * | 1997-03-25 | 1999-05-25 | Cypress Semiconductor | Dynamic voltage reference which compensates for process variations |
JPH10289574A (ja) * | 1997-04-10 | 1998-10-27 | Fujitsu Ltd | 電圧発生回路を有した半導体装置 |
KR100481824B1 (ko) * | 1997-05-07 | 2005-07-08 | 삼성전자주식회사 | 리플레쉬용발진회로를갖는반도체메모리장치 |
KR19990003770A (ko) * | 1997-06-26 | 1999-01-15 | 김영환 | 전압 제어 발진기 |
KR100319164B1 (ko) * | 1997-12-31 | 2002-04-22 | 박종섭 | 다중레벨검출에의한다중구동장치및그방법 |
US6628564B1 (en) | 1998-06-29 | 2003-09-30 | Fujitsu Limited | Semiconductor memory device capable of driving non-selected word lines to first and second potentials |
US6781439B2 (en) * | 1998-07-30 | 2004-08-24 | Kabushiki Kaisha Toshiba | Memory device pump circuit with two booster circuits |
KR100338548B1 (ko) * | 1999-07-28 | 2002-05-27 | 윤종용 | 반도체 메모리 장치의 부스팅 회로 |
US7336121B2 (en) * | 2001-05-04 | 2008-02-26 | Samsung Electronics Co., Ltd. | Negative voltage generator for a semiconductor memory device |
US20030197546A1 (en) * | 2001-07-09 | 2003-10-23 | Samsung Electronics Co., Ltd. | Negative voltage generator for a semiconductor memory device |
JP4834261B2 (ja) * | 2001-09-27 | 2011-12-14 | Okiセミコンダクタ株式会社 | 昇圧電源発生回路 |
US6891426B2 (en) * | 2001-10-19 | 2005-05-10 | Intel Corporation | Circuit for providing multiple voltage signals |
JP2010257528A (ja) * | 2009-04-24 | 2010-11-11 | Toshiba Corp | 半導体集積回路装置 |
JP6581765B2 (ja) * | 2013-10-02 | 2019-09-25 | 株式会社半導体エネルギー研究所 | ブートストラップ回路、およびブートストラップ回路を有する半導体装置 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6159688A (ja) * | 1984-08-31 | 1986-03-27 | Hitachi Ltd | 半導体集積回路装置 |
US4760560A (en) * | 1985-08-30 | 1988-07-26 | Kabushiki Kaisha Toshiba | Random access memory with resistance to crystal lattice memory errors |
US5022055A (en) * | 1988-04-28 | 1991-06-04 | Amaf Industries, Inc. | Trunk dialing converter |
JPH0724298B2 (ja) * | 1988-08-10 | 1995-03-15 | 日本電気株式会社 | 半導体記憶装置 |
JP2645142B2 (ja) * | 1989-06-19 | 1997-08-25 | 株式会社東芝 | ダイナミック型ランダムアクセスメモリ |
-
1992
- 1992-10-08 KR KR92019241U patent/KR950006067Y1/ko not_active IP Right Cessation
-
1993
- 1993-10-07 DE DE4334263A patent/DE4334263B4/de not_active Expired - Fee Related
- 1993-10-07 JP JP25153493A patent/JP3761202B2/ja not_active Expired - Lifetime
- 1993-10-08 TW TW082108359A patent/TW230815B/zh not_active IP Right Cessation
- 1993-10-08 US US08/134,040 patent/US5434820A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
DE4334263B4 (de) | 2004-07-29 |
TW230815B (ko) | 1994-09-21 |
KR950006067Y1 (ko) | 1995-07-27 |
JPH06215568A (ja) | 1994-08-05 |
US5434820A (en) | 1995-07-18 |
JP3761202B2 (ja) | 2006-03-29 |
DE4334263A1 (de) | 1994-04-14 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
E701 | Decision to grant or registration of patent right | ||
REGI | Registration of establishment | ||
FPAY | Annual fee payment |
Payment date: 20070622 Year of fee payment: 13 |
|
EXPY | Expiration of term |