DE69322436T2 - Halbleiterspeicheranordnung - Google Patents

Halbleiterspeicheranordnung

Info

Publication number
DE69322436T2
DE69322436T2 DE69322436T DE69322436T DE69322436T2 DE 69322436 T2 DE69322436 T2 DE 69322436T2 DE 69322436 T DE69322436 T DE 69322436T DE 69322436 T DE69322436 T DE 69322436T DE 69322436 T2 DE69322436 T2 DE 69322436T2
Authority
DE
Germany
Prior art keywords
memory device
semiconductor memory
semiconductor
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69322436T
Other languages
English (en)
Other versions
DE69322436D1 (de
Inventor
Satoru Takase
Tohru Furuyama
Donald C Stark
Natsuki Kushiyama
Kiyofumi Sakurai
Hiroyuki Noji
Shigeo Ohshima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Toshiba Electronic Device Solutions Corp
Original Assignee
Toshiba Corp
Toshiba Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Toshiba Microelectronics Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE69322436D1 publication Critical patent/DE69322436D1/de
Publication of DE69322436T2 publication Critical patent/DE69322436T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
    • G11C7/1021—Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
DE69322436T 1992-05-22 1993-05-21 Halbleiterspeicheranordnung Expired - Lifetime DE69322436T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4131095A JP2892216B2 (ja) 1992-05-22 1992-05-22 半導体メモリ

Publications (2)

Publication Number Publication Date
DE69322436D1 DE69322436D1 (de) 1999-01-21
DE69322436T2 true DE69322436T2 (de) 1999-05-27

Family

ID=15049864

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69322436T Expired - Lifetime DE69322436T2 (de) 1992-05-22 1993-05-21 Halbleiterspeicheranordnung

Country Status (6)

Country Link
US (1) US5410512A (de)
EP (1) EP0570977B1 (de)
JP (1) JP2892216B2 (de)
KR (1) KR0136744B1 (de)
DE (1) DE69322436T2 (de)
TW (1) TW223707B (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IL96808A (en) * 1990-04-18 1996-03-31 Rambus Inc Introductory / Origin Circuit Agreed Using High-Performance Brokerage
US5896404A (en) * 1997-04-04 1999-04-20 International Business Machines Corporation Programmable burst length DRAM
JP3481868B2 (ja) * 1998-10-01 2003-12-22 株式会社日立製作所 データ伝送回路及び液晶表示装置
JP4270707B2 (ja) * 1999-04-09 2009-06-03 株式会社東芝 ダイナミック型半導体記憶装置
US6404694B2 (en) 1999-08-16 2002-06-11 Hitachi, Ltd. Semiconductor memory device with address comparing functions
JP3705113B2 (ja) 2000-10-27 2005-10-12 セイコーエプソン株式会社 半導体メモリ装置内のワード線の活性化
US6735546B2 (en) 2001-08-31 2004-05-11 Matrix Semiconductor, Inc. Memory device and method for temperature-based control over write and/or read operations
US6724665B2 (en) * 2001-08-31 2004-04-20 Matrix Semiconductor, Inc. Memory device and method for selectable sub-array activation
US6954394B2 (en) * 2002-11-27 2005-10-11 Matrix Semiconductor, Inc. Integrated circuit and method for selecting a set of memory-cell-layer-dependent or temperature-dependent operating conditions
US7057958B2 (en) * 2003-09-30 2006-06-06 Sandisk Corporation Method and system for temperature compensation for memory cells with temperature-dependent behavior
US7218570B2 (en) * 2004-12-17 2007-05-15 Sandisk 3D Llc Apparatus and method for memory operations using address-dependent conditions
US7283414B1 (en) 2006-05-24 2007-10-16 Sandisk 3D Llc Method for improving the precision of a temperature-sensor circuit
TWI828229B (zh) * 2022-07-13 2024-01-01 港香蘭藥廠股份有限公司 麻黃中麻黃生物鹼的改良型核磁共振氫譜（１ｈ-ｎｍｒ）定量方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4701885A (en) * 1984-07-26 1987-10-20 Texas Instruments Incorporated Dynamic memory array with quasi-folded bit lines
US5257235A (en) * 1989-04-25 1993-10-26 Kabushiki Kaisha Toshiba Semiconductor memory device having serial access mode
JPH0330183A (ja) * 1989-06-28 1991-02-08 Nec Corp メモリ制御方式
US5121354A (en) * 1990-03-12 1992-06-09 International Business Machines Corp. Random access memory with access on bit boundaries
DE69121366T2 (de) * 1990-11-30 1997-01-23 Toshiba Kawasaki Kk Halbleiterspeicheranordnung
JP2601951B2 (ja) * 1991-01-11 1997-04-23 株式会社東芝 半導体集積回路
JPH05274879A (ja) * 1992-03-26 1993-10-22 Nec Corp 半導体装置

Also Published As

Publication number Publication date
EP0570977A3 (de) 1995-03-22
EP0570977B1 (de) 1998-12-09
TW223707B (de) 1994-05-11
KR0136744B1 (ko) 1998-04-29
US5410512A (en) 1995-04-25
DE69322436D1 (de) 1999-01-21
EP0570977A2 (de) 1993-11-24
JP2892216B2 (ja) 1999-05-17
KR930024167A (ko) 1993-12-22
JPH05325544A (ja) 1993-12-10

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition