DE69227792D1 - Halbleiter-Speicheranordnung - Google Patents

Halbleiter-Speicheranordnung

Info

Publication number
DE69227792D1
DE69227792D1 DE69227792T DE69227792T DE69227792D1 DE 69227792 D1 DE69227792 D1 DE 69227792D1 DE 69227792 T DE69227792 T DE 69227792T DE 69227792 T DE69227792 T DE 69227792T DE 69227792 D1 DE69227792 D1 DE 69227792D1
Authority
DE
Germany
Prior art keywords
memory device
semiconductor memory
semiconductor
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69227792T
Other languages
English (en)
Other versions
DE69227792T2 (de
Inventor
Masao Taguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Semiconductor Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE69227792D1 publication Critical patent/DE69227792D1/de
Publication of DE69227792T2 publication Critical patent/DE69227792T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/02—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Databases & Information Systems (AREA)
  • Dram (AREA)
  • Semiconductor Memories (AREA)
  • Static Random-Access Memory (AREA)
DE69227792T 1991-03-13 1992-03-12 Halbleiter-Speicheranordnung Expired - Fee Related DE69227792T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4798191A JP2876799B2 (ja) 1991-03-13 1991-03-13 半導体記憶装置

Publications (2)

Publication Number Publication Date
DE69227792D1 true DE69227792D1 (de) 1999-01-21
DE69227792T2 DE69227792T2 (de) 1999-04-29

Family

ID=12790495

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69227792T Expired - Fee Related DE69227792T2 (de) 1991-03-13 1992-03-12 Halbleiter-Speicheranordnung

Country Status (5)

Country Link
US (1) US5251175A (de)
EP (1) EP0505091B1 (de)
JP (1) JP2876799B2 (de)
KR (1) KR950014245B1 (de)
DE (1) DE69227792T2 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5416743A (en) * 1993-12-10 1995-05-16 Mosaid Technologies Incorporated Databus architecture for accelerated column access in RAM
US7064376B2 (en) 1996-05-24 2006-06-20 Jeng-Jye Shau High performance embedded semiconductor memory devices with multiple dimension first-level bit-lines
US20050036363A1 (en) * 1996-05-24 2005-02-17 Jeng-Jye Shau High performance embedded semiconductor memory devices with multiple dimension first-level bit-lines
US5748547A (en) * 1996-05-24 1998-05-05 Shau; Jeng-Jye High performance semiconductor memory devices having multiple dimension bit lines

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0323876B1 (de) * 1983-09-21 1992-11-11 THORN EMI North America Inc. Bitzeilenlast und Spaltenschaltung für einen Halbleiterspeicher
US4791613A (en) * 1983-09-21 1988-12-13 Inmos Corporation Bit line and column circuitry used in a semiconductor memory
JPS60211693A (ja) * 1984-04-06 1985-10-24 Hitachi Ltd Ｍｏｓ増幅回路
JPH0713857B2 (ja) * 1988-06-27 1995-02-15 三菱電機株式会社 半導体記憶装置
JPH02146180A (ja) * 1988-11-28 1990-06-05 Nec Corp 半導体メモリ装置

Also Published As

Publication number Publication date
DE69227792T2 (de) 1999-04-29
JPH04283495A (ja) 1992-10-08
JP2876799B2 (ja) 1999-03-31
KR950014245B1 (ko) 1995-11-23
KR920018761A (ko) 1992-10-22
EP0505091A1 (de) 1992-09-23
US5251175A (en) 1993-10-05
EP0505091B1 (de) 1998-12-09

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: FUJITSU MICROELECTRONICS LTD., TOKYO, JP

8339 Ceased/non-payment of the annual fee