DE69423996T2 - Halbleiterspeicheranordnung - Google Patents

Halbleiterspeicheranordnung

Info

Publication number
DE69423996T2
DE69423996T2 DE69423996T DE69423996T DE69423996T2 DE 69423996 T2 DE69423996 T2 DE 69423996T2 DE 69423996 T DE69423996 T DE 69423996T DE 69423996 T DE69423996 T DE 69423996T DE 69423996 T2 DE69423996 T2 DE 69423996T2
Authority
DE
Germany
Prior art keywords
memory device
semiconductor memory
semiconductor
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69423996T
Other languages
English (en)
Other versions
DE69423996D1 (de
Inventor
Toshiya Uchida
Masao Taguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Semiconductor Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of DE69423996D1 publication Critical patent/DE69423996D1/de
Application granted granted Critical
Publication of DE69423996T2 publication Critical patent/DE69423996T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
DE69423996T 1993-04-28 1994-03-01 Halbleiterspeicheranordnung Expired - Lifetime DE69423996T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10328893A JP3253745B2 (ja) 1993-04-28 1993-04-28 半導体記憶装置

Publications (2)

Publication Number Publication Date
DE69423996D1 DE69423996D1 (de) 2000-05-25
DE69423996T2 true DE69423996T2 (de) 2001-01-04

Family

ID=14350126

Family Applications (2)

Application Number Title Priority Date Filing Date
DE69432764T Expired - Lifetime DE69432764T2 (de) 1993-04-28 1994-03-01 Halbleiterspeichereinrichtung
DE69423996T Expired - Lifetime DE69423996T2 (de) 1993-04-28 1994-03-01 Halbleiterspeicheranordnung

Family Applications Before (1)

Application Number Title Priority Date Filing Date
DE69432764T Expired - Lifetime DE69432764T2 (de) 1993-04-28 1994-03-01 Halbleiterspeichereinrichtung

Country Status (5)

Country Link
US (1) US5544109A (de)
EP (2) EP0622800B1 (de)
JP (1) JP3253745B2 (de)
KR (1) KR100213426B1 (de)
DE (2) DE69432764T2 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2825291B2 (ja) * 1989-11-13 1998-11-18 株式会社東芝 半導体記憶装置
DE19548053A1 (de) * 1995-12-21 1997-07-03 Siemens Ag Verfahren zum Betrieb einer SRAM MOS-Transistor Speicherzelle
US7157940B1 (en) * 2001-06-25 2007-01-02 Inapac Technology, Inc System and methods for a high-speed dynamic data bus
KR100425474B1 (ko) * 2001-11-21 2004-03-30 삼성전자주식회사 감소된 프리차지 레벨을 적용하는 데이터 출력방법과데이터 출력회로
JP4783002B2 (ja) * 2004-11-10 2011-09-28 株式会社東芝 半導体メモリ素子
JP4756581B2 (ja) * 2005-07-21 2011-08-24 ルネサスエレクトロニクス株式会社 半導体記憶装置

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4053873A (en) * 1976-06-30 1977-10-11 International Business Machines Corporation Self-isolating cross-coupled sense amplifier latch circuit
US4458336A (en) * 1980-10-22 1984-07-03 Fujitsu Limited Semiconductor memory circuit
US4665507A (en) * 1984-04-20 1987-05-12 Hitachi, Ltd. Semiconductor memory having load devices controlled by a write signal
US4780850A (en) * 1986-10-31 1988-10-25 Mitsubishi Denki Kabushiki Kaisha CMOS dynamic random access memory
US5042013A (en) * 1987-05-27 1991-08-20 Hitachi, Ltd. Semiconductor memory
GB9007788D0 (en) * 1990-04-06 1990-06-06 Foss Richard C Dynamic memory bitline precharge scheme
GB9007787D0 (en) * 1990-04-06 1990-06-06 Foss Richard C High-speed,small-swing datapath for dram
JPH07122989B2 (ja) * 1990-06-27 1995-12-25 株式会社東芝 半導体記憶装置
US5291450A (en) * 1990-11-28 1994-03-01 Matsushita Electric Industrial Co., Ltd. Read circuit of dynamic random access memory
JP2664810B2 (ja) * 1991-03-07 1997-10-22 株式会社東芝 メモリセルアレイ分割型半導体記憶装置
JP2745251B2 (ja) * 1991-06-12 1998-04-28 三菱電機株式会社 半導体メモリ装置

Also Published As

Publication number Publication date
DE69423996D1 (de) 2000-05-25
JPH06309874A (ja) 1994-11-04
US5544109A (en) 1996-08-06
EP0622800A3 (de) 1995-09-20
KR100213426B1 (ko) 1999-08-02
EP0933779A3 (de) 2000-03-22
EP0933779B1 (de) 2003-05-28
DE69432764T2 (de) 2004-02-05
EP0622800A2 (de) 1994-11-02
DE69432764D1 (de) 2003-07-03
JP3253745B2 (ja) 2002-02-04
EP0622800B1 (de) 2000-04-19
EP0933779A2 (de) 1999-08-04

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: FUJITSU MICROELECTRONICS LTD., TOKYO, JP

8327 Change in the person/name/address of the patent owner

Owner name: FUJITSU SEMICONDUCTOR LTD., YOKOHAMA, KANAGAWA, JP

8328 Change in the person/name/address of the agent

Representative=s name: SEEGER SEEGER LINDNER PARTNERSCHAFT PATENTANWAELTE