DE69823753D1 - Synchrone Halbleiterspeicheranordnung - Google Patents
Synchrone HalbleiterspeicheranordnungInfo
- Publication number
- DE69823753D1 DE69823753D1 DE69823753T DE69823753T DE69823753D1 DE 69823753 D1 DE69823753 D1 DE 69823753D1 DE 69823753 T DE69823753 T DE 69823753T DE 69823753 T DE69823753 T DE 69823753T DE 69823753 D1 DE69823753 D1 DE 69823753D1
- Authority
- DE
- Germany
- Prior art keywords
- memory device
- semiconductor memory
- synchronous semiconductor
- synchronous
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Tests Of Electronic Circuits (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18780697 | 1997-06-27 | ||
JP18780697A JP3189745B2 (ja) | 1997-06-27 | 1997-06-27 | 同期式半導体記憶装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69823753D1 true DE69823753D1 (de) | 2004-06-17 |
DE69823753T2 DE69823753T2 (de) | 2005-03-31 |
Family
ID=16212577
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69823753T Expired - Lifetime DE69823753T2 (de) | 1997-06-27 | 1998-06-29 | Synchrone Halbleiter-Speichervorrichtung |
Country Status (5)
Country | Link |
---|---|
US (1) | US6055209A (de) |
EP (1) | EP0895245B1 (de) |
JP (1) | JP3189745B2 (de) |
KR (1) | KR100304336B1 (de) |
DE (1) | DE69823753T2 (de) |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7751370B2 (en) * | 2001-07-13 | 2010-07-06 | Qualcomm Incorporated | Method and apparatus for forward link rate scheduling |
KR100532388B1 (ko) * | 1998-08-04 | 2006-01-27 | 삼성전자주식회사 | 직렬 출력 비교기를 갖는 메모리 집적회로 |
US6341093B1 (en) * | 2000-06-07 | 2002-01-22 | International Business Machines Corporation | SOI array sense and write margin qualification |
JP4712183B2 (ja) * | 2000-11-30 | 2011-06-29 | 富士通セミコンダクター株式会社 | 同期型半導体装置、及び試験システム |
WO2002056043A1 (fr) * | 2001-01-12 | 2002-07-18 | Advantest Corporation | Appareil de test pour dispositif a semi-conducteur et procede mettant en oeuvre ledit appareil |
KR100401506B1 (ko) * | 2001-05-10 | 2003-10-17 | 주식회사 하이닉스반도체 | 비동기 프리차지 기능을 갖는 싱크로노스 메모리 디바이스 |
JP2002343081A (ja) * | 2001-05-18 | 2002-11-29 | Mitsubishi Electric Corp | 半導体記憶装置 |
KR100400311B1 (ko) | 2001-06-29 | 2003-10-01 | 주식회사 하이닉스반도체 | 반도체 메모리 소자의 신호 지연 제어 장치 |
DE10149192B4 (de) * | 2001-10-05 | 2005-07-14 | Infineon Technologies Ag | Vorrichtung zum Erzeugen von Speicher-internen Befehlssignalen aus einem Speicheroperationsbefehl |
KR100414734B1 (ko) * | 2001-12-21 | 2004-01-13 | 주식회사 하이닉스반도체 | 반도체 메모리 장치 |
KR100442965B1 (ko) * | 2001-12-29 | 2004-08-04 | 주식회사 하이닉스반도체 | 반도체 메모리장치의 내부 프리차지 펄스신호 발생회로 |
US6920524B2 (en) | 2003-02-03 | 2005-07-19 | Micron Technology, Inc. | Detection circuit for mixed asynchronous and synchronous memory operation |
KR100620645B1 (ko) | 2004-04-13 | 2006-09-13 | 주식회사 하이닉스반도체 | 동기 및 비동기 병용 모드 레지스터 세트를 포함하는psram |
KR100809690B1 (ko) | 2006-07-14 | 2008-03-07 | 삼성전자주식회사 | 저속 테스트 동작이 가능한 반도체 메모리 장치 및 반도체메모리 장치의 테스트 방법 |
JP2010182359A (ja) | 2009-02-04 | 2010-08-19 | Elpida Memory Inc | 半導体記憶装置及びそのテスト方法 |
JP2012203970A (ja) * | 2011-03-28 | 2012-10-22 | Elpida Memory Inc | 半導体装置及び半導体装置の制御方法 |
KR20160003818U (ko) | 2015-04-27 | 2016-11-04 | (주)오성마이더스 | 드럼통 거치대 |
FR3050150B1 (fr) * | 2016-04-18 | 2018-04-06 | Reydel Automotive B.V. | Dispositif de bouton rotatif de commande et aerateur comportant un tel dispositif |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5442642A (en) * | 1992-12-11 | 1995-08-15 | Micron Semiconductor, Inc. | Test signal generator on substrate to test |
JP3591887B2 (ja) * | 1994-09-12 | 2004-11-24 | 富士通株式会社 | 半導体記憶装置 |
US5598376A (en) * | 1994-12-23 | 1997-01-28 | Micron Technology, Inc. | Distributed write data drivers for burst access memories |
JPH1011966A (ja) * | 1996-06-27 | 1998-01-16 | Mitsubishi Electric Corp | 同期型半導体記憶装置および同期型メモリモジュール |
US5784332A (en) * | 1996-12-12 | 1998-07-21 | Micron Technology Corporation | Clock frequency detector for a synchronous memory device |
US5764592A (en) * | 1996-12-21 | 1998-06-09 | Sgs-Thomson Microelectronics, Inc. | External write pulse control method and structure |
-
1997
- 1997-06-27 JP JP18780697A patent/JP3189745B2/ja not_active Expired - Fee Related
-
1998
- 1998-06-27 KR KR1019980024496A patent/KR100304336B1/ko not_active IP Right Cessation
- 1998-06-29 US US09/106,101 patent/US6055209A/en not_active Expired - Lifetime
- 1998-06-29 DE DE69823753T patent/DE69823753T2/de not_active Expired - Lifetime
- 1998-06-29 EP EP98111986A patent/EP0895245B1/de not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP0895245A2 (de) | 1999-02-03 |
KR19990007406A (ko) | 1999-01-25 |
EP0895245A3 (de) | 1999-11-17 |
KR100304336B1 (ko) | 2001-11-22 |
DE69823753T2 (de) | 2005-03-31 |
JP3189745B2 (ja) | 2001-07-16 |
EP0895245B1 (de) | 2004-05-12 |
JPH1125695A (ja) | 1999-01-29 |
US6055209A (en) | 2000-04-25 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8327 | Change in the person/name/address of the patent owner |
Owner name: ELPIDA MEMORY, INC., TOKIO/TOKYO, JP |
|
8364 | No opposition during term of opposition |