DE69834540D1 - Halbleiterspeicher - Google Patents

Halbleiterspeicher

Info

Publication number
DE69834540D1
DE69834540D1 DE69834540T DE69834540T DE69834540D1 DE 69834540 D1 DE69834540 D1 DE 69834540D1 DE 69834540 T DE69834540 T DE 69834540T DE 69834540 T DE69834540 T DE 69834540T DE 69834540 D1 DE69834540 D1 DE 69834540D1
Authority
DE
Germany
Prior art keywords
semiconductor memory
semiconductor
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69834540T
Other languages
English (en)
Other versions
DE69834540T2 (de
Inventor
Gerhard Mueller
Toshiaki Kirihata
Hing Wong
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qimonda AG
International Business Machines Corp
Original Assignee
Infineon Technologies AG
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG, International Business Machines Corp filed Critical Infineon Technologies AG
Publication of DE69834540D1 publication Critical patent/DE69834540D1/de
Application granted granted Critical
Publication of DE69834540T2 publication Critical patent/DE69834540T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
  • Static Random-Access Memory (AREA)
DE69834540T 1997-12-18 1998-12-18 Halbleiterspeicher Expired - Lifetime DE69834540T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/993,538 US6069815A (en) 1997-12-18 1997-12-18 Semiconductor memory having hierarchical bit line and/or word line architecture
US993538 1997-12-18

Publications (2)

Publication Number Publication Date
DE69834540D1 true DE69834540D1 (de) 2006-06-22
DE69834540T2 DE69834540T2 (de) 2007-05-03

Family

ID=25539655

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69834540T Expired - Lifetime DE69834540T2 (de) 1997-12-18 1998-12-18 Halbleiterspeicher

Country Status (7)

Country Link
US (1) US6069815A (de)
EP (1) EP0926683B1 (de)
JP (1) JPH11283365A (de)
KR (1) KR19990063189A (de)
CN (1) CN1220466A (de)
DE (1) DE69834540T2 (de)
TW (1) TW419668B (de)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6333866B1 (en) * 1998-09-28 2001-12-25 Texas Instruments Incorporated Semiconductor device array having dense memory cell array and heirarchical bit line scheme
US6404664B1 (en) * 1998-09-29 2002-06-11 Texas Instruments Incorporated Twisted bit line structure and method for making same
DE19907176A1 (de) * 1999-02-19 2000-08-31 Siemens Ag Decoder-Anschlußanordnung für Speicherchips mit langen Bitleitungen
US6370055B1 (en) 2001-02-28 2002-04-09 Infineon Technologies Ag Semiconductor memory having asymmetric column addressing and twisted read write drive (RWD) line architecture
CA2340985A1 (en) * 2001-03-14 2002-09-14 Atmos Corporation Interleaved wordline architecture
US6519174B2 (en) * 2001-05-16 2003-02-11 International Business Machines Corporation Early write DRAM architecture with vertically folded bitlines
US6385083B1 (en) * 2001-08-01 2002-05-07 Hewlett-Packard Company MRAM device including offset conductors
US6567329B2 (en) 2001-08-28 2003-05-20 Intel Corporation Multiple word-line accessing and accessor
US7042749B2 (en) * 2002-05-16 2006-05-09 Micron Technology, Inc. Stacked 1T-nmemory cell structure
DE10255834A1 (de) * 2002-11-29 2004-06-17 Infineon Technologies Ag Integrierter Halbleiterspeicher
US6657880B1 (en) 2002-12-04 2003-12-02 Virtual Silicon Technology, Inc. SRAM bit line architecture
KR100541818B1 (ko) * 2003-12-18 2006-01-10 삼성전자주식회사 반도체 메모리 장치의 라인 배치구조
JP2006128471A (ja) * 2004-10-29 2006-05-18 Toshiba Corp 半導体メモリ
KR100621769B1 (ko) * 2004-11-18 2006-09-19 삼성전자주식회사 반도체 메모리 장치에서의 비트라인 배치구조
KR100621774B1 (ko) * 2005-04-08 2006-09-15 삼성전자주식회사 반도체 메모리 장치에서의 레이아웃구조 및 그에 따른레이아웃 방법
US7688612B2 (en) * 2007-04-13 2010-03-30 Aplus Flash Technology, Inc. Bit line structure for a multilevel, dual-sided nonvolatile memory cell array
KR100945796B1 (ko) * 2008-05-08 2010-03-08 주식회사 하이닉스반도체 반도체 집적 회로
JP2011040706A (ja) * 2009-07-15 2011-02-24 Toshiba Corp 不揮発性半導体記憶装置
KR101562429B1 (ko) * 2009-09-01 2015-10-21 램버스 인코포레이티드 계층적 비트라인을 갖는 반도체 메모리 디바이스
JP2011181131A (ja) 2010-02-26 2011-09-15 Toshiba Corp 半導体記憶装置
CN103985407A (zh) * 2013-02-07 2014-08-13 辉达公司 采用分段式页面配置的dram
US20140219007A1 (en) 2013-02-07 2014-08-07 Nvidia Corporation Dram with segmented page configuration
US9165623B2 (en) * 2013-10-13 2015-10-20 Taiwan Semiconductor Manufacturing Company Limited Memory arrangement
KR20150113400A (ko) * 2014-03-28 2015-10-08 에스케이하이닉스 주식회사 계층적 비트라인 구조를 갖는 저항성 메모리 장치
US9704575B1 (en) 2016-01-07 2017-07-11 Globalfoundries Inc. Content-addressable memory having multiple reference matchlines to reduce latency

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4980860A (en) * 1986-06-27 1990-12-25 Texas Instruments Incorporated Cross-coupled complementary bit lines for a semiconductor memory with pull-up circuitry
US5214601A (en) * 1986-12-11 1993-05-25 Mitsubishi Denki Kabushiki Kaisha Bit line structure for semiconductor memory device including cross-points and multiple interconnect layers
JPH0766666B2 (ja) * 1988-08-29 1995-07-19 三菱電機株式会社 半導体記憶装置
US5136543A (en) * 1989-05-12 1992-08-04 Mitsubishi Denki Kabushiki Kaisha Data descrambling in semiconductor memory device
JPH02302986A (ja) * 1989-05-16 1990-12-14 Mitsubishi Electric Corp ダイナミック型半導体記憶装置
JPH03278573A (ja) * 1990-03-28 1991-12-10 Mitsubishi Electric Corp 半導体記憶装置
US5107459A (en) * 1990-04-20 1992-04-21 International Business Machines Corporation Stacked bit-line architecture for high density cross-point memory cell array
JP3672946B2 (ja) * 1993-11-30 2005-07-20 株式会社ルネサステクノロジ 半導体記憶装置
JP3364549B2 (ja) * 1995-02-22 2003-01-08 三菱電機株式会社 半導体記憶装置
JP3411129B2 (ja) * 1995-07-03 2003-05-26 沖電気工業株式会社 半導体メモリ
AU1757797A (en) * 1996-02-01 1997-08-22 Micron Technology, Inc. Digit line architecture for dynamic memory

Also Published As

Publication number Publication date
EP0926683A3 (de) 2000-03-15
JPH11283365A (ja) 1999-10-15
US6069815A (en) 2000-05-30
EP0926683A2 (de) 1999-06-30
KR19990063189A (ko) 1999-07-26
CN1220466A (zh) 1999-06-23
DE69834540T2 (de) 2007-05-03
TW419668B (en) 2001-01-21
EP0926683B1 (de) 2006-05-17

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: INTERNATIONAL BUSINESS MACHINES CORP., ARMONK,, US

Owner name: QIMONDA AG, 81739 MUENCHEN, DE