DE69225198T2 - Verfahren zur Herstellung einer Halbleiterspeicheranordnung, die ein schwebendes Gate mit verbesserter Isolierschicht enthält - Google Patents

Verfahren zur Herstellung einer Halbleiterspeicheranordnung, die ein schwebendes Gate mit verbesserter Isolierschicht enthält

Info

Publication number
DE69225198T2
DE69225198T2 DE69225198T DE69225198T DE69225198T2 DE 69225198 T2 DE69225198 T2 DE 69225198T2 DE 69225198 T DE69225198 T DE 69225198T DE 69225198 T DE69225198 T DE 69225198T DE 69225198 T2 DE69225198 T2 DE 69225198T2
Authority
DE
Germany
Prior art keywords
manufacturing
insulating layer
memory device
semiconductor memory
floating gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69225198T
Other languages
English (en)
Other versions
DE69225198D1 (de
Inventor
Tatsuya Kajita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of DE69225198D1 publication Critical patent/DE69225198D1/de
Application granted granted Critical
Publication of DE69225198T2 publication Critical patent/DE69225198T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
    • H10B41/48—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with a tunnel dielectric layer also being used as part of the peripheral transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/49—Simultaneous manufacture of periphery and memory cells comprising different types of peripheral transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
DE69225198T 1991-11-14 1992-11-13 Verfahren zur Herstellung einer Halbleiterspeicheranordnung, die ein schwebendes Gate mit verbesserter Isolierschicht enthält Expired - Fee Related DE69225198T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP29928191A JP3548984B2 (ja) 1991-11-14 1991-11-14 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
DE69225198D1 DE69225198D1 (de) 1998-05-28
DE69225198T2 true DE69225198T2 (de) 1998-08-13

Family

ID=17870516

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69225198T Expired - Fee Related DE69225198T2 (de) 1991-11-14 1992-11-13 Verfahren zur Herstellung einer Halbleiterspeicheranordnung, die ein schwebendes Gate mit verbesserter Isolierschicht enthält

Country Status (5)

Country Link
US (2) US5449629A (de)
EP (1) EP0542575B1 (de)
JP (1) JP3548984B2 (de)
KR (1) KR100189092B1 (de)
DE (1) DE69225198T2 (de)

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DE69313816T2 (de) * 1993-02-11 1998-03-26 St Microelectronics Srl EEPROM-Zelle und peripherer MOS-Transistor
KR0124629B1 (ko) * 1994-02-23 1997-12-11 문정환 불휘발성 반도체 메모리장치의 제조방법
JP3675500B2 (ja) * 1994-09-02 2005-07-27 株式会社東芝 不揮発性半導体記憶装置
US5478767A (en) * 1994-09-30 1995-12-26 United Microelectronics Corporation Method of making a flash EEPROM memory cell comprising polysilicon and textured oxide sidewall spacers
KR100246162B1 (ko) * 1995-01-19 2000-03-15 로데릭 더블류 루이스 주변 회로 내의 트랜지스터 형성 방법
EP0751559B1 (de) 1995-06-30 2002-11-27 STMicroelectronics S.r.l. Herstellungsverfahren eines Schaltkreises, der nichtflüchtige Speicherzellen und Randtransistoren enthält, und entsprechender IC
US6787844B2 (en) * 1995-09-29 2004-09-07 Nippon Steel Corporation Semiconductor device including transistor with composite gate structure and transistor with single gate structure, and method for manufacturing the same
TW347567B (en) * 1996-03-22 1998-12-11 Philips Eloctronics N V Semiconductor device and method of manufacturing a semiconductor device
DE69631879D1 (de) * 1996-04-30 2004-04-22 St Microelectronics Srl Herstellungsverfahren für einen integrierten Dickoxydtransistor
US6330190B1 (en) 1996-05-30 2001-12-11 Hyundai Electronics America Semiconductor structure for flash memory enabling low operating potentials
US6043123A (en) * 1996-05-30 2000-03-28 Hyundai Electronics America, Inc. Triple well flash memory fabrication process
JP3107199B2 (ja) * 1996-08-29 2000-11-06 日本電気株式会社 不揮発性半導体記憶装置の製造方法
US6258669B1 (en) * 1997-12-18 2001-07-10 Advanced Micro Devices, Inc. Methods and arrangements for improved formation of control and floating gates in non-volatile memory semiconductor devices
US5998262A (en) * 1998-04-23 1999-12-07 Worldwide Semiconductor Manufacturing Corp. Method for manufacturing ETOX cell having damage-free source region
US6034395A (en) * 1998-06-05 2000-03-07 Advanced Micro Devices, Inc. Semiconductor device having a reduced height floating gate
JP3314807B2 (ja) * 1998-11-26 2002-08-19 日本電気株式会社 半導体装置の製造方法
KR100290787B1 (ko) * 1998-12-26 2001-07-12 박종섭 반도체 메모리 소자의 제조방법
JP2000311992A (ja) 1999-04-26 2000-11-07 Toshiba Corp 不揮発性半導体記憶装置およびその製造方法
JP2001035943A (ja) * 1999-07-23 2001-02-09 Mitsubishi Electric Corp 半導体装置および製造方法
EP1104022A1 (de) * 1999-11-29 2001-05-30 STMicroelectronics S.r.l. Herstellungsverfahren eines integrierten Schaltkreis der Hoch- und Niederspannungs-MOS-Transistoren sowie EPROM-Zellen beinhaltet
US6979619B1 (en) * 2000-06-15 2005-12-27 Advanced Micro Devices, Inc. Flash memory device and a method of fabrication thereof
US6743680B1 (en) 2000-06-22 2004-06-01 Advanced Micro Devices, Inc. Process for manufacturing transistors having silicon/germanium channel regions
TW461093B (en) * 2000-07-07 2001-10-21 United Microelectronics Corp Fabrication method for a high voltage electrical erasable programmable read only memory device
JP4003031B2 (ja) * 2000-09-04 2007-11-07 セイコーエプソン株式会社 半導体装置の製造方法
US7323422B2 (en) * 2002-03-05 2008-01-29 Asm International N.V. Dielectric layers and methods of forming the same
US6869835B2 (en) * 2002-09-11 2005-03-22 Samsung Electronics, Co., Ltd Method of forming MOS transistor
US8314024B2 (en) * 2008-12-19 2012-11-20 Unity Semiconductor Corporation Device fabrication
JP2005260253A (ja) * 2005-04-04 2005-09-22 Renesas Technology Corp 半導体集積回路装置およびその製造方法

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JPS56120166A (en) * 1980-02-27 1981-09-21 Hitachi Ltd Semiconductor ic device and manufacture thereof
JPS5974677A (ja) * 1982-10-22 1984-04-27 Ricoh Co Ltd 半導体装置及びその製造方法
JPS6150371A (ja) * 1984-08-20 1986-03-12 Toshiba Corp 半導体記憶装置及びその製造方法
JPS6362382A (ja) * 1986-09-03 1988-03-18 Nec Corp 浮遊ゲ−ト型不揮発性半導体記憶装置およびその製造方法
JPH088310B2 (ja) * 1987-03-18 1996-01-29 株式会社日立製作所 半導体集積回路装置の製造方法
JPS63255964A (ja) * 1987-04-14 1988-10-24 Toshiba Corp 半導体装置
JPS63255972A (ja) * 1987-04-14 1988-10-24 Toshiba Corp 半導体装置の製造方法
JP2664685B2 (ja) * 1987-07-31 1997-10-15 株式会社東芝 半導体装置の製造方法
JP2650925B2 (ja) * 1987-11-02 1997-09-10 株式会社日立製作所 半導体集積回路装置の製造方法
JP2617972B2 (ja) * 1988-02-26 1997-06-11 株式会社日立製作所 半導体集積回路装置の製造方法
JP2615876B2 (ja) * 1988-07-13 1997-06-04 三菱電機株式会社 半導体装置およびその製造方法
US5089433A (en) * 1988-08-08 1992-02-18 National Semiconductor Corporation Bipolar field-effect electrically erasable programmable read only memory cell and method of manufacture
FR2642900B1 (fr) * 1989-01-17 1991-05-10 Sgs Thomson Microelectronics Procede de fabrication de circuits integres a transistors de memoire eprom et a transistors logiques
US5081054A (en) * 1989-04-03 1992-01-14 Atmel Corporation Fabrication process for programmable and erasable MOS memory device
JP2820432B2 (ja) * 1989-05-23 1998-11-05 富士通株式会社 半導体装置の製造方法
US5066992A (en) * 1989-06-23 1991-11-19 Atmel Corporation Programmable and erasable MOS memory device
US5104819A (en) * 1989-08-07 1992-04-14 Intel Corporation Fabrication of interpoly dielctric for EPROM-related technologies
JP2509717B2 (ja) * 1989-12-06 1996-06-26 株式会社東芝 半導体装置の製造方法
US5225361A (en) * 1990-03-08 1993-07-06 Matshshita Electronics Coropration Non-volatile semiconductor memory device and a method for fabricating the same
US5188976A (en) * 1990-07-13 1993-02-23 Hitachi, Ltd. Manufacturing method of non-volatile semiconductor memory device
JP2913817B2 (ja) * 1990-10-30 1999-06-28 日本電気株式会社 半導体メモリの製造方法
KR940009644B1 (ko) * 1991-11-19 1994-10-15 삼성전자 주식회사 불휘발성 반도체메모리장치 및 그 제조방법

Also Published As

Publication number Publication date
EP0542575B1 (de) 1998-04-22
US5449629A (en) 1995-09-12
EP0542575A2 (de) 1993-05-19
DE69225198D1 (de) 1998-05-28
JPH05136424A (ja) 1993-06-01
EP0542575A3 (en) 1993-08-18
US5497018A (en) 1996-03-05
JP3548984B2 (ja) 2004-08-04
KR100189092B1 (ko) 1999-06-01

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee