DE60045636D1 - Verfahren zur behandlung eines halbleitersubstrats - Google Patents

Verfahren zur behandlung eines halbleitersubstrats

Info

Publication number
DE60045636D1
DE60045636D1 DE60045636T DE60045636T DE60045636D1 DE 60045636 D1 DE60045636 D1 DE 60045636D1 DE 60045636 T DE60045636 T DE 60045636T DE 60045636 T DE60045636 T DE 60045636T DE 60045636 D1 DE60045636 D1 DE 60045636D1
Authority
DE
Germany
Prior art keywords
treating
semiconductor substrate
semiconductor
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60045636T
Other languages
English (en)
Inventor
Thierry Barge
Bruno Ghyselen
Toshiaki Iwamatsu
Hideki Naruoka
Junichiro Furihata
Kiyoshi Mitani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec SA filed Critical Soitec SA
Application granted granted Critical
Publication of DE60045636D1 publication Critical patent/DE60045636D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/06—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials
    • H01L21/08—Preparation of the foundation plate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/12—All metal or with adjacent metals
    • Y10T428/12493—Composite; i.e., plural, adjacent, spatially distinct metal components [e.g., layers, joint, etc.]
    • Y10T428/12528—Semiconductor component

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Formation Of Insulating Films (AREA)
  • Weting (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
DE60045636T 1999-08-20 2000-08-17 Verfahren zur behandlung eines halbleitersubstrats Expired - Lifetime DE60045636D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR9910668A FR2797714B1 (fr) 1999-08-20 1999-08-20 Procede de traitement de substrats pour la microelectronique et substrats obtenus par ce procede
PCT/FR2000/002331 WO2001015218A1 (fr) 1999-08-20 2000-08-17 Procede de traitement de substrats pour la micro-electronique et substrats obtenus par ce procede

Publications (1)

Publication Number Publication Date
DE60045636D1 true DE60045636D1 (de) 2011-03-31

Family

ID=9549261

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60045636T Expired - Lifetime DE60045636D1 (de) 1999-08-20 2000-08-17 Verfahren zur behandlung eines halbleitersubstrats

Country Status (9)

Country Link
US (2) US6902988B2 (de)
EP (1) EP1208593B1 (de)
JP (1) JP4582982B2 (de)
KR (1) KR100752467B1 (de)
DE (1) DE60045636D1 (de)
FR (1) FR2797714B1 (de)
MY (1) MY125775A (de)
TW (1) TW530378B (de)
WO (1) WO2001015218A1 (de)

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FR2842648B1 (fr) * 2002-07-18 2005-01-14 Commissariat Energie Atomique Procede de transfert d'une couche mince electriquement active
US6908774B2 (en) 2002-08-12 2005-06-21 S.O. I. Tec Silicon On Insulator Technologies S.A. Method and apparatus for adjusting the thickness of a thin layer of semiconductor material
FR2843486B1 (fr) * 2002-08-12 2005-09-23 Soitec Silicon On Insulator Procede d'elaboration de couches minces de semi-conducteur comprenant une etape de finition
AU2003263391A1 (en) 2002-08-12 2004-02-25 S.O.I.Tec Silicon On Insulator Technologies A method of preparing a thin layer, the method including a step of correcting thickness by sacrificial oxidation, and an associated machine
FR2843487B1 (fr) * 2002-08-12 2005-10-14 Procede d'elaboration de couche mince comprenant une etape de correction d'epaisseur par oxydation sacrificielle, et machine associee
JP4382438B2 (ja) * 2002-11-14 2009-12-16 株式会社東芝 半導体ウェーハの検査方法、半導体装置の開発方法、半導体装置の製造方法、および半導体ウェーハ処理装置
FR2849269B1 (fr) * 2002-12-20 2005-07-29 Soitec Silicon On Insulator Procede de realisation de cavites dans une plaque de silicium
FR2852143B1 (fr) 2003-03-04 2005-10-14 Soitec Silicon On Insulator Procede de traitement preventif de la couronne d'une tranche multicouche
FR2855909B1 (fr) 2003-06-06 2005-08-26 Soitec Silicon On Insulator Procede d'obtention concomitante d'au moins une paire de structures comprenant au moins une couche utile reportee sur un substrat
DE10326578B4 (de) * 2003-06-12 2006-01-19 Siltronic Ag Verfahren zur Herstellung einer SOI-Scheibe
EP1571241A1 (de) 2004-03-01 2005-09-07 S.O.I.T.E.C. Silicon on Insulator Technologies Herstellungsverfahren eines Substrates
JP4407384B2 (ja) * 2004-05-28 2010-02-03 株式会社Ｓｕｍｃｏ Ｓｏｉ基板の製造方法
KR100914898B1 (ko) * 2004-12-28 2009-08-31 에스오아이테크 실리콘 온 인슐레이터 테크놀로지스 낮은 홀들의 밀도를 가지는 박막을 구현하는 방법
JP2008526010A (ja) * 2004-12-28 2008-07-17 エス． オー． アイ． テック シリコン オン インシュレーター テクノロジーズ 低いホール密度を有する薄層を得るための方法
FR2884647B1 (fr) * 2005-04-15 2008-02-22 Soitec Silicon On Insulator Traitement de plaques de semi-conducteurs
FR2893446B1 (fr) * 2005-11-16 2008-02-15 Soitec Silicon Insulator Techn TRAITEMENT DE COUCHE DE SiGe POUR GRAVURE SELECTIVE
FR2895563B1 (fr) * 2005-12-22 2008-04-04 Soitec Silicon On Insulator Procede de simplification d'une sequence de finition et structure obtenue par le procede
JP2008028070A (ja) * 2006-07-20 2008-02-07 Sumco Corp 貼り合わせウェーハの製造方法
CN101675280B (zh) * 2007-03-30 2013-05-15 盾安美斯泰克公司(美国) 先导式微型滑阀
CN101668973B (zh) * 2007-03-31 2013-03-13 盾安美斯泰克公司(美国) 先导式滑阀
EP2105957A3 (de) * 2008-03-26 2011-01-19 Semiconductor Energy Laboratory Co., Ltd. Verfahren zur Herstellung eines SOI-Substrats und Verfahren zur Herstellung einer Halbleitervorrichtung
FR2934925B1 (fr) * 2008-08-06 2011-02-25 Soitec Silicon On Insulator Procede de fabrication d'une structure comprernant une etape d'implantations d'ions pour stabiliser l'interface de collage.
CN102164846B (zh) * 2008-08-09 2016-03-30 盾安美斯泰克公司(美国) 改进的微型阀装置
EP2161741B1 (de) * 2008-09-03 2014-06-11 Soitec Verfahren zur Herstellung eines Halbleiters auf einem Isoliersubstrat mit verringerter SECCO-Fehlerdichte
US20100130021A1 (en) * 2008-11-26 2010-05-27 Memc Electronic Materials, Inc. Method for processing a silicon-on-insulator structure
CN102308131B (zh) 2008-12-06 2014-01-08 盾安美斯泰克有限公司 流体流动控制组件
FR2943458B1 (fr) * 2009-03-18 2011-06-10 Soitec Silicon On Insulator Procede de finition d'un substrat de type "silicium sur isolant" soi
WO2010117874A2 (en) 2009-04-05 2010-10-14 Microstaq, Inc. Method and structure for optimizing heat exchanger performance
US20120145252A1 (en) 2009-08-17 2012-06-14 Dunan Microstaq, Inc. Micromachined Device and Control Method
JP5522175B2 (ja) * 2009-09-04 2014-06-18 信越半導体株式会社 Ｓｏｉウェーハの製造方法
US9006844B2 (en) 2010-01-28 2015-04-14 Dunan Microstaq, Inc. Process and structure for high temperature selective fusion bonding
WO2011094302A2 (en) * 2010-01-28 2011-08-04 Microstaq, Inc. Process for reconditioning semiconductor surface to facilitate bonding
GB2499969A (en) 2010-06-25 2013-09-11 Cambridge Display Tech Ltd Composition comprising an organic semiconducting material and a triplet-accepting material
GB2495250A (en) 2010-06-25 2013-04-03 Cambridge Display Tech Ltd Organic light-emitting composition comprising anthranthene derivatives and device and method using the same
US8996141B1 (en) 2010-08-26 2015-03-31 Dunan Microstaq, Inc. Adaptive predictive functional controller
JP5927894B2 (ja) 2011-12-15 2016-06-01 信越半導体株式会社 Ｓｏｉウェーハの製造方法
US8925793B2 (en) 2012-01-05 2015-01-06 Dunan Microstaq, Inc. Method for making a solder joint
JP2013143407A (ja) * 2012-01-06 2013-07-22 Shin Etsu Handotai Co Ltd 貼り合わせｓｏｉウェーハの製造方法
FR2987166B1 (fr) 2012-02-16 2017-05-12 Soitec Silicon On Insulator Procede de transfert d'une couche
US9136134B2 (en) 2012-02-22 2015-09-15 Soitec Methods of providing thin layers of crystalline semiconductor material, and related structures and devices
US9140613B2 (en) 2012-03-16 2015-09-22 Zhejiang Dunan Hetian Metal Co., Ltd. Superheat sensor
JP5096634B2 (ja) * 2012-06-14 2012-12-12 ソイテック 低いホール密度を有する薄層を得るための方法
FR3007891B1 (fr) * 2013-06-28 2016-11-25 Soitec Silicon On Insulator Procede de fabrication d'une structure composite
US9188375B2 (en) 2013-12-04 2015-11-17 Zhejiang Dunan Hetian Metal Co., Ltd. Control element and check valve assembly
JP2016082093A (ja) * 2014-10-17 2016-05-16 信越半導体株式会社 貼り合わせウェーハの製造方法
JP6601119B2 (ja) * 2015-10-05 2019-11-06 株式会社Ｓｕｍｃｏ エピタキシャルウェーハ裏面検査装置およびそれを用いたエピタキシャルウェーハ裏面検査方法
FR3103055A1 (fr) * 2019-11-08 2021-05-14 Soitec Procédé de finition d’une couche semi-conductrice monocristalline transférée sur un substrat receveur
FR3133104A1 (fr) * 2022-02-28 2023-09-01 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procédé de collage par activation de surface par bombardement d’ions ou d’atomes d’une première surface d’un premier substrat à une deuxième surface d’un deuxième substrat

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JP2002022159A (ja) 2000-07-07 2002-01-23 Matsushita Electric Ind Co Ltd 一酸化炭素の検知装置

Also Published As

Publication number Publication date
FR2797714B1 (fr) 2001-10-26
US20040115905A1 (en) 2004-06-17
JP4582982B2 (ja) 2010-11-17
EP1208593B1 (de) 2011-02-16
US20050208322A1 (en) 2005-09-22
KR100752467B1 (ko) 2007-08-24
US6902988B2 (en) 2005-06-07
TW530378B (en) 2003-05-01
WO2001015218A1 (fr) 2001-03-01
MY125775A (en) 2006-08-30
EP1208593A1 (de) 2002-05-29
JP2003510799A (ja) 2003-03-18
KR20020031412A (ko) 2002-05-01
US7235427B2 (en) 2007-06-26
FR2797714A1 (fr) 2001-02-23

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