DE69127582T2 - Verfahren zur Herstellung eines Halbleitersubstrates und Verfahren zur Herstellung einer Halbleiteranordnung unter Verwendung dieses Substrates - Google Patents
Verfahren zur Herstellung eines Halbleitersubstrates und Verfahren zur Herstellung einer Halbleiteranordnung unter Verwendung dieses SubstratesInfo
- Publication number
- DE69127582T2 DE69127582T2 DE69127582T DE69127582T DE69127582T2 DE 69127582 T2 DE69127582 T2 DE 69127582T2 DE 69127582 T DE69127582 T DE 69127582T DE 69127582 T DE69127582 T DE 69127582T DE 69127582 T2 DE69127582 T2 DE 69127582T2
- Authority
- DE
- Germany
- Prior art keywords
- manufacturing
- substrate
- semiconductor
- semiconductor device
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B28—WORKING CEMENT, CLAY, OR STONE
- B28D—WORKING STONE OR STONE-LIKE MATERIALS
- B28D5/00—Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12972590 | 1990-05-18 | ||
JP23777590 | 1990-09-07 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69127582D1 DE69127582D1 (de) | 1997-10-16 |
DE69127582T2 true DE69127582T2 (de) | 1998-03-26 |
Family
ID=26465027
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69127582T Expired - Fee Related DE69127582T2 (de) | 1990-05-18 | 1991-05-16 | Verfahren zur Herstellung eines Halbleitersubstrates und Verfahren zur Herstellung einer Halbleiteranordnung unter Verwendung dieses Substrates |
Country Status (4)
Country | Link |
---|---|
US (1) | US5227339A (de) |
EP (1) | EP0460437B1 (de) |
KR (1) | KR950003227B1 (de) |
DE (1) | DE69127582T2 (de) |
Families Citing this family (34)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06112451A (ja) * | 1992-09-29 | 1994-04-22 | Nagano Denshi Kogyo Kk | Soi基板の製造方法 |
US5427644A (en) * | 1993-01-11 | 1995-06-27 | Tokyo Seimitsu Co., Ltd. | Method of manufacturing semiconductor wafer and system therefor |
US5360509A (en) * | 1993-03-08 | 1994-11-01 | Gi Corporation | Low cost method of fabricating epitaxial semiconductor devices |
US5389579A (en) * | 1993-04-05 | 1995-02-14 | Motorola, Inc. | Method for single sided polishing of a semiconductor wafer |
EP0709878B1 (de) * | 1994-10-24 | 1998-04-01 | Naoetsu Electronics Company | Verfahren zur Herstellung von Einzelsubstraten aus einem Silizium-Halbleiterwafer |
JP2910507B2 (ja) * | 1993-06-08 | 1999-06-23 | 信越半導体株式会社 | 半導体ウエーハの製造方法 |
US5733175A (en) | 1994-04-25 | 1998-03-31 | Leach; Michael A. | Polishing a workpiece using equal velocity at all points overlapping a polisher |
US5607341A (en) | 1994-08-08 | 1997-03-04 | Leach; Michael A. | Method and structure for polishing a wafer during manufacture of integrated circuits |
JPH08222798A (ja) * | 1995-02-15 | 1996-08-30 | Mitsubishi Electric Corp | 半導体レーザの製造方法 |
US5937312A (en) * | 1995-03-23 | 1999-08-10 | Sibond L.L.C. | Single-etch stop process for the manufacture of silicon-on-insulator wafers |
US5635414A (en) * | 1995-03-28 | 1997-06-03 | Zakaluk; Gregory | Low cost method of fabricating shallow junction, Schottky semiconductor devices |
US5733814A (en) * | 1995-04-03 | 1998-03-31 | Aptek Industries, Inc. | Flexible electronic card and method |
US6268237B1 (en) | 1995-04-03 | 2001-07-31 | Aptek Industries, Inc. | Stress-free silicon wafer and a die or chip made therefrom and method |
US6054372A (en) * | 1995-04-03 | 2000-04-25 | Aptek Industries, Inc. | Stress-free silicon wafer and a die or chip made therefrom |
JP3213563B2 (ja) * | 1997-03-11 | 2001-10-02 | 株式会社スーパーシリコン研究所 | ノッチレスウェーハの製造方法 |
US6391744B1 (en) * | 1997-03-19 | 2002-05-21 | The United States Of America As Represented By The National Security Agency | Method of fabricating a non-SOI device on an SOI starting wafer and thinning the same |
CN1272222A (zh) * | 1997-08-21 | 2000-11-01 | Memc电子材料有限公司 | 处理半导体晶片的方法 |
WO1999026282A1 (fr) * | 1997-11-18 | 1999-05-27 | Mitsui Chemicals, Incorporated | Procede de fabrication pour plaquette en semiconducteur |
WO1999031723A1 (en) * | 1997-12-12 | 1999-06-24 | Memc Electronic Materials, Inc. | Method of improving the flatness of polished semiconductor wafers |
US6248651B1 (en) | 1998-06-24 | 2001-06-19 | General Semiconductor, Inc. | Low cost method of fabricating transient voltage suppressor semiconductor devices or the like |
JP3329288B2 (ja) * | 1998-11-26 | 2002-09-30 | 信越半導体株式会社 | 半導体ウエーハおよびその製造方法 |
US6214704B1 (en) | 1998-12-16 | 2001-04-10 | Memc Electronic Materials, Inc. | Method of processing semiconductor wafers to build in back surface damage |
US6716722B1 (en) * | 1999-07-15 | 2004-04-06 | Shin-Etsu Handotai Co., Ltd. | Method of producing a bonded wafer and the bonded wafer |
FR2797714B1 (fr) * | 1999-08-20 | 2001-10-26 | Soitec Silicon On Insulator | Procede de traitement de substrats pour la microelectronique et substrats obtenus par ce procede |
US6383056B1 (en) | 1999-12-02 | 2002-05-07 | Yin Ming Wang | Plane constructed shaft system used in precision polishing and polishing apparatuses |
FR2819099B1 (fr) * | 2000-12-28 | 2003-09-26 | Commissariat Energie Atomique | Procede de realisation d'une structure empilee |
JP2002334927A (ja) * | 2001-05-11 | 2002-11-22 | Hitachi Ltd | 半導体装置の製造方法 |
FR2835652B1 (fr) * | 2002-02-04 | 2005-04-15 | St Microelectronics Sa | Procede de fabrication d'un circuit integre comportant des transistors bipolaires, en particulier a heterojonction si/sige, et des transistors a effet de champ a grilles isolees, et circuit integre correspondant |
JP2004022899A (ja) * | 2002-06-18 | 2004-01-22 | Shinko Electric Ind Co Ltd | 薄シリコンウエーハの加工方法 |
JP2004119943A (ja) * | 2002-09-30 | 2004-04-15 | Renesas Technology Corp | 半導体ウェハおよびその製造方法 |
DE102005046726B4 (de) * | 2005-09-29 | 2012-02-02 | Siltronic Ag | Nichtpolierte monokristalline Siliziumscheibe und Verfahren zu ihrer Herstellung |
JP4533934B2 (ja) * | 2008-01-15 | 2010-09-01 | エプソントヨコム株式会社 | 振動片及び振動子の製造方法 |
EP2870626B1 (de) * | 2012-07-03 | 2021-06-23 | RFHIC Corporation | Verbundwafer mit temporärem trägerwafer und halbleiter auf diamant-wafer und verfahren zu seiner herstellung |
FI129826B (en) * | 2020-10-08 | 2022-09-15 | Okmetic Oy | Manufacturing method of high-resistive silicon wafer intended for hybrid substrate structure |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0161740B1 (de) * | 1984-05-09 | 1991-06-12 | Kabushiki Kaisha Toshiba | Verfahren zur Herstellung eines Halbleitersubstrates |
JPS62154614A (ja) * | 1985-12-27 | 1987-07-09 | Toshiba Corp | 接合型半導体基板の製造方法 |
JPS62181869A (ja) * | 1986-01-31 | 1987-08-10 | Sumitomo Electric Ind Ltd | 半導体ウエハの研磨方法 |
JPH06103678B2 (ja) * | 1987-11-28 | 1994-12-14 | 株式会社東芝 | 半導体基板の加工方法 |
EP0368584B1 (de) * | 1988-11-09 | 1997-03-19 | Sony Corporation | Herstellungsverfahren eines Halbleiterwafers |
JP2825322B2 (ja) * | 1989-09-13 | 1998-11-18 | 株式会社東芝 | 誘電体分離構造を有する半導体基板の製造方法 |
-
1991
- 1991-05-16 DE DE69127582T patent/DE69127582T2/de not_active Expired - Fee Related
- 1991-05-16 EP EP91107952A patent/EP0460437B1/de not_active Expired - Lifetime
- 1991-05-17 KR KR1019910008057A patent/KR950003227B1/ko not_active IP Right Cessation
- 1991-05-17 US US07/701,809 patent/US5227339A/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
EP0460437A2 (de) | 1991-12-11 |
EP0460437B1 (de) | 1997-09-10 |
US5227339A (en) | 1993-07-13 |
EP0460437A3 (de) | 1995-04-19 |
KR950003227B1 (ko) | 1995-04-06 |
KR910020806A (ko) | 1991-12-20 |
DE69127582D1 (de) | 1997-10-16 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |