FI129826B - Manufacture method of a high-resistivity silicon handle wafer for a hybrid substrate structure - Google Patents

Manufacture method of a high-resistivity silicon handle wafer for a hybrid substrate structure Download PDF

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Publication number
FI129826B
FI129826B FI20205989A FI20205989A FI129826B FI 129826 B FI129826 B FI 129826B FI 20205989 A FI20205989 A FI 20205989A FI 20205989 A FI20205989 A FI 20205989A FI 129826 B FI129826 B FI 129826B
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wafer
polishing
thickness
grinding
front surface
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FI20205989A
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Finnish (fi)
Swedish (sv)
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FI20205989A1 (en
Inventor
Samuli Sievänen
Päivi Sievilä
Karri Mannermaa
Jukka-Pekka Lähteenmäki
Atte Haapalinna
Joel Salmi
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Okmetic Oy
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Priority to FI20205989A priority Critical patent/FI129826B/en
Priority to KR1020237012366A priority patent/KR20230080428A/en
Priority to PCT/FI2021/050664 priority patent/WO2022074297A1/en
Priority to JP2023520210A priority patent/JP2023549029A/en
Priority to CN202180069096.5A priority patent/CN116325084A/en
Priority to EP21877067.5A priority patent/EP4226411A1/en
Publication of FI20205989A1 publication Critical patent/FI20205989A1/en
Application granted granted Critical
Publication of FI129826B publication Critical patent/FI129826B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H01L21/02013—Grinding, lapping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H01L21/02024—Mirror polishing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/08—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/02535—Details of surface acoustic wave devices
    • H03H9/02543—Characteristics of substrate, e.g. cutting angles
    • H03H9/02574—Characteristics of substrate, e.g. cutting angles of combined substrates, multilayered substrates, piezoelectrical layers on not-piezoelectrical substrate

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Acoustics & Sound (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Grinding Of Cylindrical And Plane Surfaces (AREA)
  • Grinding And Polishing Of Tertiary Curved Surfaces And Surfaces With Complex Shapes (AREA)
  • Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)

Abstract

The application relates to a manufacture method (100) of a high-resistivity silicon handle wafer (230) for a hybrid substrate structure (336). The method comprises a step of producing (108, 112, 114) the wafer (212) having a crystal orientation identifier (210) and a certain thickness (h1). The method further comprises a step of thinning (116, 122) the produced wafer from the certain thickness to a desired thickness (h5) of the wafer (222) in order to obtain the thinned wafer (222). The method further comprises a step of providing (128) a surface passivation layer (229) having a certain layer thickness (h6) on a front surface (221) of the thinned wafer. The method further comprises a step of polishing (130) the passivation layer from the certain layer thickness to a desired final layer thickness (h9) of the passivation layer so that the polished front surface (232) of the wafer (230) enables active layer bonding in order to form the hybrid substrate structure. The step of thinning comprises a controlled single-side, fixed abrasive grinding (116, 118, 120) of the produced, crystal orientation identifier-comprised wafer (218) with a chuck arrangement, which eliminates at least partly an effect of non-circular asymmetry caused by the identifier, in order to manufacture the wafer (218, 222) with a desired submicron total thickness variation for the formation of the hybrid substrate structure.

Description

MANUFACTURE METHOD OF A HIGH-RESISTIVITY SILICON HANDLE WAFER
FOR A HYBRID SUBSTRATE STRUCTURE Technical field The application relates generally to a manufacture method of a high-resistivity sili- con handle wafer for a hybrid substrate structure, a high-resistivity silicon handle wafer, and a hybrid substrate structure. Background Devices, which are manufactured on hybrid wafers, utilize an active layer that is bonded to a single crystal silicon handle wafer and thinned against it. The handle wafer enables to a reliable handling of hybrid material with advanced tools, which are designed for standard silicon wafer processing, and it provides mechanical sta- bility and compatibly with cleanliness and chemicals, which are used in semicon- ductor manufacturing. One example of such devices is piezoacoustic thin film sur- face acoustic wave (TF-SAW) filters, which are designed to utilize a thin active layer made of e.g. piezomaterial. Hybrid wafer structures, which are used for devices operating at radio frequencies (RF) of several hundreds of MHz to several tens of GHz, require the use of very high resistivity (over 5000 Q-cm) silicon substrates, featured with an additional parasitic current suppression surface passivation layer, in order to minimize an interaction of the RF signal with the handle wafer. One example of such silicon substrate is ex- plained in patent US 9,312,345. The performance of these devices, which are on the thinned-down active layer, is N to a large extend limited by by their geometric accuracy. The final device geometry > is defined both by the manufacture process of the device and the thickness control <Q 25 ofthe active layer in a substrate process. As the accuracy of the device manufacture NN process is defined using lithography, the precision achievable with modern pro- E cesses is very high. This increases the relative importance of active layer thickness o variation, as this dimension cannot be controlled in the same manner. 00 2 The geometry of the handle wafer strongly influences the geometry of the thinned- S 30 down active layer, typically resulting a thickness variation roughly the same in ab- solute terms (um). As the active layer is very thin in comparison to the handle wafer thickness, the proportional geometry variation becomes significantly higher. Thus, the flatness requirement for the handle wafer is far beyond to that of standard silicon substrates. In accordance with SEMI M1, a total thickness variation (TTV) is defined as 10 um for 625 pm-thick polished wafers with a 150 mm diameter.
The TTV is especially critical when it appears non-circular symmetrically over a wa- fer surface, as a further rotational active layer thinning process can be relatively easily adjusted in radial direction, but correcting other shapes is much more compli- cated.
The preceding drawbacks have limited significantly the performance of existing de- vices having the thinned-down active layer.
Summary One object of the invention is to withdraw drawbacks of known solutions and to pro- vide a manufacture method for a high-resistive, surface-passivated silicon handle wafer, which compensates a geometric influence of a produced crystal orientation identifier and enables higher flatness of a 150-200 mm -diameter silicon handle wa- fer used in a hybrid substrate structure.
One object of the invention is fulfilled by providing a manufacture method, a high- resistivity silicon handle wafer, and a hybrid substrate structure according to the independent claims.
Embodiments of the invention are specified by the manufacture method, a high- resistivity silicon handle wafer, and a hybrid substrate structure according to the independent claims.
One manufacture method of a high-resistivity silicon handle wafer for a hybrid sub- N strate structure comprises a step of producing the wafer having a crystal orientation O identifier and a certain thickness. The method further comprises a step of thinning O the produced wafer from the certain thickness to a desired thickness of the wafer in oO 25 order to obtain the thinned wafer. The method further comprises a step of providing - a surface passivation layer having a certain layer thickness on a front surface of the = thinned wafer. The method further comprises a step of polishing the passivation 3 layer from the certain layer thickness to a desired final layer thickness of the pas- 3 sivation layer so that the polished front surface of the wafer enables active layer S 30 bonding (bonding of an active layer) in order to form the hybrid substrate structure. N The step of thinning comprises a controlled single-side, fixed abrasive grinding of the produced, crystal orientation identifier-comprised wafer with a chuck arrange- ment, which eliminates at least partly an effect of non-circular asymmetry caused by the identifier, in order to manufacture the wafer with a desired submicron total thick- ness variation. One high-resistivity silicon handle wafer for a hybrid substrate structure is manufac- tured in accordance with the steps of previous method. One hybrid substrate structure comprises the high-resistivity silicon in accordance with the previous handle wafer. Brief description of the figures The exemplary embodiments of the invention are explained with reference to the accompanying figures: Fig. 1a-1b present a flowchart of manufacture method of a handle wafer Fig. 2a-2b — present how the handle wafer is processed during the manufacture method Fig. 3a-3b — present how an active layer is bonded to the manufactured handle wa- fer and thinned to form a hybrid substrate structure Detailed description of the figures Fig. 1a and 1b present how steps of manufacture method 100 of a high-resistivity silicon (HRS) handle wafer 230 for a hybrid substrate structure 336 proceed and, beside the method steps, fig. 2a and 2b how each method step effects to the wafer
230. Fig. 3a and 3b present the hybrid substrate structure 336, which may be used in manufacturing a piezoacoustic thin film surface acoustic wave (TF-SAW) filter or N other, e.g. sapphire-on-silicon, III-IV hybrid substrate structure, or [I-VI hybrid sub- > strate structure, which is based on thinned down material layers. The hybrid sub- <Q strate structure 336 utilizes a thin active layer 334, which is made of sapphire or NN 25 compound semiconductor material, and which is fusion bonded in accordance with E fig. 3a and thinned against the wafer 230 in accordance with fig. 3b. & At step 108, a crystal puller, which is suitable either for a float zone (FZ) or Magnetic S Czochralski (MCz) silicon crystal growth, is used in crystal growing. Special prepa- S rations, which are necessary for extremely low impurity cystal growth are carried out, e.g. the verification of very high cleanliness status of crystal growth chamber, the availability of very high purity inert gas, and the extremely tight control of impu- rities added to a polysilicon charge to be used.
Then, at step 108, a HRS ingot, which has a target diameter (d) of 150-210 mm, e.g. 150, 160, 170, 180, 190, or 200 mm, is pulled in the growing chamber as the first stage of production of the wafer 230. The grown HRS ingot is cut and ground for producing a crystal orientation identifier 210, which is e.g. a primary flat when the diameter d of HRS ingot is 150 mm or a notch when the diameter d is 200 mm, along a side of the HRS ingot. The primary flat 210, which is used as an example of an identifier 210 in these fig- ures, is used as a standard identifier in order to identify the surface orientation for a 150 mm silicon wafer 230. The surface orientation of a silicon wafer 230 is required to be exactly {111} or very close to it, or exactly {100} or very close to it, typically at most with 0,5 degree tolerance. The primary flat 210 is an irregularity in the round shape of a silicon wafer 230 that invariably causes flathess degradation in mechan- ical thinning steps typically used in wafer manufacturing, e.g. grinding and polishing steps 116, 122. The method 100 compensates the influence of the identifier 210 and enables higher flatness for the silicon wafer 230, e.g. for the 150 mm-diameter silicon wafer 230, specification of which typically requires the primary flat 210 because of processing tool requirements for this wafer size, and for a 200 mm-diameter silicon wafer 230. At step 112, HRS wafers 212 are sliced from the produced HRS ingot, e.g. by multi- wire slicing in accordance with the current industry standard. The slicing process applies mechanical force to remove material and creates sub-surface crystal lattice damage into and under the front (top) surface 209 of sliced wafers 212. Naturally, similar crystal lattice damage is also incorporated into and under the back surface 211 of sliced wafers 212. The incorporated crystal lattice damage creates a disor- N 25 dered lattice damage zone 213 into the front (top) side of sliced wafers 212 and N another disordered lattice damage zone (not presented in the figures) into the back S side of sliced wafers 212.
O - Each sliced wafer 212 comprises single crystal silicon, the identifier 210 and the first & thickness h1, which is a distance between the front and back surfaces 209, 211.
O 3 30 Atstep 114, the sliced wafer 212 may be thinned at least from its front side by lap- N ping in order to remove at least partly the slicing-based crystal damage, i.e. the N disordered zone 213, and the lapped wafer 212 may be cleaned. Since the lapping process also incorporates mechanically some sub-surface crys- tal lattice damage into the sliced wafer 212, the lapped wafer 212 comprises the disordered zone 213. Alternatively, if the slicing-based crystal damage is meant to retain at least partly in the lapped wafer 212, it is possible to modify the lapping process so that at least a part of the slicing-based disordered zone 213 remains, whereupon the lapped wafer 212 comprises the slicing and lapping-based crystal 5 damages.
Then, at step 114, the lapped wafer 212 may be acid etched in order to remove at least partly the produced crystal damage(s) and, then, the etched wafer 212 is in- spected visually, cleaned, and processed by thermal donor anneal.
At step 116, the processed, identifier 210-comprised wafer 212 is attached to a chuck arrangement of a grinding machine and only its front surface 209 on the front side of the wafer 212 is exposed to a controlled single-side, fixed abrasive grinding, which is carried out by a rotating grinding wheel of the grinding machine.
As a result of the fixed abrasive grinding process, the thickness of the wafer 218 decreases about a distance h2 from the first thickness h1 to a third thickness h3 so that its front surface 217 approaches the back surface of wafer 218 said distance h2. Additionally, the fixed abrasive grinding process incorporates mechanically again some sub-surface crystal lattice damage into and under the front surface 217 of the ground wafer 218, and creates the disordered zone 213 into the front side of the ground wafer 218, if such does not already exist.
The effective, short control loop controlled, fixed abrasive grinding process elimi- nates at least partly, in fact significantly, the effect of asymmetric variation (non- circular asymmetry), which is caused at least partly by the identifier 210 from the front surface 217 of the ground wafer 218 so that it is possible to obtain a desired N total thickness variation (TTV) on the wafer 218. The TTV defines the difference O 25 between the minimum (min, lowest) thickness and the maximum (max, highest) O thickness of the wafer 218, 222, 230 in accordance with fig. 2a.
NN At step 118, during the fixed abrasive grinding process, it is monitored continuosly E by at least one of an optical measurement (eguipment, system) and a charge carrier- o adjusted capacitive measurement (eguipment, system), and at least one grinding 3 30 parameter is controlled continuously.
O O For HRS wafers 212, 218 the standard capacitive measurement cannot be reliably applied due to the lack of conductivity in the material to be measured. Additionally, the control of achievable accuracy in thickness is not sufficient. Thus, the use of optical or charge carrier-adjusted capacitive measurement, which enables higher accuracy, is needed to meet the thickness variation requirements for wafers 230, which are used in the hybrid substrate structure 336. When using capacitive measurements, effective electrostatic discharging (ESD) is incorporated in the measurement equipment.
Cross correlation of optical and suita- bly modified capacitive geometry measurement enhances the measurement system as a whole as these technologies complement each other.
A measurement system, that reliably gives accurate, high-resolution data of the whole wafer geometry even for ultra high resistivity silicon, enables effective, short feedback loop needed to ob- tain the required precise geometry control.
With method 100, it is possible to achieve clearly superior flatness capability compared to an integrated and automated flat- ness control feature that can be found in typical commercially available tools for single-side grinding of silicon wafers 212, which typically claim capabilities between 1 and 2 um in the TTV.
The grinding parameter(s) comprises at least one of the cooling water temperature of the chuck arrangement, the grinding chuck inclination of the chuck arrangement, and the grinding feed rate of the grinding wheel.
At step 120, if it is necessary to adjust the grinding parameter(s) because of a pre- determined grinding plan or an emerged need as a result of monitoring, said grinding parameter(s) is adjusted during the the fixed abrasive grinding process in order to achieve the desired TTV.
For example, the tolerance of cooling water temperature is in a range of +1*C or better.
The inclinations of grinding chuck between the wafer 212 and the grinding wheel are constantly monitored, e.g. 0,5 to 2 per hour in a constant operation and N adjusted with short feedback loop.
The incoming TTV is in a range of 1 to 5 um.
In O 25 order to obtain high surface quality and to enable stable cutting efficiency for the O grinding wheel, the grinding feed rate is in a range of 0.15 to 1 um per second. oO Additionally, a diamond size and type of grinding wheel is selected for the best com- - bination of throughput, robustness, and surface guality.
The particle cleanliness of = the incoming wafer 218 must be sufficient to prevent generation of local excess ma- 2 30 terial removal.
N At step 122, the single-side ground wafer 218 is attached to a wafer carrier of a N polishing machine and only its ground front surface 217 on the front side of the wafer 218 is exposed to a controlled polishing, which is carried out by a rotating polishing pad of the polishing machine.
As a result of the polishing process, the thickness of the wafer 222, as well as its lattice damage zone 213, decreases about a fourth distance h4 from the third thick- ness h3 to a fifth thickness h5 so that its polished front surface 222 approaches the back surface of wafer 222 said fourth distance h4. Additionally, the polishing process removes the sub-surface crystal lattice damage under the front surface 221 of the polished wafer 218. The polishing process finishes the elimination of the thickness variation from the polished wafer 222 so that the polished wafer 222 meets the desired TTV level. The desired TTV of the wafer 222, 230 is less than 600 nm, e.g. 200, 300, 400, or 500 nm. At step 124, during the polishing process, it is monitored continuosly by a Makyoh mirror, an optical measurement (equipment) or a geometry-monitoring suitable car- rier-adjusted capacitive measurement (equipment, system), and a surface scanning equipment (system) and at least one polishing parameter is controlled continuously. The polishing parameter(s) comprises at least one of the polishing pressure of the wafer 222 and the polishing pad, the rotation speed of the wafer 222 and the polish- ing pad, and the location of the wafer 222 relative to the polishing pad. At step 126, if it is necessary to adjust the polishing parameter(s) because of a pre- determined polishing plan or an emerged need as a result of monitoring, said at least one polishing parameter is adjusted during the the polishing process in order to achieve the desired TTV, to complete the thinning steps 116, 122 so that the thinned wafer 222 is ready for a treatment, which produces parasitic current sup- pression in radio frequencies (RF).
N
QA N At step 128, the thinned wafer 222 is set into a deposition chamber of a deposition © 25 machine and at least one polysilicon layer 229 is deposited on its front surface 221 IN by a chemical vapour deposition (CVD) process. The deposited polysilicon layer(s) z 229 comprises a highly uniform polysilicon film, which has a total layer thickness h6. 3 As a result of the deposition process, the thickness of the wafer 222 increases about 3 a sixth distance h6, which is equal with the total layer thickness h6, from the fifth S 30 thickness h5 to a seventh thickness h7 so that its front surface 223 goes away from
N the back surface of the wafer 222 said sixth distance h6.
At step 130, the wafer 222, which comprises the deposited polysilicon layer(s) 229, is attached to a wafer carrier of a polishing machine, which is suitable for chemical- mechanical polishing, and only its deposited front surface 223 on the front side of the wafer 222 is exposed to controlled chemical-mechanical polishing, which is car- ried out by a rotating polishing pad of the polishing machine. As a result of the chemical-mechanical polishing process, the thickness of the wafer 230 decreases about an eight distance h8 from the seventh thickness h7 to a tenth thickness h10 and the thickness of deposited polysilicon layer(s) 229 decreases about said eight distance h8 from the sixth thickness ht to a nineth thickness h9 so that its front surface 232 approaches the back surface of the wafer 230 said eight distance h8. Additionally, the chemical-mechanical polishing process provides the polysilicon layer(s) 229 with the desired thickness h9 and a mirror-polished front surface 232, which is suitable for fusion bonding the hybrid substrate structure 336. At step 134, the chemical-mechanical polishing process is monitored continuosly by — measuring polished wafers 230 with an optical measurement (equipment) , e.g. in- terferometry, reflectometry, or ellipsometry, using an optical wavelenght range from visible (VIS) to near-infrared (NIR), and at least one chemical-mechanical polishing parameter is controlled continuously. The operating principle of the optical measurement is based on reflecting broadband light from the front surface 223 and the polysilicon layer(s) interface, and calculating the layer thickness from the resulting spectrum. The reflected light shows a periodic interference spectrum based on the layer thickness versus the wavelength, and the thickness is calculated from the signal by using a theoretical model for a layer having a matching period. The poly—monocrystalline silicon interface produces only a weak N 25 reflection due to a small difference in the refractive indices of poly- and monocrys- N talline silicon materials. A moderate difference is still seen in the visible part of the S spectrum, although light absorbance in silicon is high in the same wavelength area. IN The optimal spectral range found is from 600 nm to 900 nm. E: The chemical-mechanical polishing parameter(s) comprises at least one of the re- 3 30 moval rate of material from the front surface 223 of the wafer 222 and the polishing 3 time of the front surface 223 of the wafer 222.
QA S At step 136, if it is necessary to adjust the chemical-mechanical polishing parame- ter(s) because of a predetermined polishing plan or an emerged need as a result of monitoring, said chemical-mechanical polishing parameter(s) is adjusted during the the chemical-mechanical polishing process in order to achieve the desired final layer thickness h9 of the polysilicon layer(s) 229 and to complete the polishing step 130 so that the processed wafer 230 is ready for fusion bonding with the active layer 334 in accordance with fig. 3a to form a hybrid substrate structure 336.
This method 100 addresses the critical importance of the geometry of the wafer 230, especially its non-circular symmetric variation, by carrying out the vast majority of material removal of the wafer shape definition with a circular symmetric, fixed abra- sive grinding process. A double-sided variant of this type of process is widely used for reaching very tight geometry in manufacturing 300 mm-diameter wafers, but the same is not possible for smaller wafer sizes relevant to substrates bonded to a sin- gle crystal silicon wafer 230. One-sided grinding tools are commercially available for these wafer sizes, but the typical processes are not capable of the geometric accuracy needed. The method 100 uses very well controlled, single-side grinding to manufacture very accurately — defined geometries, resulting a TTV typically in the level of 500 nm in the wafer 230. Importantly, because of the radial processing, this variation mainly appears as a circular symmetric shape with the asymmetric part of the thickness variation being as low as 200 nm. The invention has been explained above with reference to the above-mentioned exemplary embodiments and its several advantages have been demonstrated. It is clear that the invention is not only restricted to these embodiments, but it comprises all possible embodiments within the scope of the following claims.
N QA O N
O <Q
O N
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LO O QA O N

Claims (17)

Claims
1. A manufacture method (100) of a high-resistivity silicon handle wafer (230) for enabling a formation of a hybrid substrate structure (336), comprising steps of producing (108, 112, 114) the wafer (212) having a crystal orientation identifier (210) and a certain thickness (h1), thinning (116, 122) the produced wafer from the certain thickness to a desired thickness (h5) of the wafer (222) in order to obtain the thinned wafer (222), providing (128) a surface passivation layer (229) having a certain layer thick- ness (h6) on a front surface (221) of the thinned wafer, and polishing (130) the passivation layer from the certain layer thickness to a de- sired final layer thickness (h9) of the passivation layer so that the polished front surface (232) of the wafer (230) enables active layer bonding in order to form the hybrid substrate structure, characterized in that the step of thinning comprises a controlled single-side, fixed abrasive grinding (116, 118, 120) of the produced, crystal orientation identifier- comprised wafer (218) with a chuck arrangement, which eliminates significantly an effect of non-circular asymmetry caused by the identifier, in order to manufacture the wafer (218, 222) with a desired submicron total thickness variation for enabling the formation of the hybrid substrate structure.
2. The method according to the preceding claim, wherein the step of controlled grinding comprises a continuous control (118) of at least one grinding parameter during the controlled grinding (116) and, when necessary, an adjustement (120) of the at least one grinding parameter in order to achieve the desired total thickness variation.
N 25
3. The method according to claim 2, wherein the step of continuos control of the N at least one grinding parameter comprises a control (118) of at least one of a cooling S water temperature of the chuck arrangement, a grinding chuck inclination of the IN chuck arrangement, and a grinding feed rate of a grinding wheel. E:
4. The method according to claim 2 or 3, wherein the step of continuos control of 3 30 the at least one grinding parameter comprises a monitoring (118) of the controlled 3 grinding by an optical measurement and/or a charge carrier-adjusted capacitive O measurement.
5. The method according to any of the preceding claims, wherein the step of thin- ning further comprises controlled polishing (122, 124, 126) of the single-side, fixed abrasive ground wafer (218) from its ground front surface (217) in order to control a condition of the front surface of the wafer.
6. The method according to claim 5, wherein the step of controlled polishing com- prises polishing (122, 124, 126) of the single-side, fixed abrasive ground handle wafer.
7. The method according to claim 5 or 6, wherein the step of controlled polishing comprises a continuous control (124) of at least one polishing parameter during the controlled polishing (122) and, when necessary, an adjustement (126) of the at least one polishing parameter in order to achieve the desired thickness of the wafer.
8. The method according to any of claims 5-7, wherein the step of continuos con- trol of the at least one polishing parameter comprises a control (124) of at least one of a polishing pressure of the wafer (222) and a polishing pad, a rotation speed of the wafer and the polishing pad, and a location of the wafer relative to the polishing pad.
9 The method according to any of claims 5-8, wherein the step of continuos con- trol of the at least one polishing parameter comprises a monitoring (124) of the con- trolled polishing by a Makyoh mirror, an optical measurement equipment or a carrier- adjusted capacitive measurement equipment for geometry monitoring, and a sur- face scanning equipment.
10. The method according to any of the preceding claims, wherein a diameter (d) of the wafer is 150-200 mm, a surface orientation of the handle wafer is {111}, and the desired total thickness variation of the completed wafer is less than 600 nm.
N
11. The method according to any of the preceding claims, wherein the step of pro- N duction of the surface passivation layer comprises a deposition of (128) at least one S 25 — polysilicon layer (229) having the certain layer thickness (h6) on the front surface IN (221) of the thinned wafer (222) by means of a chemical vapour deposition process. E:
12. Themethod according to claim 11, wherein the step of polishing of the surface 3 passivation layer comprises a controlled polishing (130) of the at least one deposited 3 polysilicon layer from the certain layer thickness of the at least one deposited pol- S 30 — ysilicon layer to a desired final layer thickness (h9) of the at least one deposited N polysilicon layer on the manufactured wafer (222) by means of a chemical-mechan- ical polishing process in order to provide the chemical-mechanical polished front surface (232) of the wafer (230).
13. The method according to claim 12, wherein the step of controlled chemical- mechanical polishing comprises a continuous control (132) of at least one chemical- mechanical polishing parameter during the controlled chemical-mechanical polish- ing (130) and, when necessary, an adjustement (134) of the at least one chemical- mechanical polishing parameter in order to achieve the desired final layer thickness.
14. The method according to claim 13, wherein the step of continuos control of the at least one chemical-mechanical polishing parameter comprises a control (132) of removal rate from a front surface (223, 232) of the wafer and polishing time of the front surface of the wafer.
15. The method according to claim 13 or 14, wherein the step of continuos control of the at least one chemical-mechanical polishing parameter comprises a monitoring (134) of the controlled chemical-mechanical polishing by an optical measurement equipment using an optical wavelenght range from visible to near-infrared (VIS-NIR) range.
16. Ahigh-resistivity silicon handle wafer (230) for enabling a formation of a hybrid substrate structure (336), which is manufactured by the steps of the method (100) according to any of the preceding claims, comprising the crystal orientation identifier (210), the desired thickness (h10), and the polished surface passivation layer (229) having the desired final layer thick- ness (h9) on the front surface (221) of the wafer (230), wherein the polished front surface (232) of the wafer is configured to enable active layer bonding for the formation of the hybrid substrate structure, characterized in that the wafer comprises the single-side, fixed abrasive N 25 ground wafer (218, 222) with the desired submicron total thickness variation, from N which wafer the effect of non-circular asymmetry caused by the identifier has been S eliminated significantly.
O -
17. Ahybrid substrate structure (336) comprising the high-resistivity silicon handle = wafer (230) according to claim 16. > 30
S
N
FI20205989A 2020-10-08 2020-10-08 Manufacture method of a high-resistivity silicon handle wafer for a hybrid substrate structure FI129826B (en)

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KR1020237012366A KR20230080428A (en) 2020-10-08 2021-10-08 Manufacturing Method of High Resistance Silicon Handle Wafers to Enabling Formation of Hybrid Substrate Structures
PCT/FI2021/050664 WO2022074297A1 (en) 2020-10-08 2021-10-08 Manufacture method of a high-resistivity silicon handle wafer for enabling a formation of a hybrid substrate structure
JP2023520210A JP2023549029A (en) 2020-10-08 2021-10-08 Method for manufacturing high-resistivity silicon handle wafers to enable the formation of hybrid substrate structures
CN202180069096.5A CN116325084A (en) 2020-10-08 2021-10-08 Method of manufacturing high resistivity silicon handle wafer capable of forming hybrid substrate structure
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