CN116325084A - Method of manufacturing high resistivity silicon handle wafer capable of forming hybrid substrate structure - Google Patents

Method of manufacturing high resistivity silicon handle wafer capable of forming hybrid substrate structure Download PDF

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Publication number
CN116325084A
CN116325084A CN202180069096.5A CN202180069096A CN116325084A CN 116325084 A CN116325084 A CN 116325084A CN 202180069096 A CN202180069096 A CN 202180069096A CN 116325084 A CN116325084 A CN 116325084A
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wafer
polishing
thickness
front surface
substrate structure
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佩伊维·谢维莱
萨穆利·谢韦宁
尤卡-佩卡·莱赫滕迈基
卡里·曼纳马
约珥·萨米
阿特·哈帕林纳
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Okmetic Oy
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Okmetic Oy
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H01L21/02013—Grinding, lapping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H01L21/02024—Mirror polishing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/08—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/02535—Details of surface acoustic wave devices
    • H03H9/02543—Characteristics of substrate, e.g. cutting angles
    • H03H9/02574—Characteristics of substrate, e.g. cutting angles of combined substrates, multilayered substrates, piezoelectrical layers on not-piezoelectrical substrate

Abstract

A method (100) of fabricating a high resistivity silicon handle wafer (230) capable of forming a hybrid substrate structure (336). The method includes producing the wafer (212) with a crystal orientation identifier (210), thinning the produced wafer to obtain a thinned wafer (222), providing a surface passivation layer (229) on a front surface (221) of the thinned wafer, and polishing the passivation layer to enable active layer bonding of a polished front surface (232) of the wafer to form the hybrid substrate structure. The thinning step includes controlled single-sided fixed abrasive lapping of the resulting wafer (218) including the crystal orientation identifier with a chuck arrangement that eliminates at least a majority of the effects of non-circular asymmetry caused by the identifier to produce the wafer with the desired sub-micron total thickness variation to enable formation of the hybrid substrate structure.

Description

Method of manufacturing high resistivity silicon handle wafer capable of forming hybrid substrate structure
Technical Field
The present application relates generally to a method of manufacturing a high resistivity silicon handle wafer capable of forming a hybrid substrate structure, a high resistivity silicon handle wafer, and a hybrid substrate structure.
Background
Devices fabricated on hybrid wafers utilize an active layer that is bonded to and thinned against a monocrystalline silicon handle wafer. The handle wafer is capable of reliably handling mixed materials with advanced tools designed for standard silicon wafer processing and provides mechanical stability and compatibility with cleaning and chemicals used in semiconductor manufacturing. One example of such a device is a piezoelectric acoustic thin film surface acoustic wave (TF-SAW) filter designed to utilize a thin active layer made of, for example, a piezoelectric material.
Hybrid wafer structures for devices operating at Radio Frequencies (RF) of hundreds of MHz to tens of GHz require the use of extremely high resistivity (exceeding 5000 Ω -cm) silicon substrates featuring additional parasitic current suppressing surface passivation layers in order to minimize RF signal interactions with the handle wafer.
The performance of these devices on thinned active layers is largely limited by their geometric accuracy. The final geometry of the device is defined by both the fabrication process of the device and the thickness control of the active layer in the substrate process. Since the accuracy of the device fabrication process is defined using photolithography, the accuracy achievable by modern processes is extremely high. This increases the relative importance of the variation in active layer thickness, as this dimension cannot be controlled in the same way.
The geometry of the handle wafer has a large impact on the geometry of the thinned active layer, typically resulting in thickness variations that are approximately the same in absolute value (μm). Since the active layer thickness is extremely thin compared to the handle wafer thickness, the proportional geometry variation becomes significantly higher. Thus, the flatness requirements of handle wafers far exceed those of standard silicon substrates. According to SEMI M1, the Total Thickness Variation (TTV) is defined as 10 μm for a polished wafer 150mm in diameter and 625 μm thick.
TTV is particularly important when non-circular shapes are symmetrically presented above the wafer surface, since further rotational active layer thinning processes can be adjusted relatively easily in the radial direction, but correcting other shapes is much more complicated.
The aforementioned drawbacks significantly limit the performance of existing devices with thinned active layers.
Disclosure of Invention
It is an object of the present invention to eliminate the drawbacks of the known solutions and to provide a method of manufacturing high-resistance, surface-passivated silicon handle wafers that compensates for the geometrical influence of the resulting crystal orientation identifier and enables silicon handle wafers with diameters of 150 to 200mm to have a higher flatness. The silicon handle wafer thus manufactured is used to form a hybrid substrate structure, and then the formed hybrid substrate structure can be used in a device manufacturing method, such as a front-end and back-end method, to manufacture a semiconductor device (component).
One object of the present invention is met by providing a manufacturing method, a high resistivity silicon handle wafer and a hybrid substrate structure according to the independent claims.
Embodiments of the invention are specified by the manufacturing method, the high resistivity silicon handle wafer and the hybrid substrate structure according to the independent claims.
A method of fabricating a high resistivity silicon handle wafer capable of forming a hybrid substrate structure includes the steps of creating a wafer having a crystal orientation identifier and a specific thickness. The method further includes the step of thinning the resulting wafer from a particular thickness to a desired thickness of the wafer to obtain a thinned wafer. The method further includes the step of providing a surface passivation layer having a specific layer thickness on the front surface of the thinned wafer. The method further includes the step of polishing the passivation layer from a particular layer thickness to a desired final layer thickness of the passivation layer, enabling active layer bonding (bonding of active layers) of the polished front surface of the wafer to form a hybrid substrate structure. The thinning step includes controlled single-sided fixed abrasive lapping of the resulting wafer including the crystal orientation identifier with a chuck arrangement that eliminates at least a substantial portion of the effects of non-circular asymmetry caused by the identifier to produce a wafer having the desired sub-micron total thickness variation to enable formation of a hybrid substrate structure.
A high resistivity silicon handle wafer capable of forming a hybrid substrate structure is fabricated according to the steps of the foregoing method.
A hybrid substrate structure includes high resistivity silicon according to the handle wafer previously described.
Drawings
Exemplary embodiments of the present invention will be explained with reference to the accompanying drawings:
FIGS. 1a to 1b present a flow chart of a method of manufacturing a handle wafer
Figures 2a to 2b present how a handle wafer is handled during the manufacturing method
Fig. 3a to 3b show how the active layer is bonded to the handle wafer being manufactured and thinned in the front end fabrication method to form a hybrid substrate structure.
Detailed Description
Fig. 1a and 1b present how the steps of method 100 of fabricating a High Resistivity Silicon (HRS) handle wafer 230, which is ready (prepared) for forming (fabricating) a hybrid substrate structure 336, are performed, and fig. 2a and 2b present how each method step acts on wafer 230 in addition to the method steps.
Fabrication of wafer 230 occurs prior to formation of hybrid substrate structure 336 and a device fabrication stage in which hybrid substrate structure 336 is formed exposed to at least one device fabrication method (process). Device fabrication methods, including, for example, front-end methods (processes) and back-end methods (processes), are directed to the hybrid substrate structure 336 to obtain (fabricate, process) semiconductor devices (components).
Fig. 3a and 3b present a hybrid substrate structure 336 that is fabricated in a front-end process by using the processed wafer 230 as a handle wafer and that can be used to fabricate a piezoelectric acoustic thin film surface acoustic wave (TF-SAW) filter or other structure based on a thinned material layer, such as a sapphire on silicon, III-IV hybrid substrate structure, or II-VI hybrid substrate structure. The hybrid substrate structure 336 utilizes a thin active layer 334 made of sapphire or a compound semiconductor material and which is fusion bonded during the front-end process according to fig. 3a and thinned against the wafer 230 according to fig. 3 b.
At step 108, a crystal puller suitable for Floating Zone (FZ) or magnetic Czochralski (MCz) silicon crystal growth is used in the crystal growth. Special preparations necessary for extremely low impurity crystal growth are made, such as verification of extremely high cleanliness state of the crystal growth chamber, availability of extremely high purity inert gas, and extremely strict control of impurities added to the polysilicon charge to be used.
Subsequently, at step 108, an HRS ingot having a target diameter (d) of 150 to 210mm (e.g., 150, 160, 170, 180, 190, or 200 mm) is pulled into the growth chamber as a first stage of production of wafer 230. The growing HRS ingot is cut and ground to produce a crystal orientation identifier 210 along one side of the HRS ingot, which is, for example, the principal plane when the diameter d of the HRS ingot is 150mm, or the notch when the diameter d is 200 mm.
The principal plane 210, which is used in these figures as an example of the identifier 210, is used as a standard identifier to identify the surface orientation of the 150mm silicon wafer 230. The surface orientation of the silicon wafer 230 needs to be exactly 111 or very close to it, or exactly 100 or very close to it, typically with a tolerance of at most 0.5 degrees. The principal plane 210 is an irregularity of the circular shape of the silicon wafer 230 that always causes a decrease in flatness during mechanical thinning steps (e.g., grinding and polishing steps 116, 122) typically used in wafer fabrication.
The method 100 compensates for the effects of the identifier 210 and enables a silicon wafer 230 (e.g., a 150mm diameter silicon wafer 230 (the specification of which typically requires a major plane 210 due to processing tool requirements for this wafer size), and a 200mm diameter silicon wafer 230) to have a higher flatness.
At step 112, HRS wafer 212 is sliced from the generated HRS ingot, such as by multi-wire slicing according to current industry standards. The dicing process applies mechanical forces to remove material and create subsurface lattice damage within and below the front (top) surface 209 of the diced wafer 212. Naturally, similar lattice damage is also incorporated into and below the back surface 211 of the diced wafer 212. The incorporated lattice damage creates a disordered lattice damage region 213 inside the front (top) side of the cut wafer 212 and another disordered lattice damage region (not shown in the figures) inside the back side of the cut wafer 212.
Each sliced wafer 212 includes monocrystalline silicon, a discriminator 210, and a first thickness h1, which is the distance between the front surface 209 and the back surface 211.
At step 114, the sliced wafer 212 may be thinned at least from its front side by grinding so as to at least partially remove slice-based crystal damage, i.e., disordered regions 213, and the ground wafer 212 may be cleaned.
Since the grinding process also mechanically incorporates some subsurface lattice damage into the cut wafer 212, the ground wafer 212 includes disordered regions 213. Alternatively, if the slice-based crystal damage is to be at least partially maintained in the ground wafer 212, it is possible to modify the grinding process so that at least a portion of the slice-based disordered region 213 remains, and thus the ground wafer 212 includes both slice-based and ground crystal damage.
Next, at step 114, the ground wafer 212 may be acid etched to at least partially remove the resulting crystal damage, and then the etched wafer 212 is visually inspected, cleaned, and treated by thermal donor annealing.
At step 116, the processed wafer 212 including the identifier 210 is attached to the chuck arrangement of the grinder and only its front surface 209 on the front side of the wafer 212 is exposed to a controlled single-sided fixed abrasive grinding performed by the rotating grinding wheel of the grinder.
Due to the fixed abrasive grinding process, the thickness of the wafer 218 is reduced from the first thickness h1 by about a distance h2 to a third thickness h3 such that its front surface 217 is at the distance h2 from the back surface of the wafer 218. In addition, the fixed abrasive grinding process again mechanically incorporates some subsurface lattice damage into and below the front surface 217 of the ground wafer 218 and creates disordered regions 213 (if not already present) in the interior of the front side of the ground wafer 218.
The effective, short control loop controlled fixed abrasive lapping process at least partially eliminates, in fact at least a majority (most, notably, substantially completely) of the effects of the asymmetric variation (non-circular asymmetry) caused at least in part by the identifier 210 from the front surface 217 of the lapped wafer 218, making it possible to obtain the desired Total Thickness Variation (TTV) on the wafer 218. The TTV defines the difference between the minimum (min, lowest) and maximum (max, highest) thickness of the wafers 218, 222, 230 according to fig. 2 a. The controlled fixed abrasive lapping process removes or at least minimizes the asymmetry variation caused by the identifier from becoming noticeable, thereby eliminating its effect on TTV.
At step 118, during the fixed abrasive grinding process, at least one grinding parameter is continuously monitored by at least one of optical measurement (apparatus, system) and capacitance measurement (apparatus, system) of the adjusted charge carriers, and continuously controlled.
For HRS wafers 212, 218, standard capacitance measurements cannot be reliably applied due to the lack of conductivity in the material to be measured. In addition, control over the achievable thickness accuracy is not sufficient. Thus, it is desirable to use optical measurements or capacitance measurements that enable higher accuracy or adjustment of charge carriers to meet the thickness variation requirements of the wafer 230 for use in the hybrid substrate structure 336.
When capacitance measurement is used, an effective electrostatic discharge (ESD) is incorporated into the measurement device. The cross-correlation of the optical measurement and the appropriately modified capacitance geometry measurement enhances the overall measurement system, as these techniques complement each other. The measurement system reliably gives accurate high resolution data of the entire wafer geometry, even for ultra-high resistivity silicon, thus achieving the effective, short feedback loop needed to obtain the required accurate geometry control. Significantly superior flatness capabilities, typically required for typical commercial tools having a TTV between 1 and 2 μm, are possible to achieve by the method 100, compared to the integrated and automated flatness control features that can be found in typical commercial tools for single side grinding of silicon wafers 212.
The polishing parameters include at least one of: the temperature of the cooling water of the chuck arrangement, the inclination of the grinding chuck of the chuck arrangement and the grinding feed rate of the grinding wheel.
At step 120, if the grinding parameters need to be adjusted due to a predetermined grinding schedule or due to a need to monitor, the grinding parameters are adjusted during the fixed abrasive grinding process to achieve the desired TTV.
For example, the tolerance of the cooling water temperature is within ±1 ℃ or better. The tilt of the polishing chuck between the wafer 212 and the polishing wheel is continuously monitored, e.g., 0.5 to 2 times per hour in continuous operation, and adjusted with a short feedback loop. The TTV introduced is in the range of 1 to 5. Mu.m. In order to obtain a high surface quality and to achieve a stable cutting efficiency of the grinding wheel, the grinding feed rate is in the range of 0.15 to 1 μm per second. In addition, the diamond size and type of grinding wheel is selected to achieve the best combination of yield, robustness and surface quality. The particle cleanliness of the incoming wafer 218 must be sufficient to prevent localized excess material removal.
At step 122, a single-sided lapped wafer 218 is attached to the wafer carrier of the polisher, and only its lapped front surface 217 on the front side of the wafer 218 is exposed to controlled polishing performed by the rotating polishing pad of the polisher.
Due to the polishing process, the thickness of the wafer 222 and its lattice-damaged region 213 decrease from the third thickness h3 by about the fourth distance h4 to the fifth thickness h5 such that its polishing front surface 222 is at the fourth distance h4 from the back surface of the wafer 222. In addition, the polishing process removes subsurface lattice damage below the front surface 221 of the polished wafer 218.
The polishing process completes the elimination of thickness variations of the polished wafer 222 so that the polished wafer 222 meets the desired TTV level.
The desired TTV of the wafer 222, 230 is less than 600nm, for example 200, 300, 400 or 500nm.
At step 124, during the polishing process, the adjusted current carrying capacitance measurements (devices, systems) and surface scanning devices (systems) are continuously monitored by a Makyoh mirror, optical measurement (device) or suitable geometry monitoring, and at least one polishing parameter is continuously controlled.
The polishing parameters include at least one of a polishing pressure of the wafer 222 and the polishing pad, a rotational speed of the wafer 222 and the polishing pad, and a position of the wafer 222 relative to the polishing pad.
At step 126, if the polishing parameters need to be adjusted due to a predetermined polishing schedule or due to a need for monitoring, the at least one polishing parameter is adjusted during the polishing process to achieve the required TTV to complete the thinning steps 116, 122, so that the thinned wafer 222 is ready for processing, which can create parasitic current suppression in the Radio Frequency (RF).
At step 128, the thinned wafer 222 is set into a deposition chamber of a deposition machine and at least one polysilicon layer 229 is deposited on its front surface 221 by a Chemical Vapor Deposition (CVD) process. The deposited polysilicon layer 229 comprises an extremely uniform polysilicon film having a total layer thickness h6.
Due to the deposition process, the thickness of the wafer 222 increases from the fifth thickness h5 by about a sixth distance h6 equal to the total layer thickness h6 to a seventh thickness h7 such that its front surface 223 is at said sixth distance h6 from the back surface of the wafer 222.
At step 130, the wafer 222 including the deposited polysilicon layer 229 is attached to a wafer carrier of a polisher suitable for chemical mechanical polishing, and only its deposited front surface 223 on the front side of the wafer 222 is exposed to controlled chemical mechanical polishing performed by the rotating polishing pad of the polisher.
Due to the chemical mechanical polishing process, the thickness of the wafer 230 is reduced from the seventh thickness h7 by about an eighth distance h8 to a tenth thickness h10, and the thickness of the deposited polysilicon layer 229 is reduced from the sixth thickness h6 by about the eighth distance h8 to a ninth thickness h9 such that the front surface 232 thereof is at the eighth distance h8 from the back surface of the wafer 230. In addition, the chemical mechanical polishing process provides a polysilicon layer 229 having a desired thickness h9 and a mirror polished front surface 232, which is suitable for fusion bonding the hybrid substrate structure 336 in a front end approach.
At step 134, the chemical mechanical polishing process is continuously monitored by measuring the polished wafer 230 using an optical wavelength range from Visible (VIS) to Near Infrared (NIR), with an optical measurement (device), such as interferometry, reflectometry, or ellipsometry, and continuously controlling at least one chemical mechanical polishing parameter.
The principle of operation of optical measurement is based on reflecting broadband light from the front surface 223 and polysilicon layer interface and calculating the layer thickness from the resulting spectrum. The reflected light shows a periodic interference spectrum based on layer thickness versus wavelength, and the thickness is calculated from the signal by using a theoretical model of the layer with a matching period. The polysilicon-monocrystalline silicon interface produces only weak reflection due to the small difference in refractive index of the polysilicon material and the monocrystalline silicon material. Although the absorbance in silicon is very high in the same wavelength region, there is still a modest difference in the visible part of the spectrum. The optimal spectral range is 600nm to 900nm.
The chemical mechanical polishing parameters include at least one of a rate of removal of material from the front surface 223 of the wafer 222 and a polishing time of the front surface 223 of the wafer 222.
At step 136, if the cmp parameters need to be adjusted due to a predetermined polishing schedule or due to a need arising from monitoring, the cmp parameters are adjusted during the cmp process in order to achieve the desired final layer thickness h9 of the polysilicon layer 229 and the polishing step 130 is completed, so that the processed wafer 230 is ready for fusion bonding with the active layer 334 according to fig. 3a to form the hybrid substrate structure 336 in the front-end method. Alternatively or additionally, other structures may be formed (processed) on the back surface of wafer 230 in a back-end-of-line approach (process).
The method 100 solves a critical problem of the geometry of the wafer 230, particularly its non-circularly symmetric variation, by utilizing a circularly symmetric fixed abrasive grinding process to remove a majority of the material during the wafer shape definition process. A double sided variant of this type of process is widely used to achieve very tight geometries when manufacturing wafers with a diameter of 300mm, but this is not possible for smaller wafer sizes associated with substrates bonded to monocrystalline silicon wafer 230.
For these wafer sizes, single-sided abrasive tools are commercially available, but typical processes are not capable of achieving the required geometric accuracy. The method 100 uses extremely precisely controlled single-sided lapping to produce extremely precisely defined geometries such that the TTV in the wafer 230 is typically at the level of 500nm. Importantly, this variation appears predominantly as a circularly symmetric shape due to the radial treatment, with asymmetric portions of the thickness variation as low as 200nm.
The invention has been explained above with reference to the foregoing exemplary embodiments, and several advantages of the invention have been demonstrated. It is clear that the invention is not limited to these embodiments only, but includes all possible embodiments within the scope of the appended claims.

Claims (17)

1. A method (100) of fabricating a high resistivity silicon handle wafer (230) capable of forming a hybrid substrate structure (336), the method comprising the steps of:
a wafer (212) is produced (108, 112, 114) having a crystal orientation identifier (210) and a specified thickness (h 1),
thinning (116, 122) the resulting wafer from the particular thickness to a desired thickness (h 5) of the wafer (222) to obtain a thinned wafer (222),
providing (128) a surface passivation layer (229) having a specific layer thickness (h 6) on the front surface (221) of the thinned wafer, and
polishing (130) the passivation layer from the particular layer thickness to a desired final layer thickness (h 9) of the passivation layer, enabling active layer bonding of a polished front surface (232) of the wafer (230) to form the hybrid substrate structure,
characterized in that the thinning step comprises controlled single-sided fixed abrasive lapping (116, 118, 120) of the resulting wafer (218) comprising a crystal orientation identifier with a chuck arrangement that eliminates at least a substantial portion of the effects of non-circular asymmetry caused by the identifier to produce the wafer (218, 222) with the desired sub-micron total thickness variation to enable formation of the hybrid substrate structure.
2. The method according to the preceding claim, wherein the controlled grinding step comprises continuous control (118) of at least one grinding parameter during the controlled grinding (116), and, if necessary, adjustment (120) of the at least one grinding parameter to achieve a desired overall thickness variation.
3. The method of claim 2, wherein the step of continuously controlling the at least one grinding parameter comprises controlling (118) at least one of a cooling water temperature of the chuck arrangement, a grinding chuck inclination of the chuck arrangement, and a grinding feed rate of a grinding wheel.
4. A method according to claim 2 or 3, wherein the step of continuously controlling the at least one polishing parameter comprises monitoring (118) the controlled polishing by optical measurement and/or capacitance measurement of the adjusted charge carriers.
5. The method of any of the preceding claims, wherein the thinning step further comprises controlled polishing (122, 124, 126) of the single-sided fixed abrasive lapped wafer (218) from a lapped front surface (217) of the single-sided fixed abrasive lapped wafer (218) so as to control a condition of the front surface of the wafer.
6. The method of claim 5, wherein the controlled polishing step comprises polishing (122, 124, 126) the single-sided fixed abrasive lapping handle wafer.
7. The method of claim 5 or 6, wherein the controlled polishing step comprises continuously controlling (124) at least one polishing parameter during the controlled polishing (122), and, if necessary, adjusting (126) the at least one polishing parameter to achieve a desired thickness of the wafer.
8. The method of any of claims 5 to 7, wherein the step of continuously controlling the at least one polishing parameter comprises controlling (124) at least one of a polishing pressure of the wafer (222) and a polishing pad, a rotational speed of the wafer and the polishing pad, and a position of the wafer relative to the polishing pad.
9. The method according to any one of claims 5 to 8, wherein the step of continuously controlling the at least one polishing parameter comprises monitoring (124) the controlled polishing by a Makyoh mirror, an optical measuring device or a capacitance measuring device and a surface scanning device for geometry monitoring, which adjusts the current carrying.
10. The method of any one of the preceding claims, wherein the wafer has a diameter (d) of 150 to 200mm, the surface of the handle wafer is oriented {111}, and the desired total thickness variation of the finished wafer is less than 600nm.
11. The method according to any of the preceding claims, wherein the step of producing the resulting surface passivation layer comprises depositing (128) at least one polysilicon layer (229) having the specific layer thickness (h 6) on the front surface (221) of the thinned wafer (222) by means of a chemical vapor deposition process.
12. The method of claim 11, wherein the step of polishing the surface passivation layer comprises controlled polishing (130) of at least one deposited polysilicon layer by means of a chemical mechanical polishing process from the specific layer thickness of the at least one deposited polysilicon layer to a desired final layer thickness (h 9) of the at least one deposited polysilicon layer on a fabricated wafer (222), thereby producing a chemical mechanical polished front surface (232) of the wafer (230).
13. The method of claim 12, wherein the controlled chemical mechanical polishing step comprises continuously controlling (132) at least one chemical mechanical polishing parameter during the controlled chemical mechanical polishing (130), and, if necessary, adjusting (134) the at least one chemical mechanical polishing parameter so as to achieve a desired final layer thickness.
14. The method of claim 13, wherein the step of continuously controlling the at least one chemical mechanical polishing parameter comprises controlling (132) a rate of removal from a front surface (223, 232) of the wafer and a polishing time of the front surface of the wafer.
15. The method according to claim 13 or 14, wherein the step of continuously controlling the at least one chemical mechanical polishing parameter comprises monitoring (134) the controlled chemical mechanical polishing by an optical measurement device using an optical wavelength range from the visible near infrared (VIS-NIR) range.
16. A high resistivity silicon handle wafer (230) capable of forming a hybrid substrate structure (336), the wafer being manufactured by the steps of the method (100) according to any one of the preceding claims, comprising
The crystal orientation identifier (210),
desired thickness (h 10), and
the polished surface passivation layer (229) having a desired final layer thickness (h 9) on the front surface (221) of the single-sided fixed abrasive lapping wafer having a desired sub-micron total thickness variation to create the polished front surface (232) capable of forming the hybrid substrate structure,
wherein at least a majority of the effect of the non-circular asymmetry caused by the identifier has been removed from the wafer.
17. A hybrid substrate structure (336) comprising the high resistivity silicon handle wafer (230) of claim 16.
CN202180069096.5A 2020-10-08 2021-10-08 Method of manufacturing high resistivity silicon handle wafer capable of forming hybrid substrate structure Pending CN116325084A (en)

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PCT/FI2021/050664 WO2022074297A1 (en) 2020-10-08 2021-10-08 Manufacture method of a high-resistivity silicon handle wafer for enabling a formation of a hybrid substrate structure

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Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69127582T2 (en) * 1990-05-18 1998-03-26 Fujitsu Ltd Method of manufacturing a semiconductor substrate and method of manufacturing a semiconductor device using this substrate
JP2000114216A (en) * 1998-10-01 2000-04-21 Sumitomo Metal Ind Ltd Manufacture of semiconductor wafer
FI130149B (en) * 2013-11-26 2023-03-15 Okmetic Oyj High-resistive silicon substrate with a reduced radio frequency loss for a radio-frequency integrated passive device

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