KR20230080428A - Manufacturing Method of High Resistance Silicon Handle Wafers to Enabling Formation of Hybrid Substrate Structures - Google Patents

Abstract

A method (100) of fabricating a high resistivity silicon handle wafer (230) to enable the formation of a hybrid substrate structure (336). The method includes the steps of producing a wafer 212 having a crystal orientation identifier 210, thinning the resulting wafer to obtain a thinned wafer 222, the front side 221 of the thinned wafer. ), and polishing the passivation layer to enable active layer bonding to the polished front side 232 of the wafer to form a hybrid substrate structure. The thinning step includes subjecting the resulting wafer 218 with crystal orientation identifiers to a controlled-side fixed abrasive grinding by means of a chuck arrangement, having a desired submicron total thickness variation to enable formation of a hybrid substrate structure. To fabricate the wafer, it removes at least most of the non-circular asymmetry effect caused by the identifier.

Description

Manufacturing Method of High Resistance Silicon Handle Wafers to Enabling Formation of Hybrid Substrate Structures

This application generally relates to a method of manufacturing a high resistivity silicon handle wafer, a high resistivity silicon handle wafer, and a hybrid substrate structure to enable the formation of a hybrid substrate structure.

Devices fabricated on hybrid wafers utilize an active layer that is bonded to and thinned to a monocrystalline silicon handle wafer. Handle Wafer is an advanced tool designed for standard silicon wafer processing, enabling reliable handling of hybrid materials, which provides mechanical stability and is compatible with the chemicals and cleanliness used in semiconductor manufacturing. One example of such devices are thin film surface acoustic wave (TF-SAW) filters, which are designed to use a thin active layer made of, for example, a piezoelectric material.

Hybrid wafer structures used in radio frequency (RF) operating devices of hundreds of MHz to tens of GHz are ultra-high resistivity, featuring an additional parasitic current suppression surface passivation layer to minimize the interaction of the handle wafer with the RF signal. (greater than 5000 Ω-cm) silicon substrates.

The performance of these devices for thinned active layers is greatly limited by their geometric accuracy. The final device geometry is defined by both the fabrication process of the device and the thickness control of the active layer in the substrate process. Since the accuracy of the device manufacturing process is defined using lithography, the accuracy achievable with state-of-the-art processes is very high. This increases the relative importance of the active layer thickness variation, since these dimensions cannot be controlled in the same way.

The geometry of the handle wafer has a significant effect on the geometry of the thinned active layer, typically resulting in approximately equal thickness variations in absolute terms (μm). Since the active layer is very thin compared to the handle wafer thickness, the proportional geometry variation becomes significantly higher. Accordingly, the flatness requirements for handle wafers are much greater than those of standard silicon substrates. According to SEMI M1, the total thickness variation (TTV) is defined as 10 μm for a 625 μm thick polished wafer with a 150 mm diameter.

TTV is particularly important when viewing non-circular symmetry across the wafer surface, since the additional rotational active layer thinning process can be relatively easily tuned in the radial direction, but modifying other shapes is much more complex.

The aforementioned drawbacks have significantly limited the performance of existing devices with thinned active layers.

It is an object of the present invention to eliminate the drawbacks of known solutions, to provide a high-resistance surface passivated substrate that compensates for the geometrical effect of the resulting crystal orientation identifier and enables higher flatness of 150-200 mm diameter silicon handle wafers. To provide a fabrication method for a silicon handle wafer. This fabricated silicon handle wafer is used in the formation of a hybrid substrate structure, and then the formed hybrid substrate structure can be used in device fabrication methods, such as front-end and back-end methods, to fabricate a semiconductor device (component). .

The object of the present invention is achieved by providing a manufacturing method according to the independent claims, a high resistance silicon handle wafer, and a hybrid substrate structure.

Embodiments of the present invention are embodied by a manufacturing method, a high resistivity silicon handle wafer, and a hybrid substrate structure according to the independent claims.

One method of fabricating a high resistivity silicon handle wafer to enable the formation of a hybrid substrate structure includes creating a wafer having a crystal orientation identifier and a specific thickness. The method further includes thinning the resulting wafer from a specified thickness to a desired thickness of the wafer to obtain a thinned wafer. The method further includes providing a surface passivation layer having a specific layer thickness on the front surface of the thinned wafer. The method further includes polishing the passivation layer from a specified layer thickness to a desired final layer thickness of the passivation layer such that the polished front side of the wafer enables active layer bonding (bonding of the active layer) to form a hybrid substrate structure. The step of thinning includes the step of subjecting the resulting wafer with crystal orientation identifiers to a controlled cross-section fixed abrasive grinding by means of a chuck arrangement to produce a wafer having a desired submicron total thickness deviation to enable formation of a hybrid substrate structure. To do so, at least most of the non-circular asymmetry effect caused by the identifier is removed.

One high resistivity silicon handle wafer for enabling the formation of a hybrid substrate structure is fabricated according to the steps of the previous method.

One hybrid substrate structure includes high resistivity silicon according to the previous handle wafer.

Exemplary embodiments of the present invention are described with reference to the following accompanying drawings.
1A-1B shows a flow diagram of a method of manufacturing a handle wafer.
2a-2b show how a handle wafer is processed during a fabrication method.
3A-3B show how an active layer is bonded and thinned to a fabricated handle wafer to form a hybrid substrate structure with a front-end fabrication method.

1A and 1B show a fabrication method 100 of a high-resistivity silicon (HRS) handle wafer 230 that is ready to be used (fabricated) for forming (manufacturing) a hybrid substrate structure 336. Next to the method steps, FIGS. 2A and 2B show how each method step affects the wafer 230 .

Fabrication of the wafer 230 is performed prior to formation of the hybrid substrate structure 336 and prior to a device fabrication step in which the formed hybrid substrate structure 336 is exposed to at least one device fabrication method (process). For example, the device fabrication method(s) including a front-end method (process) and a back-end method (fabrication) may be a hybrid substrate structure 336 for obtaining (manufacturing, processing) a semiconductor device (component). ) is about.

3A and 3B show a hybrid substrate structure 336, which is fabricated in a front-end method by using a processed wafer 230 as a handle wafer, and a piezoacoustic thin film surface acoustic wave (TF-SAW) filter or Other, for example, sapphire on silicon, III-IV hybrid substrate structures, or II-VI hybrid substrate structures, which are based on thinned material layers, can be used to fabricate. The hybrid substrate structure 336 utilizes a thin active layer 334, which is made of sapphire or a compound semiconductor material, fusion bonded according to FIG. 3A during the front end method and thinned to the wafer 230 according to FIG. 3B. do.

In step 108, a crystal puller suitable for either float zone (FZ) or magnetic Czochralski (MCz) silicon crystal growth is used in the crystal growth. Special fabrication required for ultra-low impurity crystal growth, eg verification of ultra-clean conditions of the crystal growth chamber, availability of ultra-high purity inert gas, and very tight removal of impurities added to the polysilicon charge to be used is performed.

Then, in step 108, an HRS ingot having a target diameter d of 150-210 mm, e.g., 150, 160, 170, 180, 190, or 200 mm, is a first generation step of wafer 230. As it is pulled up in the growth chamber. The grown HRS ingot is cut and ground to create a crystal orientation identifier 210, which is along the side of the ingot of the HRS, for example, when the diameter (d) of the HRS ingot is 150 mm, a basic flat portion. , or a notch when the diameter (d) is 200 mm.

The base flat portion 210 used as an example identifier 210 in these figures is used as a standard identifier to identify a surface orientation for a 150 mm silicon wafer 230. The surface orientation of the silicon wafer 230 is typically required to be exactly {111} or very close to exactly {111}, or exactly {100} or very close to it, by a maximum 0.5 degree tolerance. Basic flat portion 210 is an anomaly in the round shape of silicon wafer 230 that invariably causes a decrease in flatness in mechanical thinning steps commonly used in wafer fabrication, such as grinding and polishing steps 116 and 122. am.

Method 100 compensates for the effect of identifier 210, and for a silicon wafer 230, e.g., a 150 mm diameter silicon wafer 230 (the specification of which is typically the process tool requirements for this wafer size). requires basic planarization 210), and enables higher flatness for a 200 mm diameter silicon wafer 230.

In step 112, HRS wafers 212 are sliced from the resulting HRS ingot by, for example, multi-wire slicing according to current industry standards. The slicing process applies mechanical forces to remove material and causes subsurface crystal lattice damage in and under the front (top) 209 of the sliced wafer 212 . Of course, similar crystal lattice damage is also incorporated into and under the back surface 211 of the sliced wafers 212 . The crystal lattice damage incorporation results in an irregular lattice damage region 213 on the front surface (top surface) of the sliced wafers 212, and another irregular lattice damage region (not shown in the figure) within the back surface of the sliced wafers 212. ) causes

Each sliced wafer 212 includes single crystal silicon, an identifier 210, and a first thickness h1, which is the distance between the front and back surfaces 209, 211.

In step 114, the sliced wafer 212 may be thinned from at least its front surface by lapping to at least partially remove the crystal damage resulting from the slicing, i.e., the irregular region 213, the lapped wafer 212 may be cleaned.

The lapping process also mechanically incorporates some subsurface crystal lattice damage into sliced wafer 212 , so that wrapped wafer 212 includes irregular regions 213 . Alternatively, if crystal damage upon slicing is intended to be at least partially retained in the wrapped wafer 212, it is possible to modify the lapping process so that at least a portion of the irregular region 213 following slicing remains, The resulting lapped wafer 212 will contain crystal damage from slicing and lapping.

Then, at step 114, the lapped wafer 212 may be acid etched to at least partially remove the resulting crystal damage(s), and then the etched wafer 212 may be visually inspected. It is inspected, cleaned and processed by thermal donor annealing.

In step 116, the wafer 212 containing the machined identifier 210 is attached to the chuck arrangement of the grinder, and only the front surface 209 on the front surface of the wafer 212 is placed on the rotating grinding wheel of the grinder. A control section carried out by fixed abrasive grinding is exposed.

As a result of the fixed abrasive grinding process, the thickness of the wafer 218 decreases from the first thickness h1 to the third thickness h3 by about a distance h2 so that its front surface 217 is above the rear surface of the wafer 218. is approached by a distance h2 of The fixed abrasive grinding process also mechanically incorporates some subsurface crystal lattice damage into and back into and under the front surface 217 of the ground wafer 218, and irregular areas (if not present) within the front surface of the ground wafer 218. (213).

An effective and short control loop controlled stationary abrasive grinding process can achieve at least part of the effect of an asymmetry deviation (non-circular asymmetry) caused at least in part by the identifier 210 from the front side 217 of the ground wafer 218, in fact at least By quenching the majority (mostly, significantly, substantially completely), it becomes possible to obtain the desired total thickness variation (TTV) on the wafer 218 . TTV defines the difference between the minimum (lowest) and maximum (highest) thickness of wafers 218, 222, 230 according to FIG. 2A. The controlled fixed abrasive grinding process eliminates the asymmetry variations due to identifiers, or at least minimizes these asymmetry variations to a very small degree, eliminating their effect on the TTV.

At step 118, during the fixed abrasive grinding process, at least one grinding parameter is continuously monitored by at least one of an optical measurement (equipment, system) and a charge carrier steering capacitive measurement (equipment, system), and is continuously controlled. .

For HRS wafers 212 and 218, standard capacitive measurements cannot be reliably applied due to the lack of conductivity of the material being measured. Also, the control of achievable thickness accuracy is not sufficient. Accordingly, to meet the thickness variation requirements for the wafers 230 used in the hybrid substrate structure 336, the use of optical or charge carrier steering capacitive measurements enabling higher accuracy is required.

When using capacitive measurements, effective electrostatic discharging (ESD) is incorporated into the measurement equipment. The cross-correlation of optical and appropriately corrected capacitive geometry measurements enhances the measurement system as a whole because these techniques complement each other. A measurement system that reliably provides accurate, high-resolution data of the entire wafer geometry, even for ultra-high resistivity silicon, enables the effective short feedback loops needed to obtain the precise geometry control required. Method 100 is directed to integrated and automated flatness control features that can be found in typical off-the-shelf tools for face grinding of silicon wafers 212, which typically require 1-2 μm performance in TTV. It is possible to achieve an obviously superior flatness performance compared to

The grinding parameter(s) includes at least one of a cooling water temperature of the chuck arrangement, a grinding chuck inclination of the chuck arrangement, and a grinding feed rate of the grinding wheel.

In step 120, if it is necessary to adjust the grinding parameter(s) due to a need arising as a result of a predetermined grinding plan or monitoring, the grinding parameter(s) are adjusted during the fixed abrasive grinding process to achieve the desired TTV. do.

For example, the tolerance for coolant temperature is ±1°C or better. The inclination of the grinding chuck between the wafer 212 and the grinding wheel is constantly monitored and adjusted with a short feedback loop, for example 0.5 to 2 per hour in constant operation. The incoming TTV ranges from 1 to 5 μm. In order to obtain a high-quality surface and enable a stable cutting efficiency for the grinding wheel, the grinding feed rate is in the range of 0.15 to 1 μm per second. Also, the diamond size and type of grinding wheel are selected for the best combination of throughput, firmness, and surface quality. The particle cleanliness of the incoming wafers 218 should be sufficient to prevent localized excess material removal from occurring.

In step 122, the single side ground wafer 218 is attached to the wafer carrier of the polisher, and only its grinding front surface 217 on the front side of the wafer 218 is subject to the controlled polishing performed by the rotary polishing pad of the polisher. Exposed.

As a result of the polishing process, the thickness of the wafer 222 as well as its lattice damage region 213 are reduced from the third thickness h3 to the fifth thickness h5 by about a fourth distance h4, so that the polished The front surface 222 approaches the rear surface of the wafer 222 by a fourth distance h4. The polishing process also removes subsurface crystal lattice damage under the front surface 221 of the polished wafer 218 .

The polishing process completes the removal of thickness variations from the polished wafer 222 so that the polished wafer 222 meets the desired TTV level.

The desired TTV of wafers 222 and 230 is less than 600 nm, for example 200, 300, 400, or 500 nm.

In step 124, continuous monitoring is performed during the polishing process by Makoh mirrors, optical measurements (equipment) or geometry monitoring suitable carrier adjustment capacitive measurements (equipment, system), and surface scanning equipment (system). and at least one polishing parameter is continuously controlled.

The polishing parameter(s) includes at least one of a polishing pressure of the wafer 222 and the polishing pad, a rotation speed of the wafer 222 and the polishing pad, and a position of the wafer 222 relative to the polishing pad.

In step 126, if it is necessary to adjust the polishing parameter(s) due to a need arising as a result of a predetermined polishing plan or monitoring, the at least one polishing parameter achieves the desired TTV, so that thinning steps 116 , 122) so that the thinned wafer 222 is ready for processing to suppress parasitic current at radio frequencies (RF).

In step 128, the thinned wafer 222 is set into a deposition chamber of an evaporator, and at least one polysilicon layer 229 is deposited on the front surface 221 thereof by a chemical vapor deposition (CVD) process. The deposited polysilicon layer(s) 229 comprises a highly uniform polysilicon film having a total layer thickness h6.

As a result of the deposition process, the thickness of the wafer 222 increases from a first thickness h5 to a seventh thickness h7 by about a sixth distance h6 equal to the total layer thickness h6, so that its front surface 223 The rear surface of the wafer 222 is approached by the above distance h6.

In step 130, the wafer 222 including the deposited polysilicon layer(s) 229 is attached to the wafer carrier of a polisher suitable for chemical-mechanical polishing and its deposited polysilicon layer(s) 229 on the front side of the wafer 222. Only the front surface 223 is exposed to the controlled chemical-mechanical polishing performed by the rotary polishing pad of the polisher.

As a result of the chemical-mechanical polishing process, the thickness of the wafer 230 decreases from the seventh thickness h7 to the tenth thickness h10 by about an eighth distance h8, and the deposited polysilicon layer(s) ( 229) is reduced from the sixth thickness h6 to the ninth thickness h9 by the eighth distance h8, so that the front surface 232 is attached to the rear surface of the wafer 230 by the eighth distance ( h8). In addition, the chemical-mechanical polishing process takes the polysilicon layer(s) 229 to a desired thickness h9 and provides a mirror polished front surface 232, which is suitable for fusion bonding the hybrid substrate structure 336 in a shear method. Suitable.

At step 134, the chemical-mechanical polishing process takes the polished wafers 230 to optical measurements (instrumentation), e.g., using an optical wavelength range from the visible (VIS) to near infrared (NIR), It is continuously monitored and at least one chemical-mechanical polishing parameter is continuously controlled by measuring interferometry, reflectometry, or ellipsometry.

The operating principle of the optical measurement is based on reflecting broadband light from the front surface 223 and the interface of the polysilicon layer(s), and calculating the layer thickness from the resulting spectrum. The reflected light exhibits a periodic interference spectrum based on layer thickness versus wavelength, and the thickness is calculated from the signal by using a theoretical model for a layer with a matching period. The multi-monocrystalline silicon interface produces only weak reflections due to the small difference in refractive index of the poly and monocrystalline silicon materials. Moderate differences are still present in the visible part of the spectrum, but light absorption in silicon is high in the same wavelength region. The optimal spectral range found is between 600 nm and 900 nm.

The chemical-mechanical polishing parameter(s) includes at least one of a removal rate of material from the front side 223 of the wafer 222 and a polishing time of the front side 223 of the wafer 222 .

In step 136, if it is necessary to adjust the chemical-mechanical polishing parameter(s) due to a need arising as a result of the predetermined polishing plan or monitoring, the chemical-mechanical polishing parameter(s) are adjusted to the polysilicon layer(s). ) 229 and to complete the polishing step 130, the processed wafer 230 adjusts during the chemical-mechanical polishing process to form the hybrid substrate structure 336 in a front-end manner. to be ready for fusion bonding with the active layer 334 according to FIG. 3A to form. Alternatively or additionally, other structures may be formed (processed) on the back side of the wafer 230 in a back end method (process).

The method 100 addresses the very important geometry of the wafer 230, particularly its non-circular symmetry deviations, by performing most material removal of the wafer shape definition in a circularly symmetric fixed abrasive grinding process. A double-sided variant of this type of process is widely used to reach very tight geometries for fabricating 300 mm diameter wafers, but not possible for smaller wafer sizes involving substrates bonded to monocrystalline silicon wafer 230. not.

Although face grinding tools are commercially available for these wafer sizes, conventional processes cannot have the required geometrical accuracy. Method 100 uses very well-controlled single-sided grinding to fabricate very precisely defined geometries, typically producing TTV at the 500 nm level in wafer 230. Importantly, due to the radial processing, these deviations mainly appear as circularly symmetric shapes, and the asymmetric part of the thickness deviation is as low as 200 nm.

The invention has been described above with reference to the above-described illustrative embodiments, and several advantages of the invention have been demonstrated. It is clear that the present invention is not limited to these embodiments only, but includes all possible embodiments within the scope of the following claims.

Claims (17)

A method (100) of manufacturing a high resistivity silicon handle wafer (230) to enable the formation of a hybrid substrate structure (336), comprising:
producing (108, 112, 114) a wafer (212) having a crystal orientation identifier (210) and a specified thickness (h1);
Thinning (116, 122) the produced wafer from the specific thickness to a desired thickness h5 of the wafer 222 to obtain a thinned wafer 222;
providing (128) a surface passivation layer (229) having a specified layer thickness (h6) on the front side (221) of the thinned wafer; and
polishing the passivation layer from the specified layer thickness to a desired final layer thickness h9 of the passivation layer such that the polished front side 232 of the wafer 230 enables active layer bonding to form the hybrid substrate structure. comprising step 130;
The thinning step includes steps 116, 118, and 120 of controlling end-fixed polishing grinding of the generated wafer 218 including crystal orientation identifiers by means of a chuck arrangement to enable formation of the hybrid substrate structure. characterized by eliminating at least most of the non-circular asymmetry effect caused by the identifier to produce the wafer (218, 222) with a desired submicron total thickness variation. 2. The method of claim 1, wherein the step of controlled grinding comprises continuous control (118) of at least one grinding parameter during the control grinding (116), and, when necessary, the at least one grinding step, to achieve the desired total thickness deviation. A method comprising adjusting (120) a parameter. 3. The method of claim 2, wherein the step of continuously controlling the at least one grinding parameter comprises controlling (118) at least one of a coolant temperature of the chuck arrangement, a grinding chuck inclination of the chuck arrangement, and a grinding feed rate of a grinding wheel. Including, how. 4. The method according to claim 2 or 3, wherein the step of continuously controlling the at least one grinding parameter comprises monitoring (118) of the controlled grinding by means of optical measurements and/or charge carrier steering capacitive measurements. . 5. The method according to any one of claims 1 to 4, wherein the thinning step comprises control polishing the single-sided fixed abrasive grinding wafer (218) from its grinding front surface (217) to control the condition of the front surface of the wafer. (122, 124, 126). 6. The method of claim 5, wherein the step of controlled polishing includes polishing (122, 124, 126) the single-sided fixed abrasive ground handle wafer. 7. The method of claim 5 or 6, wherein the step of control polishing comprises continuous control (124) of at least one polishing parameter during the control polishing (122) to achieve the desired thickness of the wafer, and when necessary. , adjusting (126) the at least one polishing parameter. 8. The method of any one of claims 5 to 7, wherein the step of continuously controlling the at least one polishing parameter includes polishing pressure of the wafer (222) and the polishing pad, rotation speed of the wafer and the polishing pad, and control (124) of at least one of a position of a position relative to the polishing pad. 9. The method according to any one of claims 5 to 8, wherein the step of continuous control of the at least one polishing parameter comprises a Makoh mirror, a transport control capacitive or optical measurement instrument for monitoring the geometry, and monitoring (124) the controlled polishing by surface scanning equipment. 10. The method of any one of claims 1 to 9, wherein the diameter (d) of the wafer is 150-200 mm, the surface orientation of the handle wafer is {111}, and the desired total thickness variation of the finished wafer is is less than 600 nm. 11. The method according to any one of claims 1 to 10, wherein the step of generating the surface passivation layer is to form the specific layer thickness (h6) on the front surface (221) of the thinned wafer (222) by a chemical vapor deposition process. deposition (128) of at least one polysilicon layer (229) having 12. The method of claim 11, wherein the step of polishing the surface passivation layer comprises removing the at least one deposited polysilicon layer such that the front surface (232) of the wafer (230) is chemical-mechanically polished. controlled polishing (130) by a chemical-mechanical polishing process from a specified layer thickness of R to a desired final layer thickness (h9) of said at least one deposited polysilicon layer on said wafer (222) being produced. in, how. 13. The method of claim 12, wherein the step of chemical-mechanical control polishing comprises continuous control (132) of at least one chemical-mechanical polishing parameter during the chemical-mechanical control polishing (130) to achieve the desired final layer thickness. and, when necessary, adjusting (134) the at least one chemical-mechanical polishing parameter. 14. The method of claim 13, wherein the step of continuously controlling the at least one chemical-mechanical polishing parameter comprises controlling (132) a removal rate from the front side (223, 232) of the wafer and a polishing time of the front side of the wafer. in, how. 15. The method according to claim 13 or 14, wherein the step of continuous control of the at least one chemical-mechanical polishing parameter is performed by an optical measuring instrument using optical wavelengths in the visible to near-infrared (VIS-NIR) range. monitoring (134) the controlled chemical-mechanical polishing. A high resistivity silicon handle wafer (230) for enabling the formation of a hybrid substrate structure (336) produced by the steps of a method (100) according to any one of claims 1 to 15,
crystal orientation identifier 210;
the desired thickness (h10), and
Desired final layer thickness (h9) on the front surface (221) of a fixed abrasive ground wafer, cross-section having a desired submicron total thickness deviation to establish a polished front surface (232) to enable formation of the hybrid substrate structure. A polished surface passivation layer 229 having
wherein at least most of the non-circular asymmetry effect caused by the identifier has been removed from the wafer. A hybrid substrate structure (336) comprising a high resistivity silicon wafer (230) according to claim 16.

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