JP2000211997A - Production of epitaxial wafer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the occurrence of swelling of wafer surface and sagging of the peripheral part, to raise flatness of epitaxial wafer, to reduce the amount of wafer polished and to shorten a polishing time. SOLUTION: After lapping, a silicon wafer is immersed in a mixed acid solution of hydrofluoric acid and nitric acid. Then the surface of etched wafer is ground into 2-10 μm by using whetstone #2,000 [IF-01-1-4/6-B-M01] of Disuko K.K. The ground surface is polished into 2-8 μm and an epitaxial layer is subjected to epitaxial growth on the polished surface. Since the wafer surface is ground before polishing, the amount of the wafer surface polished is small and a polishing time is shortened. The flatness of a semiconductor wafer being a substrate of an epitaxial layer is raised. The wafer surface of high flatness can be obtained by grinding. The polished surface of the same quality as that of conventional polished surface can be obtained with the small polished amount.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing an epitaxial wafer, and more particularly, to lapping and etching a semiconductor wafer and then grinding and polishing the wafer surface.
By polishing and further epitaxial growth,
The present invention relates to a method for manufacturing an epitaxial wafer having a high flatness, a reduced polishing time, and an increased throughput.

[0002]

2. Description of the Related Art A conventional method of manufacturing an epitaxial wafer will be described with reference to a flowchart of FIG. First,
In the slicing step (S501), a silicon wafer is sliced from an ingot. Next chamfering step (S50
In 2), the outer peripheral portion of the silicon wafer is chamfered. In the subsequent lapping step (S503),
Lapping is performed on both sides of the silicon wafer by a lapping machine. Then, the next etching step (S50)
In 4), the wrapped wafer is immersed in a predetermined etching solution (mixed acid or alkali + mixed acid) to remove distortion in the lapping process, distortion in the chamfering step, and the like. In this case, usually, etching is performed to about 20 μm on one side and about 40 μm on both sides.

After that, a donor killer heat treatment step (S505) is performed on the silicon wafer. Subsequently, the silicon wafer is bonded to a polishing board using wax, and the wafer surface is mirror-polished (S506). And after removing the wax etc. attached to the back surface of the silicon wafer,
After the pre-cleaning (S507) of the epitaxial growth by the RCA cleaning, a silicon epitaxial layer having a predetermined thickness is formed on the surface of the silicon wafer by, for example, C
Epitaxial growth using VD method (S50
8). Then, post-cleaning is performed to remove dust scattered on the wafer surface, such as silicon dust adhering to the inner wall of the reaction furnace and components (S509). The RCA cleaning includes SC1 cleaning for removing particles on the wafer surface, HF cleaning for removing metal contaminants in the SiO ₂ film on the wafer surface, and re-cleaning on the wafer surface from which the oxide film has been removed by the HF cleaning. S to form oxide film with high cleanliness
Consisting of C2 cleaning. The mirror polishing may be performed without wax.

[0004]

However, in such a conventional method for manufacturing an epitaxial wafer, as described above, after lapping the silicon wafer, acid etching is performed using a mixed acid. As a result, the etching rate was relatively high, and at the time of acid etching, the silicon wafer and the acidic solution reacted strongly, generating a relatively large amount of bubbles. Due to these effects and the like, undulation with a height difference of about 0.2 to 5 μm easily occurs on the wafer surface (see FIG. 2 (a)), and sag occurs on the outer peripheral portion to reduce the flatness. There was a point. There is also a problem that the taper generated by lapping is further emphasized by etching. In addition, the undulation and sag affect the subsequent polishing step and epitaxial step. Further, for the tapered shape, a long polishing is required in the subsequent polishing step. The influence of the undulation on the surface of the wafer becomes remarkable when a circuit pattern or the like is exposed on the surface of the silicon wafer using an exposure apparatus in a device process on the user side after shipment. In other words, when exposing a fine circuit pattern that is becoming denser and more highly integrated with rapid progress, there has been a problem that an accurate pattern cannot be exposed on a distorted portion of the wafer.

[0005]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of manufacturing an epitaxial wafer capable of reducing the amount of polishing on the surface of a semiconductor wafer, achieving high flatness, reducing the polishing time, and increasing the throughput. That is the purpose.

[0006]

According to the first aspect of the present invention, there is provided a method of etching a lapped wafer which has been subjected to chamfering, and after etching, the surface of the semiconductor wafer is reduced in damage by using a resinoid bond grinding wheel. And a step of polishing the surface of the polished semiconductor wafer, and a step of epitaxially growing an epitaxial layer on the polished surface of the semiconductor wafer.

[0007] The resinoid bond grinding wheel is obtained by bonding diamond abrasive grains using a high quality synthetic resin as a binder. Grinding with this resinoid bonded grinding wheel
It is preferable to use a high-count grinding wheel capable of grinding the silicon surface, which is a hardly damaged wafer surface and which is a non-damaged surface. For example, # 1500 (particle size 4 to 8 μm)
m) to # 3000 (particle size: 2 to 6 μm) are preferred. Since the grinding is performed before the polishing, the amount of polishing is reduced, so that the throughput of the epitaxial wafer can be increased. In addition, the surface of the semiconductor wafer after the grinding has a high flatness. Thus, even when the polysilicon layer is grown after mirror polishing, for example, by a high-temperature CVD method, the surface of the relatively grown polysilicon layer can be made relatively smooth. Here, the high flatness of the surface of the semiconductor wafer means that the flatness of the site, for example, a site having an area of 25 mm × 25 mm is 0.4 μm or less in a height difference (SBIR) based on the back surface. I do. The grinding damage in this grinding is, for example, 2 μm or less. If the damage is large,
The polishing amount in the subsequent surface polishing step increases.

For epitaxial growth, a vapor phase method (Vap
or Phase Epitaxy), liquid phase method (Liq
uid Phase Epitaxy), solid phase method (So
(Lid Phase Epitaxy). In particular,
For epitaxial growth of silicon, the crystallinity of the growth layer,
In view of mass productivity, simplicity of equipment, ease of forming various device structures, and the like, chemical vapor deposition CVD is mainly employed. In the epitaxial growth of silicon by the CVD method, for example, a raw material gas containing silicon is introduced into a reaction furnace together with a carrier gas (usually H ₂ gas), and a silicon single crystal substrate (CZ) heated to a high temperature of 1000 ° C. or higher is used. The method is performed by depositing silicon generated by thermal decomposition or reduction of a raw material gas on the substrate. Although there are many compounds containing silicon, in consideration of purity, reaction rate, ease of handling, and the like, usually SiCl ₄ , SiHCl ₃ , SiH ₂ Cl
₂ , and four kinds of SiH ₄ are used.

The invention according to claim 2 is the method for producing an epitaxial wafer according to claim 1, wherein the grinding step is performed using a resinoid bonded grinding wheel # 1500 to # 3000 manufactured by Disco Corporation. As a resinoid bond grinding wheel manufactured by Disco Corporation, for example, a resinoid bond # 2000 high-count grinding wheel having a product name of “IF-01-1-4 / 6-B-M01” can be used.

[0010]

According to the method of manufacturing an epitaxial wafer of the present invention, both the front and back surfaces of a chamfered semiconductor wafer are wrapped. Next, the semiconductor wafer is etched. As a result, defects previously generated on the wafer surface are removed. The surface of the etched wafer subjected to the etching is subjected to grinding using a resinoid bond grinding wheel. Thereafter, the ground surface is polished, and then an epitaxial layer is epitaxially grown on the polished surface of the wafer, thereby manufacturing an epitaxial wafer. Since the wafer surface is ground before polishing, the amount of polishing is reduced, the polishing time is reduced, and the throughput of the epitaxial wafer is increased. Moreover, the flatness of the semiconductor wafer, which is the substrate of the epitaxial layer, also increases.
This is because a high flatness wafer surface can be obtained by grinding, so that a small polishing amount (10 to 15 μ
m) means that a polished surface of the same quality as the conventional one can be obtained.

According to the second aspect of the present invention, the grinding of the surface of the semiconductor wafer is performed by using #
This is performed using a resinoid bonded grinding wheel of No. 1500 to # 3000. This grinding wheel is a high-count resinoid bonded grinding wheel capable of grinding the silicon surface, which is an undamaged surface. Therefore, the wafer surface which has been etched and has no damage can be ground with this high-count grinding wheel with little damage (for example, a damage depth of about 2 μm) and without surface damage. In addition, grinding can be performed at a higher throughput as compared with electrolytic dress grinding. In addition, as is clear from the graph showing the damage depth of the wafer surface after grinding in FIG. 3, the defects remaining on the surface of the semiconductor wafer after grinding in the present invention usually polish the wafer surface by about 2 μm during the polishing step. As a result, it can be almost completely removed. This polishing can also be performed by a waxless method.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a flowchart showing a method for manufacturing an epitaxial wafer according to the first embodiment of the present invention. As shown in FIG. 1, in the first embodiment, generally, slicing, chamfering, lapping, etching, light polishing of the back surface as necessary, cleaning, grinding,
Through the respective steps of polishing, epitaxial pre-processing cleaning, epitaxial growth, and epitaxial post-processing cleaning, an epitaxial wafer is manufactured with high throughput. Hereinafter, each step will be described in detail.

The silicon ingot pulled up by the CZ method has a thickness of 860 μm in the slicing step (S101).
It is sliced into an 8-inch silicon wafer of about m. Next, this sliced wafer is subjected to a chamfering step (S
In 102), the periphery is chamfered to a predetermined shape using a chamfering grindstone. As a result, the peripheral portion of the silicon wafer is formed into a predetermined rounded shape (for example, a MOS type chamfered shape). In addition, the grinding wheel for chamfering employ | adopts the thing of metal bond # 600- # 1500. Next, the chamfered silicon wafer is wrapped in a lapping step (S103). In this lapping step, the silicon wafer is placed between lap plates kept parallel to each other, and a lap liquid, which is a mixture of alumina abrasive grains, a dispersant, and water, is placed between the lap plate and the silicon wafer. Pour in. Then, by rotating and sliding under pressure, both sides of the wafer are mechanically wrapped. The lap amount of the silicon wafer is about 40 to 80 μm including the front and back surfaces of the wafer.

Thereafter, the wrapped wafer is etched (S104). Specifically, the silicon wafer is immersed in a mixed acid solution (normal temperature to 50 ° C.) in which hydrofluoric acid and nitric acid are mixed. By etching with this mixed acid solution, usually,
An undulation having a height difference of about 12 μm occurs on the surface of the silicon wafer (see FIG. 2A). The next light polishing step (S105) of the back surface of the wafer is performed as necessary. This step is a step of slightly polishing the back surface of the wafer. That is, the back surface of the silicon wafer has a particle size of 0.3.
Polishing is performed to about 0.1 μm using free abrasive grains of about 05 μm. As a result, the surface roughness of the wafer surface is further increased. The light polishing step (S105) of the back surface of the wafer is performed by a grinding step (S10) of the front surface of the wafer.
It may be performed after 8).

Next, a cleaning step (S106) of cleaning the silicon wafer with an RCA-based cleaning liquid is performed. Then, a known donor killer heat treatment is performed on the silicon wafer (S107). Then, the surface of the silicon wafer,
Grinding is performed using a resinoid bond grinding wheel manufactured by Disco Corporation, product name "IF-01-1-4 / 6-B-M01" (S108). This grinding wheel is a special grinding wheel developed to process a high-count and undamaged surface of # 2000. The product name of this grinding device is "DFG8
40 ". The grinding amount at this time is 2 to 10 μm.
m. As a result, the polishing amount is 2 to 8 μm at the time of polishing, which is a post-process. Specifically, when the silicon wafer has a thickness of 740 μm, it is ground to about 10 μm. As described above, since the grinding is performed with a grinding wheel having a high number, damage to the wafer is reduced (less than 2 μm).
In addition, the wafer can be ground without exposing the wafer surface (see FIG. 2B).

Next, the surface of the silicon wafer that has been ground with low damage is further polished (S109). The polishing amount is sufficient at 2 to 8 μm in order to remove the damage in the grinding step of S108. Here, it is 3 μm (see also FIG. 2B). As a result, when a silicon wafer having a high flatness surface is further polished, it is possible to avoid a problem that the flatness is reduced when the polishing amount exceeds about 10 μm. Since the wafer surface is ground before polishing, the polishing time can be shortened and the throughput of the epitaxial wafer can be increased.

Thereafter, a pretreatment cleaning step (S110) for epitaxial growth is performed. Specifically, RCA cleaning is performed. Then, an epitaxial layer is grown on the surface of the highly planarized silicon wafer (S111).
That is, trichlorosilane, which is a source gas containing silicon, is introduced into a reaction furnace together with H ₂ gas, which is a carrier gas, and the pressure is set to 100 ± 20 KPa, and
On the silicon wafer heated to a high temperature of 270 ° C., silicon generated by thermal decomposition or reduction of a source gas is deposited at a reaction rate of 2.5 to 5.5 μm / min. Then, a post-processing cleaning step of epitaxial growth (S11
Perform 2). Specifically, the pretreatment cleaning step (S110)
This is the same as the RCA-based cleaning.

FIG. 4 is a graph showing the throughput of the epitaxial wafer according to this embodiment in comparison with the case of the conventional example (the manufacturing method of FIG. 5). This shows that the throughput of the epitaxial wafer according to this example is improved about four times as compared with that of the conventional example.

[0019]

According to the present invention, in the manufacture of an epitaxial wafer, low-damage grinding is performed before polishing the surface of an etched wafer, so that the polishing amount is reduced and the polishing time is reduced. Thus, the throughput of the epitaxial wafer can be increased.

According to the second aspect of the present invention,
In addition to the effect of claim 1, # 15 manufactured by Disco Corporation
Using resinoid bond grinding wheel of 00 ~ # 3000,
Since the flat surface of the semiconductor wafer is ground, the grinding can be performed at a high throughput without exposing the wafer surface.

[Brief description of the drawings]

FIG. 1 is a flowchart showing a method for manufacturing an epitaxial wafer according to one embodiment of the present invention.

FIG. 2A is an explanatory view showing a state of a wafer surface after etching. (B) It is explanatory drawing which shows the state of the wafer surface after grinding.

FIG. 3 is a graph showing the depth of damage on the wafer surface after grinding according to the present invention.

FIG. 4 is a graph showing a throughput of an epitaxial wafer manufactured by a manufacturing method according to an embodiment of the present invention in comparison with a conventional example.

FIG. 5 is a flowchart showing a conventional method for manufacturing an epitaxial wafer.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Toshiro Kawamoto 1-5-1, Otemachi, Chiyoda-ku, Tokyo Within Mitsui Material Silicon Co., Ltd. (72) Inventor Etsuro Morita 1-5, Otemachi, Chiyoda-ku, Tokyo No. 1 Mitsubishi Materials Silicon Corporation F-term (reference) 4G077 AA02 AA03 BA04 DB05 FG07 FG12 TB03 5F045 AA03 AB02 AC01 AC03 AC05 AD16 AE21 AE23 AF03 BB08 GH02 HA04

Claims (2)

[Claims] 1. A step of etching a chamfered wrapped wafer; a step of grinding the surface of the semiconductor wafer using a resinoid bond grinding wheel after the etching; and a step of polishing the ground surface of the semiconductor wafer. A method of manufacturing an epitaxial wafer, comprising: a step; and a step of epitaxially growing an epitaxial layer on a polished surface of the semiconductor wafer. 2. The method of manufacturing an epitaxial wafer according to claim 1, wherein the grinding step is performed using a resinoid bonded grinding wheel # 1500 to # 3000 manufactured by Disco Corporation.