DE69124750D1 - Verfahren zur Herstellung eines Silizium Wafer mit einer Chip-Trennstruktur und Einkristallschichtabschnitten - Google Patents

Verfahren zur Herstellung eines Silizium Wafer mit einer Chip-Trennstruktur und Einkristallschichtabschnitten

Info

Publication number
DE69124750D1
DE69124750D1 DE69124750T DE69124750T DE69124750D1 DE 69124750 D1 DE69124750 D1 DE 69124750D1 DE 69124750 T DE69124750 T DE 69124750T DE 69124750 T DE69124750 T DE 69124750T DE 69124750 D1 DE69124750 D1 DE 69124750D1
Authority
DE
Germany
Prior art keywords
producing
single crystal
crystal layer
silicon wafer
separation structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69124750T
Other languages
English (en)
Other versions
DE69124750T2 (de
Inventor
Yuichi Saito
Kenichi Kawai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Materials Silicon Corp
Mitsubishi Materials Corp
Original Assignee
Mitsubishi Materials Silicon Corp
Mitsubishi Materials Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Materials Silicon Corp, Mitsubishi Materials Corp filed Critical Mitsubishi Materials Silicon Corp
Application granted granted Critical
Publication of DE69124750D1 publication Critical patent/DE69124750D1/de
Publication of DE69124750T2 publication Critical patent/DE69124750T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76297—Dielectric isolation using EPIC techniques, i.e. epitaxial passivated integrated circuit
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76275—Vertical isolation by bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76286—Lateral isolation by refilling of trenches with polycristalline material

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Element Separation (AREA)
  • Recrystallisation Techniques (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
DE69124750T 1990-04-24 1991-04-22 Verfahren zur Herstellung eines Silizium Wafer mit einer Chip-Trennstruktur und Einkristallschichtabschnitten Expired - Lifetime DE69124750T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2108300A JPH046875A (ja) 1990-04-24 1990-04-24 シリコンウェーハ

Publications (2)

Publication Number Publication Date
DE69124750D1 true DE69124750D1 (de) 1997-04-03
DE69124750T2 DE69124750T2 (de) 1997-07-10

Family

ID=14481197

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69124750T Expired - Lifetime DE69124750T2 (de) 1990-04-24 1991-04-22 Verfahren zur Herstellung eines Silizium Wafer mit einer Chip-Trennstruktur und Einkristallschichtabschnitten

Country Status (5)

Country Link
US (1) US5804495A (de)
EP (1) EP0455087B1 (de)
JP (1) JPH046875A (de)
KR (1) KR970007397B1 (de)
DE (1) DE69124750T2 (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0136530B1 (ko) * 1994-07-11 1998-09-15 문정환 반도체장치 및 그 제조방법
US6083811A (en) * 1996-02-07 2000-07-04 Northrop Grumman Corporation Method for producing thin dice from fragile materials
US6317358B1 (en) 2000-08-03 2001-11-13 Micron Technology, Inc. Efficient dual port DRAM cell using SOI technology
JP3788268B2 (ja) * 2001-05-14 2006-06-21 ソニー株式会社 半導体装置の製造方法
US6844236B2 (en) * 2001-07-23 2005-01-18 Agere Systems Inc. Method and structure for DC and RF shielding of integrated circuits
JP3808763B2 (ja) * 2001-12-14 2006-08-16 株式会社東芝 半導体メモリ装置およびその製造方法
KR100442619B1 (ko) * 2002-01-11 2004-08-02 삼성전자주식회사 랩핑 및 폴리싱 공정을 위한 홈을 구비하는 웨이퍼
US6784071B2 (en) * 2003-01-31 2004-08-31 Taiwan Semiconductor Manufacturing Company, Ltd. Bonded SOI wafer with <100> device layer and <110> substrate for performance improvement
JP4556158B2 (ja) * 2002-10-22 2010-10-06 株式会社Ｓｕｍｃｏ 貼り合わせｓｏｉ基板の製造方法および半導体装置
WO2008123116A1 (en) 2007-03-26 2008-10-16 Semiconductor Energy Laboratory Co., Ltd. Soi substrate and method for manufacturing soi substrate

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3393349A (en) * 1964-04-30 1968-07-16 Motorola Inc Intergrated circuits having isolated islands with a plurality of semiconductor devices in each island
US3797102A (en) * 1964-04-30 1974-03-19 Motorola Inc Method of making semiconductor devices
JPS5329551B2 (de) * 1974-08-19 1978-08-22
GB2100508A (en) * 1981-06-17 1982-12-22 Marconi Electronic Devices Method of making semiconductor devices
JPS5957450A (ja) * 1982-09-27 1984-04-03 Nec Corp 半導体装置の素子分離方法
JPS5980940A (ja) * 1982-11-01 1984-05-10 Oki Electric Ind Co Ltd 絶縁物分離基板の製造方法
JPS59104139A (ja) * 1982-12-06 1984-06-15 Nec Corp 半導体集積回路装置
KR850004178A (ko) * 1983-11-30 1985-07-01 야마모도 다꾸마 유전체 분리형 집적회로 장치의 제조방법
JPS6190443A (ja) * 1984-10-09 1986-05-08 Sony Corp 半導体ウエハのダイシング方法
JPH0783050B2 (ja) * 1985-06-21 1995-09-06 株式会社東芝 半導体素子の製造方法
JPS63108706A (ja) * 1986-10-27 1988-05-13 Toshiba Corp 半導体装置の製造方法
FR2605828A1 (fr) * 1986-10-28 1988-04-29 Univ Metz Element de compensation de contraintes d'origine thermique ou mecanique, notamment pour circuit imprime, et procede de fabrication d'un tel element mis en oeuvre dans un circuit imprime
US4851078A (en) * 1987-06-29 1989-07-25 Harris Corporation Dielectric isolation process using double wafer bonding
JPH01185935A (ja) * 1988-01-21 1989-07-25 Toshiba Corp 半導体装置の製造方法
JPH0228925A (ja) * 1988-07-19 1990-01-31 Japan Silicon Co Ltd ウェーハの製造方法
DE68920365T2 (de) * 1988-06-28 1995-06-08 Mitsubishi Material Silicon Verfahren zur Polierung eines Halbleiter-Plättchens.
JPH0245953A (ja) * 1988-08-08 1990-02-15 Nissan Motor Co Ltd 半導体基板の製造方法及びその構造
US5051378A (en) * 1988-11-09 1991-09-24 Sony Corporation Method of thinning a semiconductor wafer
US5091330A (en) * 1990-12-28 1992-02-25 Motorola, Inc. Method of fabricating a dielectric isolated area
JP3033655B2 (ja) * 1993-09-28 2000-04-17 日本電気株式会社 半導体装置及び半導体装置の製造方法

Also Published As

Publication number Publication date
EP0455087B1 (de) 1997-02-26
KR970007397B1 (ko) 1997-05-08
DE69124750T2 (de) 1997-07-10
KR910019152A (ko) 1991-11-30
JPH046875A (ja) 1992-01-10
EP0455087A1 (de) 1991-11-06
US5804495A (en) 1998-09-08

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