KR850004178A - 유전체 분리형 집적회로 장치의 제조방법 - Google Patents

유전체 분리형 집적회로 장치의 제조방법 Download PDF

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Publication number
KR850004178A
KR850004178A KR1019840006766A KR840006766A KR850004178A KR 850004178 A KR850004178 A KR 850004178A KR 1019840006766 A KR1019840006766 A KR 1019840006766A KR 840006766 A KR840006766 A KR 840006766A KR 850004178 A KR850004178 A KR 850004178A
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KR
South Korea
Prior art keywords
region
integrated circuit
substrate surface
circuit device
original
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KR1019840006766A
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English (en)
Inventor
다모쓰 이시가와 (외 2)
Original Assignee
야마모도 다꾸마
후지쑤 가부시끼 가이샤
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Priority claimed from JP58227263A external-priority patent/JPS60117752A/ja
Priority claimed from JP22726283A external-priority patent/JPS60117751A/ja
Application filed by 야마모도 다꾸마, 후지쑤 가부시끼 가이샤 filed Critical 야마모도 다꾸마
Publication of KR850004178A publication Critical patent/KR850004178A/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76297—Dielectric isolation using EPIC techniques, i.e. epitaxial passivated integrated circuit
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/026—Deposition thru hole in mask
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/085—Isolated-integrated
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/122—Polycrystalline
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/969—Simultaneous formation of monocrystalline and polycrystalline regions
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/977—Thinning or removal of substrate

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Element Separation (AREA)

Abstract

내용 없음

Description

유전체 분리형 집적회로 장치의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 본 발명에 대한 DI(Dielectric Isolation) 웨이퍼의 부분적으로 단면을 포함하며, 그 구조를 도시하는 사시도.
제3도는 단결정 기판을 덮는 질화실리콘층과 이산화실리콘층을 형성한 후의 DI웨이퍼의 횡단면도.
제4도는 분리 모우트(MOAT)를 형성한 후의 DI 웨이퍼의 횡단면도.
제5도는 본래의 단결정 실리콘층에 강하게 도핑된 영역을 형성한 후의 DI 웨이퍼의 횡단면도.

Claims (5)

  1. 한 가지 형으로 도핑된 본래의 단결성 실리콘 기판을 준비하며, 상기 본래의 기판 표면위에 분리 모우트(MOAT)를 만들고, 상기 본래의 기판 표면의 첫번째 부분에 유전체 분리층을 형성시키며, 상기 첫번째 부분을 전기 회로의 소자가 형성되어 지는 영역이고, 상기 첫번째 부분을 제외한 상기 본래의 기판 표면 위의 두번째 부분을 노출시키며 상기 본래의 기판 표면의 모든 부분위에 실리콘 층을 성장시키므로, 성장된 실리콘 기판이 상기 두번째 부분위에 단 결정부분과 상기 첫번째 부분위에 폴리실리콘 부분을 형성시키는 공정으로 이루어진 유전체 분리형(DI) 집적회로장치의 제조방법.
  2. 청구범위 제1항에 있어서, 상기 두번째 영역이 상기 웨이퍼의 구획 영역위에 존재하는 유전체 분리형(DI) 집적회로장치의 제조방법.
  3. 청구범위 제1항에 있어서, 상기 두번째 영역이 상기 웨이퍼의 주변 영역에 존재하는 유전체 분리형(DI) 집적회로장치의 제조방법.
  4. 청구범위 제1항에 있어서, 상기 두번째 영역이 상기 실리콘기판에 접촉하는 영역에 존재하는 유전체 분리형(DI) 집적회로장치의 제조방법.
  5. 청구범위 제1항에 있어서, 상기 유전체 분리층이 이산화실리콘(SiO2)층인 유전체 분리형(DI) 집적회로장치의 장치제조방법
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019840006766A 1983-11-30 1984-10-30 유전체 분리형 집적회로 장치의 제조방법 KR850004178A (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP58227263A JPS60117752A (ja) 1983-11-30 1983-11-30 半導体集積回路装置の製造法
JP??58????227263 1983-11-30
JP??58????227262 1983-11-30
JP22726283A JPS60117751A (ja) 1983-11-30 1983-11-30 半導体集積回路装置の製造法

Publications (1)

Publication Number Publication Date
KR850004178A true KR850004178A (ko) 1985-07-01

Family

ID=26527583

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019840006766A KR850004178A (ko) 1983-11-30 1984-10-30 유전체 분리형 집적회로 장치의 제조방법

Country Status (4)

Country Link
US (1) US4567646A (ko)
EP (1) EP0145573B1 (ko)
KR (1) KR850004178A (ko)
DE (1) DE3484733D1 (ko)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01185935A (ja) * 1988-01-21 1989-07-25 Toshiba Corp 半導体装置の製造方法
JP2645478B2 (ja) * 1988-10-07 1997-08-25 富士通株式会社 半導体装置の製造方法
US4925808A (en) * 1989-03-24 1990-05-15 Sprague Electric Company Method for making IC die with dielectric isolation
JPH046875A (ja) * 1990-04-24 1992-01-10 Mitsubishi Materials Corp シリコンウェーハ
JPH07118505B2 (ja) * 1990-12-28 1995-12-18 信越半導体株式会社 誘電体分離基板の製造方法
US5744851A (en) * 1992-01-27 1998-04-28 Harris Corporation Biasing of island-surrounding material to suppress reduction of breakdown voltage due to field plate acting on buried layer/island junction between high and low impurity concentration regions
US5841169A (en) * 1996-06-27 1998-11-24 Harris Corporation Integrated circuit containing devices dielectrically isolated and junction isolated from a substrate
JP3137051B2 (ja) * 1997-10-08 2001-02-19 日本電気株式会社 半導体装置およびその製造方法
US6075280A (en) * 1997-12-31 2000-06-13 Winbond Electronics Corporation Precision breaking of semiconductor wafer into chips by applying an etch process
US6492684B2 (en) 1998-01-20 2002-12-10 International Business Machines Corporation Silicon-on-insulator chip having an isolation barrier for reliability
US6133610A (en) 1998-01-20 2000-10-17 International Business Machines Corporation Silicon-on-insulator chip having an isolation barrier for reliability and process of manufacture
US6465353B1 (en) * 2000-09-29 2002-10-15 International Rectifier Corporation Process of thinning and blunting semiconductor wafer edge and resulting wafer

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3829889A (en) * 1963-12-16 1974-08-13 Signetics Corp Semiconductor structure
US3423823A (en) * 1965-10-18 1969-01-28 Hewlett Packard Co Method for making thin diaphragms
US3440498A (en) * 1966-03-14 1969-04-22 Nat Semiconductor Corp Contacts for insulation isolated semiconductor integrated circuitry
US3471922A (en) * 1966-06-02 1969-10-14 Raytheon Co Monolithic integrated circuitry with dielectric isolated functional regions
US3607466A (en) * 1967-11-22 1971-09-21 Sony Corp Method of making semiconductor wafer
JPS5120267B2 (ko) * 1972-05-13 1976-06-23
US3956034A (en) * 1973-07-19 1976-05-11 Harris Corporation Isolated photodiode array
DE2451861A1 (de) * 1973-11-02 1975-05-15 Hitachi Ltd Integrierte halbleiterschaltungsbauelemente
US3911559A (en) * 1973-12-10 1975-10-14 Texas Instruments Inc Method of dielectric isolation to provide backside collector contact and scribing yield
JPS5951743B2 (ja) * 1978-11-08 1984-12-15 株式会社日立製作所 半導体集積装置
JPS5918654A (ja) * 1982-07-22 1984-01-31 Nec Corp 誘電体分離基板の製造方法
JPS59104139A (ja) * 1982-12-06 1984-06-15 Nec Corp 半導体集積回路装置

Also Published As

Publication number Publication date
EP0145573A2 (en) 1985-06-19
EP0145573A3 (en) 1987-11-25
US4567646A (en) 1986-02-04
EP0145573B1 (en) 1991-06-19
DE3484733D1 (de) 1991-07-25

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