KR910016061A - 반도체장치 및 그 제조방법 - Google Patents

반도체장치 및 그 제조방법 Download PDF

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Publication number
KR910016061A
KR910016061A KR1019910002124A KR910002124A KR910016061A KR 910016061 A KR910016061 A KR 910016061A KR 1019910002124 A KR1019910002124 A KR 1019910002124A KR 910002124 A KR910002124 A KR 910002124A KR 910016061 A KR910016061 A KR 910016061A
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KR
South Korea
Prior art keywords
trench
region
oxide film
semiconductor device
exceeding
Prior art date
Application number
KR1019910002124A
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English (en)
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KR940003217B1 (ko
Inventor
나오토 미야시타
고이치 다카하시
히로노리 소노베
미츠토시 고야마
Original Assignee
아오이 죠오치
가부시키가이샤 도시바
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication of KR910016061A publication Critical patent/KR910016061A/ko
Application granted granted Critical
Publication of KR940003217B1 publication Critical patent/KR940003217B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/782—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, each consisting of a single circuit element
    • H01L21/784—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, each consisting of a single circuit element the substrate being a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H01L21/76235—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls trench shape altered by a local oxidation of silicon process step, e.g. trench corner rounding by LOCOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76286—Lateral isolation by refilling of trenches with polycristalline material

Abstract

내용 없음

Description

반도체장치 및 그 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 1실시예에 따른 반도체장치를 설명하기 위한 사시도, 제2도는 본 발명의 1실시예에 따른 반도체장치의 제조방법을 설명하기 위한 단면도.

Claims (3)

  1. 하나의 소자영역(14a,26a,…)을 도랑으로 에워싸도록 함으로써 이에 인접하는 다른 소자영역(14b,26b,…)과의 전기적인분리를 행한 반도체 장치에 있어서, 상기 하나의 소자영역(14a,26a,…)을 에워싸는 도랑과 다른 소자영역을 에워싸는 도랑의 간격이 적어도 3㎛를 넘도록 된 것을 특징으로 하는 반도체 장치.
  2. 제1항에 있어서, 상기 하나 및 다른 소자영역(14a,26a,…14b,26b,…)을 에워싸는 각각의 도랑내에는 두께가 9000Å를 넘지않는 산화막(17,30)이 형성되어 있는 것을 특징으로 하는 반도체장치.
  3. 도랑에 의한 소자분리방법에 있어서, 반도체기판(11,21,41)에 하나의 소자영역(14a,26a)을 에워싸면서 인접하는 다른 소자영역(14b,26b)을 에워싸는 도랑(15b,25b,44b)과의 간격이 3㎛를 넘도록 하여 도랑을 형성하는 공정과, 상기 하나의 소자영역(14a,26a) 및 다른 소자영역(14b,26b)을 에워싸는 각각의 도랑 내에 두께가 9000Å를 넘지 않는 제1산화막(17,30,45)을 형성하는 공정, 상기 제1산화막(17,30,45)이 형성된 도랑내에 다결정실리콘(18,46)을 매립하는 공정 및 상기 다결정실리콘(18,46)이 매립된 각각의 도랑상에 제2산화막(19,47)을 형성하는 공정을 구비하여 이루어진 것을 특징으로 하는 반도체장치의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019910002124A 1990-02-09 1991-02-08 반도체장치 및 그 제조방법 KR940003217B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP02-030584 1990-02-09
JP02-30584 1990-02-09
JP2030584A JPH0736419B2 (ja) 1990-02-09 1990-02-09 半導体装置及びその製造方法

Publications (2)

Publication Number Publication Date
KR910016061A true KR910016061A (ko) 1991-09-30
KR940003217B1 KR940003217B1 (ko) 1994-04-16

Family

ID=12307908

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910002124A KR940003217B1 (ko) 1990-02-09 1991-02-08 반도체장치 및 그 제조방법

Country Status (5)

Country Link
US (1) US5111272A (ko)
EP (1) EP0451454B1 (ko)
JP (1) JPH0736419B2 (ko)
KR (1) KR940003217B1 (ko)
DE (1) DE69133009T2 (ko)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04107949A (ja) * 1990-08-28 1992-04-09 Mitsubishi Electric Corp 半導体装置及びその製造方法
EP0608999B1 (en) * 1993-01-29 1997-03-26 National Semiconductor Corporation Bipolar transistors and methods for fabrication thereof
JP3031137B2 (ja) * 1993-10-15 2000-04-10 株式会社デンソー 絶縁物分離半導体装置
JP2773611B2 (ja) * 1993-11-17 1998-07-09 株式会社デンソー 絶縁物分離半導体装置
US5693971A (en) * 1994-07-14 1997-12-02 Micron Technology, Inc. Combined trench and field isolation structure for semiconductor devices
JP3781452B2 (ja) * 1995-03-30 2006-05-31 株式会社東芝 誘電体分離半導体装置およびその製造方法
DE19808514A1 (de) * 1997-02-28 1998-09-10 Int Rectifier Corp Halbleiterbauteil sowie Verfahren zu seiner Herstellung
EP1220312A1 (en) 2000-12-29 2002-07-03 STMicroelectronics S.r.l. Integration process on a SOI substrate of a semiconductor device comprising at least a dielectrically isolated well
JP4657614B2 (ja) * 2004-03-09 2011-03-23 Ｏｋｉセミコンダクタ株式会社 半導体装置及び半導体装置の製造方法
JP7038518B2 (ja) * 2017-10-11 2022-03-18 ローム株式会社 半導体装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4238278A (en) * 1979-06-14 1980-12-09 International Business Machines Corporation Polycrystalline silicon oxidation method for making shallow and deep isolation trenches
JPS5943545A (ja) * 1982-09-06 1984-03-10 Hitachi Ltd 半導体集積回路装置
US4593459A (en) * 1984-12-28 1986-06-10 Gte Laboratories Incorporated Monolithic integrated circuit structure and method of fabrication
US4631803A (en) * 1985-02-14 1986-12-30 Texas Instruments Incorporated Method of fabricating defect free trench isolation devices
US4799099A (en) * 1986-01-30 1989-01-17 Texas Instruments Incorporated Bipolar transistor in isolation well with angled corners
JPS63314844A (ja) * 1987-06-18 1988-12-22 Toshiba Corp 半導体装置の製造方法
JP2839651B2 (ja) * 1989-06-14 1998-12-16 株式会社東芝 半導体装置の製造方法及びその半導体装置

Also Published As

Publication number Publication date
EP0451454A3 (en) 1994-08-24
KR940003217B1 (ko) 1994-04-16
JPH03234042A (ja) 1991-10-18
JPH0736419B2 (ja) 1995-04-19
EP0451454B1 (en) 2002-05-15
US5111272A (en) 1992-05-05
DE69133009T2 (de) 2002-11-07
DE69133009D1 (de) 2002-06-20
EP0451454A2 (en) 1991-10-16

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