GB2100508A - Method of making semiconductor devices - Google Patents
Method of making semiconductor devices Download PDFInfo
- Publication number
- GB2100508A GB2100508A GB8118662A GB8118662A GB2100508A GB 2100508 A GB2100508 A GB 2100508A GB 8118662 A GB8118662 A GB 8118662A GB 8118662 A GB8118662 A GB 8118662A GB 2100508 A GB2100508 A GB 2100508A
- Authority
- GB
- United Kingdom
- Prior art keywords
- recesses
- semiconductor
- semiconductor material
- passivation material
- passivation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 43
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 239000000463 material Substances 0.000 claims abstract description 56
- 238000002161 passivation Methods 0.000 claims abstract description 36
- 238000000034 method Methods 0.000 claims abstract description 26
- 238000000227 grinding Methods 0.000 claims abstract description 15
- 239000010410 layer Substances 0.000 claims description 13
- 238000005299 abrasion Methods 0.000 claims description 6
- 239000010432 diamond Substances 0.000 claims description 5
- 239000002344 surface layer Substances 0.000 claims description 2
- 239000012530 fluid Substances 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 abstract description 19
- 239000010703 silicon Substances 0.000 abstract description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 18
- 239000002019 doping agent Substances 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 230000000873 masking effect Effects 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000002826 coolant Substances 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 239000010419 fine particle Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000002002 slurry Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B7/00—Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor
- B24B7/20—Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor characterised by a special design with respect to properties of the material of non-metallic articles to be ground
- B24B7/22—Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor characterised by a special design with respect to properties of the material of non-metallic articles to be ground for grinding inorganic material, e.g. stone, ceramics, porcelain
- B24B7/228—Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor characterised by a special design with respect to properties of the material of non-metallic articles to be ground for grinding inorganic material, e.g. stone, ceramics, porcelain for grinding thin, brittle parts, e.g. semiconductors, wafers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Ceramic Engineering (AREA)
- Inorganic Chemistry (AREA)
- Mechanical Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
A method of manufacturing semiconductor devices avoids the need to etch windows in a passivation layer which overlays a semiconductor surface to enable electrically conductive contacts to be made to the semiconductor material. The method uses a grinding machine 14 to remove the passivation material 9 from those regions of the semiconductor material 1 at which electrically conductive contacts are to be formed. A large number of semiconductor devices can be fabricated simultaneously from a slice of silicon and the individual devices are defined by a pattern of recesses 7 formed in one surface of the slice. The grinding operation which removes the passivation material from the surface of the individual devices leaves the passivation material in the recesses where it is needed to protect what would otherwise be exposed p-n junctions. <IMAGE>
Description
SPECIFICATION
Semiconductor devices
This invention relates to semiconductor devices and to an improved method of manufacturing them. It is customary to form a number of semiconductor devices in a single large slice of semiconductor material, so that all the devices can be processed and manufactured simultaneously. This reduces the need to handle the devices individually, which is very desirable as they may often be very small indeed, and it further enables large numbers of devices to be produced in a relatively economical manner. Even so it has proved difficult to form electrically conductive contact regions for each device in a satisfactory manner.
The disadvantages associated with a commonly used method of forming the electrically conductive contact regions are described with reference to
Figures 1 and 2 of the accompanying drawings.
These Figures illustrate different stages in the manufacture of semiconductor diodes. Initially a thin circular disc-like slice 1 of n-type silicon has p-type dopants diffused into one of its major surfaces 2 and n-type dopants diffused into the other of its major surfaces 3. A high concentration of the p-type dopant is used to form a p+ region 4 so that a p-n junction 5 is formed between it and the original n-type silicon.
The p+ region is also highly conductive and an ohmic contact can be made to it in due course. A high concentration of n-type dopant is also used so that a layer 6 of n+ silicon is formed at the other surface, and this also forms a conductive region to which an ohmic contact can be made at a later stage in the manufacturing process.
The slice of silicon typically has a relatively large diameter of about 5 centimetres, but each diode which is to be formed in the slice has a very small surface area. The actual size of the diodes will depend on their purpose and power handling capability, but typically their dimensions will be measured in millimetres. Accordingly, each diode is very small.
A A regular pattern of recesses 7 are formed in the upper surface 2 of the slice 1 of silicon. The recesses 7 take the form of a regular grid pattern so that a number of raised island regions 8 are bounded on all sides by recesses, and in this example, each island region 8 represents a separate diode. The recesses themselves are formed by a conventional acid etch process and it is not thought necessary to describe them in detail. It is, of course, necessary to protect the exposed edges of the p-n junctions 5 where they meet the surface of the recesses 1, and this is accomplished by forming a thin layer of passivation material 9. The passivation material 9 may typically be a silicon oxide, or formed from a glass slurry.The former process is more common for very small low power devices, whereas the latter passivation material is more widely used for large high power devices. In either case, the layer of passivation material 9 extends not only over the recesses 7 so as to partially or completely fill them, but also extends over the whole of the island regions 8. In order to make an ohmic contact to the upper surface of the device, it is necessary to form a window in the passivation material, and to place an electrically conductive material in the window so as to form an excellent ohmic contact with the p+ silicon surface.
A window 10 is formed, as is shown in Figure 2, by selectively etching away part of the passivation material to expose the surface 2, and the region to be removed is defined by a conventional etch resistant mask. The window 10 cannot extend very closely to the recesses 7 since otherwise there is the risk that the window would overlap and extend into the recess itself. If this were the case the operation of the device would be impaired and it would have to be rejected during manufacture. Also precise alignment of the etch resistant mask with the pattern of recesses can be very time consuming. For these reasons the area of the window 10 is very much smaller than the available surface of the island regions 8. In practice, this significantly reduces the current handling capability of the device.Once the window 10 has been formed it is necessary to use subsequent masking operations to form the electrically conductive contact within the window. This second masking operation must be very precisely aligned with the window and is therefore difficult and time consuming. Furthermore, the etching of the passivation layer is relatively expensive due to the significant consumption of the chemical etchants, and because it is difficult to precisely align the various stages of masking and etching, the reliability of the process leaves much to be desired.
The present invention seeks to provide improved semiconductor devices and a method of making them in which these difficulties are avoided.
According to this invention, a method of making semiconductor devices includes the steps of: forming a pattern of recesses in the flat surface of a body of semiconductor material to leave an array of raised localised island regions which are spaced apart from each other; producing a layer of passivation material which overlays the island regions and the pattern of recesses; removing the passivation material from the island regions by an abrasion process to expose the semiconductor material; and producing electrically conductive contact regions at the surface of the semiconductor material from which the passivation material has been removed.
Preferably all of the passivation material is removed from the whole of the raised island regions by the action of a grinding machine which is operative to grind flat the surface of the body of semiconductor material so that the passivation material present in the pattern of recesses is partially removed to leave those portions of it immediately adjacent to the island regions flush with the ground semiconductor surface so formed.
In order to ensure that the semiconductor material is fully exposed and that a thin layer of passivation material does not remain on the island regions, it will usually be necessary to grind away a thin surface layer of the semiconductor material itself and conveniently this is done at the same time that the passivation material is removed. The amount of semiconductor material which it is permissible to remove at this stage will partly be dictated by the depth of any p-n semiconductor junctions present below the surface and by the depth of the pattern of recesses. It is, of course, necessary to leave sufficient passivation material between adjacent island regions - where p-n junctions are present it is necessary that they remain covered by the passivation material at the point where they intersect the recesses.The primary purpose of the passivation material is to protect these p-n junctions, but it may also be present to electrically isolate one portion of a semiconductor surface region from another.
The invention is particularly suitable for the manufacture of a number of diodes orthyristors or the like from a single thin slice of silicon. Each island region represents a single semiconductor device, and when the preliminary manufacturing stages have been completed to the point where the individual devices are to be separated from each other, the slice of silicon is cut along the centre lines of the recesses so that the p-n junctions which extend to and terminate in a recess wall remain covered by a protecting layer of passivation material.
The invention is further described by way of example with reference to the accompanying drawings, in which Figures 3, 4 and 5 are used to explain various stages in the manufacture of semiconductor devices in conjunction with Figures 1 and 2 which have previously been used to illustrate the known processes.
A large flat parallel sided slice 1 of n-type silicon is processed in a conventional manner until its consists of a regular array of island regions 8 surrounded by recesses 7 which are overlaid by a layer of passivation material 9, as is illustrated in Figure 1. Typically the width of each recess when it is formed in the body of silicon is about 500 LtM wide and about 100 FM deep, although these figures are given only by way of example and in practice will be largely dependent on the physical size of the semiconductor devices which are to be manufactured. Typically, the distance between the p-n junction 5 and the upper surface 2 of the silicon slice will be about 70 to 80 ,aM, so it will be appreciated that the junction 5 intersects the walls of the recesses.
When the manufacture has progressed to the stage shown in Figure 1,those portions of the passivation layer 9 which lie overthe raised island regions 8 are removed in a grinding operation. The silicon slice 1 is mounted on a firm and rigid base and held in position by suction, and a grinding head is passed over the surface of the silicon slice to grind away the selected portions of the passivation layer.
Referring to Figure 3, the circular silicon slice 1 contains a large number of square island regions 8 which are separated from each other by the pattern of recesses 7. This pattern of recesses consists of a regular grid formed by intersecting straight lines, and as previously mentioned, is formed by selectively etching the upper surface of the silicon slice in a conventional manner. It will be seen that a fairly large number of individual devices are formed within a single slice, but the passivation layer 4 is removed from the whole of the slice in a single operation, to leave only the passivation material lying within the recesses themselves.
The grinding head typically consists of an inverted cup-like structure 14 having diamonds embedded in its rim. The diamonds lie in a single flat plane and define a flat cutting surface which grinds away the passivation material and the adjacent surface of the semiconductor material by an abrasion process. The grinding head is cooled by copious supplies of a liquid coolant, such as water. This also serves to carry away the fine particles of silicon as they are removed from the slice, and so keeps the head clean and prevents it becoming clogged. To ensure that the ground surface is finished uniformly the cup 14 is rotated very rapidly indeed in the direction of the arrow 15, whilst it is moved linearly in the direction of the arrow 16 at a relatively very slow rate across the surface of the slice 10.At the same time the silicon slice 10 is rotated relatively slowly in its own plane in the direction of the arrow 17. These movements combine to enable the abrading edge of the grinding head to produce a very flat and uniform surface. The surface is ground to the final depth in a single operation - it is not removed in a number of shallow passes across the slice. A number of slices can be mounted side by side on a common rigid base, so that they can all be ground at the same time, although only a single slice is shown in Figure 3.
The cup 14, and the diamonds 18 which are embedded in its rim, are shown in Figure 4 during the grinding process and it will be seen that the ground surface 19 so formed is slightly below (about 20 FtM) the original upper surface 2 of the semiconductor material - this is to ensure that the whole of the passivation layer 4 is removed. The surface of semiconductor material which is so formed does not have a mirror like surface, but has a slight and controlled roughness to which an electrically conductive contact material adheres well. This contact material 20 is shown in Figure 5 and it will be seen that it adheres only to the semiconductor material, but not to the passivation material. Typically the contact material 20 is nickel deposited by an electroless plating process.To improve the surface bond it can be subsequently sintered by heating to about 500 C.
The useful contact region extends over the whole of the raised area of the island portion and automatically extends right up to the edge of the recesses.
This maximises the current handling capability of the semiconductor device so formed, without the need to use difficult and expensive alignment techniques previously described in connection with Figure 2. A continuous contact region 22 is formed on the under side of the slice 1 at the same time as the upper contact regions 20.
Once the contact material has been deposited the individual devices are separated from each other by means of a precision saw which cuts along the centre lines 21 of the recesses to part the slice cleanly without exposing the edges of the p-n junction 5. Electrical connections are then made to the contact regions in any conventional way, e.g. by the soldering or bonding of flexible leads, to the upper surface afterthe inside has been mounted on a conductive substrate. Alternatively the upper and lower contact regions can be held between pressure contact pads - this is likely to be practical only for relatively large devices. The devices so formed by the described process are diodes, but more complex semiconductor devices such as thyristors could readily be formed by similar techniques which utilise additional processing steps. Furthermore, recesses could be formed on both sides of the semiconductor material with little additional complexity. This variant may be used with thyristors which are four junction devices and have p-n junctions located closely adjacent to both of the major surfaces of the silicon slice.
Claims (10)
1. A method of making semiconductor devices including the steps of: forming a pattern of recesses in the flat surface of a body of semiconductor material to leave an array of raised localised island regions which are spaced apart from each other; producing a layer of passivation material which overlays the island regions and the pattern of recesses; removing the passivation material from the island regions by an abrasion process to expose the semiconductor material; and producing electrically conductive contact regions at the surface of the semiconductor material from which the passivation material has been removed.
2. A method as claimed in claim 1 and wherein all of the passivation material is removed from the whole of the raised island regions by the action of a grinding machine which is operative to grind flat the surface of the body of semiconductor material so that passivation material present in the pattern of recesses is partially removed to leave those portions of it immediately adjacent to the island regions flush with the ground semiconductor surface so formed.
3. A method as claimed in claim 2 and wherein a thin surface layer of the semiconductor material is also ground away at the same time as the passivation material.
4. A method as claimed in claim 1,2 or 3 and wherein the electrically conductive contact regions extend to the edges of the recesses.
5. A method as claimed in any of the preceding claims and wherein the abrasion process is effected by a rotary grinding head having diamonds which constitute its cutting edges.
6. A method as claimed in claim 5 and wherein the grinding head consists of a hollow cup-like member having the diamonds disposed evenly around its rim.
7. A method as claimed in claim 5 and wherein, during the abrasion process, the grinding head and the body of semiconductor material are both rotated, and also have a linear motion relative to each other.
8. A method as claimed in claim 7 and wherein the grinding head is rotated much more rapidly than the body of semiconductor material.
9. A method as claimed in claim 5, 6, 7 or 8 and wherein the grinding head is cooled by a fluid which also serves to remove the fine particis produced by the abrasion process.
10. Semiconductor devices produced bythe method claimed in any of the preceding claims.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB8118662A GB2100508A (en) | 1981-06-17 | 1981-06-17 | Method of making semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB8118662A GB2100508A (en) | 1981-06-17 | 1981-06-17 | Method of making semiconductor devices |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| GB2100508A true GB2100508A (en) | 1982-12-22 |
Family
ID=10522575
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB8118662A Withdrawn GB2100508A (en) | 1981-06-17 | 1981-06-17 | Method of making semiconductor devices |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB2100508A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4822757A (en) * | 1987-11-10 | 1989-04-18 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method of manufacturing the same |
| EP0455087A1 (en) * | 1990-04-24 | 1991-11-06 | Mitsubishi Materials Corporation | Method of forming a silicon wafer with a chip separating structure and single crystal layer sections |
-
1981
- 1981-06-17 GB GB8118662A patent/GB2100508A/en not_active Withdrawn
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4822757A (en) * | 1987-11-10 | 1989-04-18 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method of manufacturing the same |
| EP0455087A1 (en) * | 1990-04-24 | 1991-11-06 | Mitsubishi Materials Corporation | Method of forming a silicon wafer with a chip separating structure and single crystal layer sections |
| US5804495A (en) * | 1990-04-24 | 1998-09-08 | Mitsubishi Materials Corporation | Method of making SOI structure |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |