CN105745749A - 方法及具有包含金属源极的存储器单元的串的设备 - Google Patents

方法及具有包含金属源极的存储器单元的串的设备 Download PDF

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CN105745749A
CN105745749A CN201480063209.0A CN201480063209A CN105745749A CN 105745749 A CN105745749 A CN 105745749A CN 201480063209 A CN201480063209 A CN 201480063209A CN 105745749 A CN105745749 A CN 105745749A
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memory cell
source
control gate
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groove
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陆振宇
罗杰·W·林赛
安德鲁·比克斯勒
永军·杰夫·胡
刘海涛
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Micron Technology Inc
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Abstract

本发明揭示用于形成存储器单元的串的方法、一种具有存储器单元的串的设备及一种系统。一种用于形成存储器单元的所述串的方法包括在衬底上方形成金属硅化物源极材料。对所述金属硅化物源极材料进行掺杂。存储器单元的垂直串形成在所述金属硅化物源极材料上方。半导体材料垂直形成且邻近于存储器单元的所述垂直串并耦合到所述金属硅化物源极材料。

Description

方法及具有包含金属源极的存储器单元的串的设备
优先权申请
本申请案主张2013年11月1日申请的第14/069,553号美国申请案的优先权益，所述申请案以全文引用方式并入本文。
技术领域
本发明大体上涉及存储器及存储器中的金属源极。
背景技术
存储器装置通常被提供作为计算机或其它电子装置中的内部半导体集成电路。存在许多不同类型的存储器，其包含随机存取存储器(RAM)、只读存储器(ROM)、动态随机存取存储器(DRAM)、同步动态随机存取存储器(SDRAM)及非易失性(例如，快闪)存储器。
快闪存储器装置通常使用单晶体管存储器单元，其可允许高存储器密度、高可靠性及低功耗。存储器单元的阈值电压的变化(通过例如浮动栅极、俘获层的电荷存储结构的编程或其它物理现象而出现)可确定每一单元的数据状态。
存储器单元可被布置在存储器单元的串中，其中每一串可耦合到源极。存储器单元的串的群组(例如，存储器块)可全部耦合到共源极。
当存储器制造商希望增加存储器装置的存储器密度时，可将存储器单元的串的额外群组添加到存储器装置且将其耦合到共源极。因此，共源极可增加长度，由此增加其电阻。
可希望保持源极的电阻尽可能低，如所属领域中众所周知，较大电阻可导致从电路的特定点到共源极的较大电压降。较大电压降可在依赖于极小电压差的存储器操作期间引起问题。
附图说明
图1说明存储器单元的串的实施例的示意图。
图2到10说明用于形成存储器单元的垂直串的制造步骤的实施例。
图11说明系统的实施例的框图。
具体实施方式
在以下详述中，参考形成详述的一部分且其中通过说明展示特定实施例的附图。在图式中，相同数字描述若干视图中的大致上类似组件。可利用其它实施例，且在不脱离本发明的范围的情况下可作出结构、逻辑及电改变。以下详述因此不应被认为具有限制意义。
图1说明存储器单元的串100的示意图。仅仅为了说明目的，串100被示为具有16个存储器单元112。替代实施例可包含多于或少于16个的存储器单元112。串100可包含源极选择栅极晶体管120，其可包含耦合在串100的一端处的存储器单元112中的一者与共源极126之间的n沟道晶体管。共源极126可包括(例如)常见的掺杂半导体材料及/或其它导电材料的狭槽。在串100的另一端处，漏极选择栅极晶体管130可包含耦合在存储器单元112中的一者与数据线(例如，位线)134之间的n沟道晶体管。
存储器单元112中的每一者可包括(例如)浮动栅极晶体管或替代地电荷俘获晶体管，且可包含单电平电荷存储装置或多电平电荷存储装置。存储器单元112、源极选择栅极晶体管120及漏极选择栅极晶体管130受其相应控制栅极上的信号控制，所述信号被提供在存取线(例如，字线)WL0到WL15上。在一个实施例中，一行存储器单元中的存储器单元的控制栅极可形成存取线的部分。
源极选择栅极晶体管120接收控制信号，所述控制信号控制源极选择栅极晶体管120以大致上控制串100与共源极126之间的传导。漏极选择栅极晶体管130接收控制漏极选择栅极晶体管130的控制信号，使得漏极选择栅极晶体管130可用来选择或取消选择串100。
串100可为存储器装置(例如，NAND架构快闪存储器装置)中的存储器单元的块中的存储器单元112的多个串中的一者。存储器单元112的每一串100可垂直形成使得其从衬底向外延伸，这与以沿衬底的平坦方式形成对比。
图2说明用于形成存储器单元的垂直串的制造步骤的实施例。源极材料200(例如，金属硅化物)可形成在衬底209(例如，硅)上方以用作金属源极材料。氧化物或多晶硅材料210可形成在衬底209与源极材料200之间。
源极材料200可包含硅化钨(WSiX)或某种其它类型的金属硅化物。例如，金属硅化物可包含以下一者：硅化钨(WSiX)、硅化钽(TaSiX)或硅化钼(MoSiX)。金属硅化物可更好地充当掺杂源极金属，因为金属硅化物可比纯金属材料更好地进行掺杂。
覆盖材料202可形成在源极材料200上方。覆盖材料202可包含氧化物材料(例如，硅的氧化物)、多晶硅材料或用于密封源极材料200中的孔的某种其它覆盖材料。如果覆盖材料202是氧化物(例如，硅的氧化物)，那么氧化物可用作源极选择栅极晶体管(例如如图1中说明的源极选择栅极晶体管120)的源极选择栅极氧化物。
图2中的源极材料200可以掺杂工艺204(例如，植入工艺)掺杂以按需要更改其电性质。例如，可在掺杂工艺204中使用砷或磷来掺杂金属材料以产生n型导电材料。可在掺杂工艺204中使用硼或镓来掺杂源极材料200以产生p型导电材料。
图3说明用于形成存储器单元的垂直串的另一制造步骤的实施例。多晶硅材料300可形成在覆盖材料202上方。在实施例中，多晶硅材料300可用作源极选择栅极晶体管(例如如图1中说明的源极选择栅极晶体管120)的栅极。
图4说明用于形成存储器单元的垂直串的一系列制造步骤的实施例。蚀刻停止材料400可形成在多晶硅材料300上方。在实施例中，蚀刻停止材料400可包含金属氧化物，例如氧化铝(Al2O3)。
控制栅极材料401、403可连同交替绝缘体材料402、404形成在蚀刻停止材料400上方。例如，控制栅极材料401、403可包含多晶硅材料，且交替绝缘体材料402、404可包含氧化物材料。控制栅极材料401、403可用作垂直形成的存储器单元的控制栅极。绝缘体材料402、404可在存储器单元之间使用以将相邻存储器单元彼此隔离。
蚀刻掩模405可形成在垂直堆叠420的顶部上方。在实施例中，蚀刻掩模405可包含氮化物硬掩模。
图5说明用于形成存储器单元的垂直串的一系列额外制造步骤的实施例。蚀刻步骤可用来在垂直堆叠420中形成向下穿过蚀刻停止材料400的沟槽500。定向蚀刻工艺可用来将凹口501到504形成到沟槽壁的两侧上的控制栅极材料401、403中。
图6说明用于形成存储器单元的垂直串的一系列额外制造步骤的实施例。电介质材料(例如，氧化物-氮化物-氧化物(ONO))600可沿沟槽500的内壁形成。ONO材料600还可给凹口501到504的壁加衬里。在实施例中，ONO材料600可用作用于存储器单元的串的电介质材料。
多晶硅材料601可沿沟槽500的侧壁形成(例如，沉积)在ONO材料600上方。多晶硅材料601还可填充凹口501到504。在实施例中，多晶硅材料601可用作用于存储器单元的串中的每一存储器单元的浮动栅极。
如图7中所示，可使用后期多晶硅蚀刻工艺去除沿侧壁的多晶硅601的部分且用来形成穿过先前形成的材料202、300、400的沟槽700。沟槽700可向下形成到源极材料200。去除给沟槽700的侧壁加衬里的多晶硅材料601的一部分之后，填充凹口501到504的多晶硅材料601的剩余部分可用作存储器单元的浮动栅极。因为蚀刻穿过如此多的材料202、300、400可使用强大的蚀刻工艺，所以金属材料200可用作优于多晶硅材料的蚀刻停止材料。
图8说明用于形成存储器单元的垂直串的一系列额外制造步骤的实施例。氧化物800到804可沿沟槽700的区域形成(例如，生长)。例如，氧化物800到803可形成在每一凹口501到504中的每一多晶硅材料上方。在实施例中，此氧化物800到803可用作浮动栅极与后续形成(例如，在形成氧化物800到804之后形成)的沟道材料之间的隧道电介质。
氧化物804可沿沟槽700的侧壁及底部部分的底部820形成(例如，生长)。在实施例中，此氧化物804可用作源极选择栅极的多晶硅材料300的电介质。
多晶硅衬里810可沿沟槽700的侧壁及底部820形成。多晶硅衬里810可形成在先前形成的氧化物800到804上方(例如，在形成氧化物800到804之后形成)。
图9说明用于形成存储器单元的垂直串的另一制造步骤的实施例。定向蚀刻工艺可用来去除形成于沟槽700的底部820处的多晶硅衬里810的一部分及氧化物804的一部分。此步骤可赋予随后形成的沟道材料与源极材料200的欧姆接触。
图10说明用于形成存储器单元的垂直串的另一制造步骤的实施例。半导体材料(例如，多晶硅)1000可用来填充沟槽。在实施例中，半导体材料1000可在形成于沟槽中的存储器单元1010的垂直串的操作期间用作沟道。在实施例中，半导体材料1000与源极材料200的欧姆接触使得在操作期间能够发生从源极材料200到沟道(例如，半导体材料1000)的扩散(例如，N+扩散)。
图11说明可使用图1到10的存储器单元的垂直形成串的系统的实施例。控制器1100可用来控制系统的操作。耦合到控制器1100的存储器1101可包含存储器单元的垂直形成串。在实施例中，控制器1100可通过控制、数据及地址总线耦合到存储器1101。在另一实施例中，地址及数据总线可共享共用I/O总线。
设备可被界定为电路、集成电路裸片、装置或系统。
结论
一或多个实施例可提供掺杂金属硅化物源极。掺杂金属硅化物源极可提供低于多晶硅源极的薄层电阻，且还提供充足的栅极引发漏极漏电性能。存储器单元的垂直串可形成在掺杂金属硅化物源极上方，且半导体材料垂直地形成在存储器单元的垂直串附近。半导体材料可与掺杂金属硅化物源极接触以实现从源极到用作存储器单元的串的沟道的半导体材料的扩散。
虽然本文已说明并描述了特定实施例，但是所属领域一般技术人员将明白，旨在实现相同目的的任何布置均可被所示的特定实施例取代。所属领域一般技术人员将明白许多调整。因此，本申请案旨在涵盖任何调整或变动。

Claims (29)

1.一种方法，其包括：
形成包含金属的源极材料；及
在所述源极材料上方形成存储器单元的串，存储器单元的所述串包含与所述源极材料接触的沟道材料。
2.根据权利要求1所述的方法，且其进一步包括：
在所述源极材料上方形成覆盖材料；
对所述源极材料进行掺杂；及
在所述覆盖材料上方形成选择栅极材料。
3.根据权利要求2所述的方法，其中形成存储器单元的所述串包括：
在所述选择栅极材料上方形成交替控制栅极材料及绝缘体材料；
形成穿过所述交替控制栅极材料及绝缘体材料、所述选择栅极材料及所述覆盖材料的沟槽，所述沟槽包括形成在所述控制栅极材料中的所述沟槽的侧壁上的凹口；
在所述交替控制栅极材料及绝缘体材料的所述沟槽的所述凹口以及所述侧壁上方形成电介质材料；
在所述凹口中形成浮动栅极材料；
在所述浮动栅极材料及所述选择栅极材料的所述沟槽的所述侧壁上方形成隧道电介质材料；及
在所述沟槽中形成所述沟道材料使得所述沟道材料接触所述源极材料。
4.根据权利要求1所述的方法，其中形成所述源极材料包括在衬底上方形成所述源极材料。
5.根据权利要求4所述的方法，且其进一步包括在所述衬底与所述源极材料之间形成氧化物。
6.根据权利要求4所述的方法，且其进一步包括在所述衬底与所述源极材料之间形成多晶硅材料。
7.根据权利要求1所述的方法，其中所述源极材料是金属硅化物。
8.根据权利要求7所述的方法，其中所述金属硅化物是以下一者：硅化钨WSiX、硅化钽TaSiX或硅化钼MoSiX。
9.根据权利要求1所述的方法，且其进一步包括在所述交替控制栅极材料及绝缘体材料上方形成氮化物硬掩模。
10.根据权利要求1所述的方法，其中所述电介质材料包括氧化物-氮化物-氧化物ONO材料。
11.根据权利要求1所述的方法，其中所述隧道电介质材料及所述绝缘体材料包括氧化物材料。
12.根据权利要求1所述的方法，其中所述覆盖材料包括氧化物或多晶硅材料中的一者。
13.根据权利要求1所述的方法，其中所述选择栅极材料、所述控制栅极材料、所述浮动栅极材料及所述沟道材料包括多晶硅。
14.根据权利要求1所述的方法，且其进一步包括在所述选择栅极材料与所述交替控制栅极材料及绝缘体材料之间形成蚀刻停止材料。
15.一种方法，其包括：
在衬底上方形成金属硅化物源极材料；
在所述金属硅化物源极材料上方形成覆盖材料；
对所述金属硅化物源极材料进行掺杂；
在所述覆盖材料上方形成多晶硅选择栅极材料；及
在所述多晶硅选择栅极材料上方形成存储器单元的串，存储器单元的所述串包含延伸穿过所述多晶硅选择栅极材料及所述覆盖材料以接触所述源极材料的沟道材料。
16.根据权利要求15所述的方法，其中对所述金属硅化物源极材料进行掺杂包括利用砷、硼、磷或镓中的一者对所述金属硅化物源极材料进行掺杂。
17.根据权利要求15所述的方法，其中对所述金属硅化物源极材料进行掺杂包括以下一者：利用砷或磷将所述金属硅化物材料掺杂为n型导电材料或利用硼或镓将所述金属硅化物材料掺杂而产生p型导电材料。
18.根据权利要求15所述的方法，其中所述沟槽是第二沟槽且其进一步包括在形成穿过所述蚀刻停止材料、所述选择栅极材料及所述覆盖材料的所述第二沟槽之前：
形成穿过所述交替控制栅极材料及所述氧化物材料以及所述蚀刻停止材料的第一沟槽；
在所述凹口中且沿所述第一沟槽的所述侧壁在ONO材料上方形成多晶硅；以及去除沿所述第一沟槽的所述侧壁的所述多晶硅。
19.根据权利要求18所述的方法，其中在形成所述第二沟槽时执行去除沿所述第一沟槽的所述侧壁的所述多晶硅。
20.一种设备，其包括：
存储器单元的垂直串，其包括控制栅极材料及绝缘体材料的多个交替层级；
半导体材料，其延伸穿过控制栅极材料及绝缘体材料的所述多个交替层级；以及
掺杂金属硅化物源极，其耦合到所述半导体材料。
21.根据权利要求20所述的设备，其中存储器单元的所述垂直串的存储器单元包括：
所述控制栅极材料中的凹口；
电介质材料，其给所述凹口以及控制栅极材料及绝缘体材料的所述多个交替层级加衬里；
浮动栅极材料，其在所述凹口中；以及
隧道电介质材料，其邻近于所述浮动栅极材料。
22.根据权利要求21所述的设备，其中所述电介质材料包括氧化物-氮化物-氧化物。
23.根据权利要求20所述的设备，其中所述掺杂金属硅化物源极包括N+掺杂金属硅化物。
24.根据权利要求20所述的设备，且其进一步包括选择栅极材料及绝缘体材料，其邻近于所述半导体材料且介于控制栅极材料的最低层级与所述掺杂金属硅化物源极之间。
25.一种方法，其包括：
形成金属源极材料；
在所述金属源极材料上方形成覆盖材料；
对所述金属源极材料进行掺杂；
在所述覆盖材料上方形成选择栅极材料；
在所述选择栅极材料上方、在控制栅极材料及绝缘体材料的多个交替层中形成存储器单元的垂直串；以及
形成耦合到所述金属源极材料且邻近于存储器单元的所述垂直串及所述选择栅极材料的垂直半导体材料，其中存储器单元的所述垂直串及所述选择栅极材料通过隧道电介质材料与垂直半导体材料绝缘。
26.根据权利要求25所述的方法，其中形成存储器单元的所述垂直串包括：
在每一控制栅极材料中形成凹口；
利用电介质材料给所述凹口加衬里；以及
利用浮动栅极材料填充所述经加衬里凹口。
27.根据权利要求26所述的方法，其中所述电介质材料耦合存储器单元的所述垂直串中的所述存储器单元中的每一者。
28.根据权利要求25所述的方法，其中所述绝缘体材料及所述隧道电介质材料包括氧化物材料。
29.根据权利要求25所述的方法，其中形成耦合到所述金属源极材料的所述垂直半导体材料包括在所述垂直半导体材料与所述金属源极材料之间形成欧姆接触。
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108565265A (zh) * 2018-04-17 2018-09-21 长江存储科技有限责任公司 一种三维存储器及其数据操作方法
US10090317B2 (en) 2013-11-01 2018-10-02 Micron Technology, Inc. Methods and apparatuses having memory cells including a monolithic semiconductor channel
US10529776B2 (en) 2013-03-15 2020-01-07 Micron Technology, Inc. Cell pillar structures and integrated flows
CN111326522A (zh) * 2020-03-10 2020-06-23 长江存储科技有限责任公司 三维存储器制造方法及三维存储器
TWI724881B (zh) * 2020-03-16 2021-04-11 大陸商長江存儲科技有限責任公司 記憶體元件以及形成記憶體元件的方法

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9437604B2 (en) 2013-11-01 2016-09-06 Micron Technology, Inc. Methods and apparatuses having strings of memory cells including a metal source
US9548313B2 (en) * 2014-05-30 2017-01-17 Sandisk Technologies Llc Method of making a monolithic three dimensional NAND string using a select gate etch stop layer
US10283520B2 (en) 2016-07-12 2019-05-07 Micron Technology, Inc. Elevationally-extending string of memory cells individually comprising a programmable charge storage transistor and method of forming an elevationally-extending string of memory cells individually comprising a programmable charge storage transistor
US10090318B2 (en) 2016-08-05 2018-10-02 Micron Technology, Inc. Vertical string of memory cells individually comprising a programmable charge storage transistor comprising a control gate and a charge storage structure and method of forming a vertical string of memory cells individually comprising a programmable charge storage transistor comprising a control gate and a charge storage structure
US10038002B2 (en) 2016-10-18 2018-07-31 Micron Technology, Inc. Semiconductor devices and methods of fabrication
US10707121B2 (en) * 2016-12-31 2020-07-07 Intel Corporatino Solid state memory device, and manufacturing method thereof
WO2019046106A1 (en) 2017-08-29 2019-03-07 Micron Technology, Inc. DEVICES AND SYSTEMS WITH CHAIN DRIVERS COMPRISING HIGH BANNED MATERIAL AND METHODS OF FORMATION
US10608012B2 (en) 2017-08-29 2020-03-31 Micron Technology, Inc. Memory devices including memory cells and related methods
KR102414294B1 (ko) 2017-09-08 2022-06-28 삼성전자주식회사 비휘발성 메모리 장치 및 그 제조 방법
US10923493B2 (en) 2018-09-06 2021-02-16 Micron Technology, Inc. Microelectronic devices, electronic systems, and related methods

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101211970A (zh) * 2006-12-28 2008-07-02 中芯国际集成电路制造(上海)有限公司 半导体器件及其制作方法
JP2009158529A (ja) * 2007-12-25 2009-07-16 Toshiba Corp 不揮発性半導体記憶装置
US20100207193A1 (en) * 2009-02-16 2010-08-19 Kabushiki Kaisha Toshiba Non-volatile semiconductor storage device and method of manufacturing the same
US20110049608A1 (en) * 2009-09-02 2011-03-03 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device and method of manufacturing the same
US20110233646A1 (en) * 2010-03-23 2011-09-29 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device and method of manufacturing the same
US20120132981A1 (en) * 2010-11-30 2012-05-31 Kabushiki Kaisha Toshiba Semiconductor storage device and manufacturing method of semiconductor storage device

Family Cites Families (123)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2755613B2 (ja) 1988-09-26 1998-05-20 株式会社東芝 半導体装置
JPH0936257A (ja) 1995-07-14 1997-02-07 Matsushita Electron Corp 半導体記憶装置およびその製造方法
SE514380C2 (sv) * 1996-03-29 2001-02-19 Sture Pettersson Integrerad halvledardetektorteleskop med låg energitröskel
US6168986B1 (en) 1998-01-23 2001-01-02 Micron Technology, Inc. Method of making a sacrificial self-aligned interconnect structure
US6054379A (en) 1998-02-11 2000-04-25 Applied Materials, Inc. Method of depositing a low k dielectric with organo silane
TW390028B (en) 1998-06-08 2000-05-11 United Microelectronics Corp A flash memory structure and its manufacturing
KR100819730B1 (ko) 2000-08-14 2008-04-07 샌디스크 쓰리디 엘엘씨 밀집한 어레이 및 전하 저장 장치와, 그 제조 방법
US6445029B1 (en) 2000-10-24 2002-09-03 International Business Machines Corporation NVRAM array device with enhanced write and erase
JP4039604B2 (ja) 2001-05-09 2008-01-30 本田技研工業株式会社 小型二輪車用のエンジン始動装置
US7132711B2 (en) 2001-08-30 2006-11-07 Micron Technology, Inc. Programmable array logic or memory with p-channel devices and asymmetrical tunnel barriers
US6780712B2 (en) 2002-10-30 2004-08-24 Taiwan Semiconductor Manufacturing Company Method for fabricating a flash memory device having finger-like floating gates structure
US20030155582A1 (en) 2002-02-19 2003-08-21 Maitreyee Mahajani Gate dielectric structures for integrated circuits and methods for making and using such gate dielectric structures
US6583009B1 (en) 2002-06-24 2003-06-24 Advanced Micro Devices, Inc. Innovative narrow gate formation for floating gate flash technology
US7045849B2 (en) 2003-05-21 2006-05-16 Sandisk Corporation Use of voids between elements in semiconductor structures for isolation
US6967136B2 (en) 2003-08-01 2005-11-22 International Business Machines Corporation Method and structure for improved trench processing
WO2005043160A2 (en) 2003-10-31 2005-05-12 University Of Hawaii Ultrasensitive biochemical sensing platform
US7148538B2 (en) 2003-12-17 2006-12-12 Micron Technology, Inc. Vertical NAND flash memory array
US20060134846A1 (en) 2004-12-16 2006-06-22 Macronix International Co., Ltd. Method of fabricating a semiconductor structure
US7422967B2 (en) * 2005-05-12 2008-09-09 Texas Instruments Incorporated Method for manufacturing a semiconductor device containing metal silicide regions
JP2006352104A (ja) 2005-05-20 2006-12-28 Semiconductor Energy Lab Co Ltd 半導体装置、及び半導体装置の作製方法
WO2006132158A1 (ja) 2005-06-10 2006-12-14 Sharp Kabushiki Kaisha 不揮発性半導体記憶装置およびその製造方法
US7687860B2 (en) 2005-06-24 2010-03-30 Samsung Electronics Co., Ltd. Semiconductor device including impurity regions having different cross-sectional shapes
US7829938B2 (en) 2005-07-14 2010-11-09 Micron Technology, Inc. High density NAND non-volatile memory device
US7342272B2 (en) 2005-08-31 2008-03-11 Micron Technology, Inc. Flash memory with recessed floating gate
KR100781563B1 (ko) 2005-08-31 2007-12-03 삼성전자주식회사 비휘발성 메모리 소자 및 그 제조 방법.
JP4822841B2 (ja) 2005-12-28 2011-11-24 株式会社東芝 半導体記憶装置及びその製造方法
CN100547604C (zh) 2006-03-27 2009-10-07 李克 带有电子标签录像的物流查询系统
JP4762041B2 (ja) 2006-04-24 2011-08-31 株式会社東芝 不揮発性半導体メモリ
KR100801078B1 (ko) 2006-06-29 2008-02-11 삼성전자주식회사 수직 채널을 갖는 비휘발성 메모리 집적 회로 장치 및 그제조 방법
US7906804B2 (en) * 2006-07-19 2011-03-15 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device and manufacturing method thereof
US7667260B2 (en) 2006-08-09 2010-02-23 Micron Technology, Inc. Nanoscale floating gate and methods of formation
JP4768557B2 (ja) * 2006-09-15 2011-09-07 株式会社東芝 不揮発性半導体記憶装置及びその製造方法
JP2008092708A (ja) 2006-10-03 2008-04-17 Hitachi Ltd モータ駆動制御装置
JP4772656B2 (ja) 2006-12-21 2011-09-14 株式会社東芝 不揮発性半導体メモリ
JP2008192708A (ja) * 2007-02-01 2008-08-21 Toshiba Corp 不揮発性半導体記憶装置
JP2008192857A (ja) * 2007-02-05 2008-08-21 Toshiba Corp 不揮発性半導体記憶装置及びその製造方法
JP4445514B2 (ja) 2007-04-11 2010-04-07 株式会社東芝 半導体記憶装置
KR100866966B1 (ko) 2007-05-10 2008-11-06 삼성전자주식회사 비휘발성 메모리 소자, 그 제조 방법 및 반도체 패키지
US8633537B2 (en) 2007-05-25 2014-01-21 Cypress Semiconductor Corporation Memory transistor with multiple charge storing layers and a high work function gate electrode
TWI340431B (en) 2007-06-11 2011-04-11 Nanya Technology Corp Memory structure and method of making the same
US7910446B2 (en) 2007-07-16 2011-03-22 Applied Materials, Inc. Integrated scheme for forming inter-poly dielectrics for non-volatile memory devices
US7795673B2 (en) 2007-07-23 2010-09-14 Macronix International Co., Ltd. Vertical non-volatile memory
US20090039410A1 (en) 2007-08-06 2009-02-12 Xian Liu Split Gate Non-Volatile Flash Memory Cell Having A Floating Gate, Control Gate, Select Gate And An Erase Gate With An Overhang Over The Floating Gate, Array And Method Of Manufacturing
KR100953050B1 (ko) 2007-10-10 2010-04-14 주식회사 하이닉스반도체 비휘발성 메모리 소자 및 그의 제조 방법
KR101226685B1 (ko) 2007-11-08 2013-01-25 삼성전자주식회사 수직형 반도체 소자 및 그 제조 방법.
KR20090079694A (ko) 2008-01-18 2009-07-22 삼성전자주식회사 비휘발성 메모리 소자 및 그 제조 방법
KR20090094632A (ko) * 2008-03-03 2009-09-08 삼성전자주식회사 액정 조성물 및 이를 이용한 액정 표시 장치
JP5086851B2 (ja) 2008-03-14 2012-11-28 株式会社東芝 不揮発性半導体記憶装置
JP2009224468A (ja) 2008-03-14 2009-10-01 Toshiba Corp 不揮発性半導体記憶装置
JP2009277770A (ja) 2008-05-13 2009-11-26 Toshiba Corp 不揮発性半導体記憶装置及びその製造方法
JP2010004020A (ja) 2008-05-19 2010-01-07 Toshiba Corp 不揮発性半導体記憶装置およびその製造方法
US8120951B2 (en) * 2008-05-22 2012-02-21 Micron Technology, Inc. Memory devices, memory device constructions, constructions, memory device forming methods, current conducting devices, and memory cell programming methods
JP5230274B2 (ja) 2008-06-02 2013-07-10 株式会社東芝 不揮発性半導体記憶装置
KR101052921B1 (ko) 2008-07-07 2011-07-29 주식회사 하이닉스반도체 버티컬 플로팅 게이트를 구비하는 플래시 메모리소자의제조방법
US8044448B2 (en) 2008-07-25 2011-10-25 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device
JP2010123600A (ja) 2008-11-17 2010-06-03 Toshiba Corp 不揮発性半導体記憶装置
KR101551901B1 (ko) 2008-12-31 2015-09-09 삼성전자주식회사 반도체 기억 소자 및 그 형성 방법
JP5388600B2 (ja) 2009-01-22 2014-01-15 株式会社東芝 不揮発性半導体記憶装置の製造方法
WO2010086067A1 (en) 2009-01-29 2010-08-05 International Business Machines Corporation Memory transistor with a non-planar floating gate and manufacturing method thereof
KR101573697B1 (ko) 2009-02-11 2015-12-02 삼성전자주식회사 수직 폴딩 구조의 비휘발성 메모리 소자 및 그 제조 방법
KR101539699B1 (ko) 2009-03-19 2015-07-27 삼성전자주식회사 3차원 구조의 비휘발성 메모리 소자 및 그 제조방법
US8274110B2 (en) 2009-05-20 2012-09-25 Micron Technology, Inc. Vertically-oriented semiconductor selection device providing high drive current in cross-point array memory
JP2011003722A (ja) 2009-06-18 2011-01-06 Toshiba Corp 半導体装置の製造方法
KR101543331B1 (ko) * 2009-07-06 2015-08-10 삼성전자주식회사 메탈 소스 라인을 갖는 수직 구조의 비휘발성 메모리 소자의 제조방법
JP2011023586A (ja) 2009-07-16 2011-02-03 Toshiba Corp 半導体記憶装置およびその製造方法
KR101525130B1 (ko) * 2009-08-03 2015-06-03 에스케이하이닉스 주식회사 수직채널형 비휘발성 메모리 소자 및 그 제조 방법
US8258034B2 (en) 2009-08-26 2012-09-04 Micron Technology, Inc. Charge-trap based memory
KR101698193B1 (ko) 2009-09-15 2017-01-19 삼성전자주식회사 3차원 반도체 메모리 장치 및 그 제조 방법
KR101603731B1 (ko) * 2009-09-29 2016-03-16 삼성전자주식회사 버티칼 낸드 전하 트랩 플래시 메모리 디바이스 및 제조방법
KR101075494B1 (ko) * 2009-12-18 2011-10-21 주식회사 하이닉스반도체 수직채널형 비휘발성 메모리 소자 및 그 제조 방법
JP2011166061A (ja) 2010-02-15 2011-08-25 Toshiba Corp 半導体装置の製造方法
KR101663566B1 (ko) * 2010-03-03 2016-10-07 삼성전자주식회사 3차원 반도체 기억 소자 및 그 형성 방법
JP2011187794A (ja) 2010-03-10 2011-09-22 Toshiba Corp 半導体記憶装置及びその製造方法
US8357970B2 (en) 2010-04-09 2013-01-22 Micron Technology, Inc. Multi-level charge storage transistors and associated methods
WO2011133825A1 (en) 2010-04-21 2011-10-27 Battelle Memorial Institute Fibers containing ferrates and methods
KR101884296B1 (ko) 2010-05-14 2018-08-01 고쿠리츠다이가쿠호진 도호쿠다이가쿠 반도체 집적 회로와 그 제조 방법
KR101738533B1 (ko) 2010-05-24 2017-05-23 삼성전자 주식회사 적층 메모리 장치 및 그 제조 방법
KR101623546B1 (ko) 2010-05-28 2016-05-23 삼성전자주식회사 3차원 반도체 메모리 장치 및 그 제조 방법
KR20110135692A (ko) * 2010-06-11 2011-12-19 삼성전자주식회사 3차원 반도체 메모리 장치 및 그 제조 방법
US8803214B2 (en) 2010-06-28 2014-08-12 Micron Technology, Inc. Three dimensional memory and methods of forming the same
US8187936B2 (en) 2010-06-30 2012-05-29 SanDisk Technologies, Inc. Ultrahigh density vertical NAND memory device and method of making thereof
US8198672B2 (en) 2010-06-30 2012-06-12 SanDisk Technologies, Inc. Ultrahigh density vertical NAND memory device
US8349681B2 (en) * 2010-06-30 2013-01-08 Sandisk Technologies Inc. Ultrahigh density monolithic, three dimensional vertical NAND memory device
US8237213B2 (en) 2010-07-15 2012-08-07 Micron Technology, Inc. Memory arrays having substantially vertical, adjacent semiconductor structures and the formation thereof
KR101660262B1 (ko) 2010-09-07 2016-09-27 삼성전자주식회사 수직형 반도체 소자의 제조 방법
KR20120029291A (ko) 2010-09-16 2012-03-26 삼성전자주식회사 반도체 소자 및 그 제조 방법
KR101731060B1 (ko) * 2010-09-27 2017-04-28 삼성전자주식회사 수직형 반도체 소자 및 그 제조 방법
KR101792778B1 (ko) 2010-10-26 2017-11-01 삼성전자주식회사 비휘발성 메모리 장치 및 그 형성 방법
JP2012094694A (ja) 2010-10-27 2012-05-17 Toshiba Corp 不揮発性半導体記憶装置
KR101800438B1 (ko) 2010-11-05 2017-11-23 삼성전자주식회사 3차원 반도체 장치 및 그 제조 방법
JP2012146773A (ja) 2011-01-11 2012-08-02 Hitachi Kokusai Electric Inc 不揮発性半導体記憶装置およびその製造方法
US8681555B2 (en) 2011-01-14 2014-03-25 Micron Technology, Inc. Strings of memory cells having string select gates, memory devices incorporating such strings, and methods of accessing and forming the same
US8759895B2 (en) 2011-02-25 2014-06-24 Micron Technology, Inc. Semiconductor charge storage apparatus and methods
KR101206508B1 (ko) * 2011-03-07 2012-11-29 에스케이하이닉스 주식회사 3차원 구조를 갖는 비휘발성 메모리 장치 제조방법
US8445347B2 (en) * 2011-04-11 2013-05-21 Sandisk Technologies Inc. 3D vertical NAND and method of making thereof by front and back side processing
JP2012227326A (ja) 2011-04-19 2012-11-15 Toshiba Corp 不揮発性半導体記憶装置とその製造方法
US8722525B2 (en) 2011-06-21 2014-05-13 Micron Technology, Inc. Multi-tiered semiconductor devices and associated methods
KR20130024303A (ko) * 2011-08-31 2013-03-08 에스케이하이닉스 주식회사 반도체 소자 및 그 제조방법
US8912589B2 (en) 2011-08-31 2014-12-16 Micron Technology, Inc. Methods and apparatuses including strings of memory cells formed along levels of semiconductor material
JP2013069928A (ja) * 2011-09-22 2013-04-18 Toshiba Corp 不揮発性半導体記憶装置
KR101845511B1 (ko) * 2011-10-11 2018-04-05 삼성전자주식회사 수직 구조의 비휘발성 메모리 소자 제조 방법
KR101906406B1 (ko) 2011-12-30 2018-12-10 삼성전자주식회사 수직 구조의 비휘발성 메모리 소자 및 그 제조방법
JP5684161B2 (ja) 2012-01-26 2015-03-11 株式会社東芝 半導体装置
US8878278B2 (en) 2012-03-21 2014-11-04 Sandisk Technologies Inc. Compact three dimensional vertical NAND and method of making thereof
JP5651632B2 (ja) * 2012-03-26 2015-01-14 株式会社東芝 プログラマブルロジックスイッチ
US20130256777A1 (en) 2012-03-30 2013-10-03 Seagate Technology Llc Three dimensional floating gate nand memory
US9627213B2 (en) 2012-04-05 2017-04-18 X-Fab Semiconductor Foundries Ag Method of fabricating a tunnel oxide layer and a tunnel oxide layer for a semiconductor device
JP5808708B2 (ja) 2012-04-10 2015-11-10 株式会社東芝 不揮発性半導体記憶装置及びその製造方法
KR20130116607A (ko) 2012-04-16 2013-10-24 삼성전자주식회사 3차원 반도체 메모리 장치 및 그 제조 방법
US8867271B2 (en) 2012-05-30 2014-10-21 Sandisk Technologies Inc. Threshold voltage adjustment for a select gate transistor in a stacked non-volatile memory device
US9178077B2 (en) 2012-11-13 2015-11-03 Micron Technology, Inc. Semiconductor constructions
US10651315B2 (en) * 2012-12-17 2020-05-12 Micron Technology, Inc. Three dimensional memory
US8946807B2 (en) 2013-01-24 2015-02-03 Micron Technology, Inc. 3D memory
US8853818B2 (en) * 2013-02-20 2014-10-07 Macronix International Co., Ltd. 3D NAND flash memory
US8933457B2 (en) * 2013-03-13 2015-01-13 Macronix International Co., Ltd. 3D memory array including crystallized channels
JP2014179465A (ja) * 2013-03-14 2014-09-25 Toshiba Corp 不揮発性半導体記憶装置およびその製造方法
US9184175B2 (en) 2013-03-15 2015-11-10 Micron Technology, Inc. Floating gate memory cells in vertical memory
US9276011B2 (en) 2013-03-15 2016-03-01 Micron Technology, Inc. Cell pillar structures and integrated flows
KR20140132102A (ko) 2013-05-07 2014-11-17 에스케이하이닉스 주식회사 반도체 메모리 장치 및 이의 동작 방법
US9437604B2 (en) 2013-11-01 2016-09-06 Micron Technology, Inc. Methods and apparatuses having strings of memory cells including a metal source
US9431410B2 (en) 2013-11-01 2016-08-30 Micron Technology, Inc. Methods and apparatuses having memory cells including a monolithic semiconductor channel
US9412753B2 (en) 2014-09-30 2016-08-09 Sandisk Technologies Llc Multiheight electrically conductive via contacts for a multilevel interconnect structure
US9608000B2 (en) 2015-05-27 2017-03-28 Micron Technology, Inc. Devices and methods including an etch stop protection material

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101211970A (zh) * 2006-12-28 2008-07-02 中芯国际集成电路制造(上海)有限公司 半导体器件及其制作方法
JP2009158529A (ja) * 2007-12-25 2009-07-16 Toshiba Corp 不揮発性半導体記憶装置
US20100207193A1 (en) * 2009-02-16 2010-08-19 Kabushiki Kaisha Toshiba Non-volatile semiconductor storage device and method of manufacturing the same
US20110049608A1 (en) * 2009-09-02 2011-03-03 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device and method of manufacturing the same
US20110233646A1 (en) * 2010-03-23 2011-09-29 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device and method of manufacturing the same
US20120132981A1 (en) * 2010-11-30 2012-05-31 Kabushiki Kaisha Toshiba Semiconductor storage device and manufacturing method of semiconductor storage device

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10529776B2 (en) 2013-03-15 2020-01-07 Micron Technology, Inc. Cell pillar structures and integrated flows
US11043534B2 (en) 2013-03-15 2021-06-22 Micron Technology, Inc. Cell pillar structures and integrated flows
US10090317B2 (en) 2013-11-01 2018-10-02 Micron Technology, Inc. Methods and apparatuses having memory cells including a monolithic semiconductor channel
US10879259B2 (en) 2013-11-01 2020-12-29 Micron Technology, Inc. Methods and apparatuses having memory cells including a monolithic semiconductor channel
CN108565265A (zh) * 2018-04-17 2018-09-21 长江存储科技有限责任公司 一种三维存储器及其数据操作方法
CN108565265B (zh) * 2018-04-17 2019-05-24 长江存储科技有限责任公司 一种三维存储器及其数据操作方法
CN111326522A (zh) * 2020-03-10 2020-06-23 长江存储科技有限责任公司 三维存储器制造方法及三维存储器
TWI724881B (zh) * 2020-03-16 2021-04-11 大陸商長江存儲科技有限責任公司 記憶體元件以及形成記憶體元件的方法
US11469245B2 (en) 2020-03-16 2022-10-11 Yangtze Memory Technologies Co., Ltd. Memory device and method for forming the same

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