CN103515390A - 包括具有不同鳍轮廓的finfet的集成电路 - Google Patents

包括具有不同鳍轮廓的finfet的集成电路 Download PDF

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CN103515390A
CN103515390A CN201310005209.2A CN201310005209A CN103515390A CN 103515390 A CN103515390 A CN 103515390A CN 201310005209 A CN201310005209 A CN 201310005209A CN 103515390 A CN103515390 A CN 103515390A
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finfet
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CN103515390B (zh
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廖忠志
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供了一种集成电路。该集成电路包括衬底、由衬底所支撑的第一FinFET器件，该第一FinFET具有带有不分层鳍轮廓的第一鳍，以及由衬底所支撑的第二FinFET，该第二FinFET具有带有分层鳍轮廓的第二鳍。本发明还提供了一种包括具有不同鳍轮廓的FINFET的集成电路。

Description

包括具有不同鳍轮廓的FINFET的集成电路
技术领域
本发明涉及半导体领域，更具体地，本发明涉及一种包括具有不同鳍轮廓的FINFET的集成电路。
背景技术
半导体器件用在大量电子器件中，诸如，计算机、手机以及其他电子器件。半导体器件包括集成电路，通过在半导体晶圆上方沉积多种材料薄膜，并且图案化材料薄膜来在半导体晶圆上形成该集成电路。集成电路包括场效应晶体管(FET)，诸如，金属氧化物半导体(MOS)晶体管。
半导体工业的目标之一是持续缩小单个FET的尺寸并且提高其速度。为了实现这些目标，发展出了鳍式FET(FINFET)或多栅极场效应晶体管(MuGFET)。这些器件不仅改善了面积密度，还改善了沟道的栅极控制。
发明内容
为了解决现有技术中所存在的问题，根据本发明的一个方面，提供了一种集成电路，包括：衬底；第一FinFET器件，由所述衬底支撑，所述第一FinFET器件包括具有不分层鳍轮廓的第一鳍；以及第二FinFET器件，由所述衬底支撑，所述第二FinFET器件包括具有分层鳍轮廓的第二鳍。
在所述的集成电路中，所述第二鳍是具有分层鳍轮廓的所述第二FinFET器件的多个第二鳍中的一个。
在所述的集成电路中，所述第一FinFET器件应用于静态随机存取存储器单元、动态随机存取存储器单元、闪存单元和静态随机存取存储器上拉晶体管中的一种。
在所述的集成电路中，所述第二FinFET器件应用于逻辑器件、下拉晶体管和传输门晶体管中的一种。
在所述的集成电路中，所述第一FinFET器件和所述第二FinFET器件均是p型金属氧化物半导体场效应晶体管。
在所述的集成电路中，所述第一FinFET器件是用作第一静态随机存取存储器中的上拉晶体管的p型金属氧化物半导体场效应晶体管，而所述第二FinFET器件是用作第二静态随机存取存储器中的下拉晶体管和传输门晶体管中的一种的n型金属氧化物半导体场效应晶体管。
在所述的集成电路中，所述第一鳍的不分层轮廓沿着所述第一鳍的长度是不一致的。
在所述的集成电路中，所述第一FinFET器件是具有多个第一鳍的多栅极场效应晶体管，所述多个第一鳍具有不分层轮廓。
在所述的集成电路中，具有所述分层鳍轮廓的所述第二鳍的下层的宽度是所述第二鳍的上层的宽度的至少两倍。
根据本发明的另一方面，提供了一种集成电路，包括：衬底；第一FinFET器件，由所述衬底支撑，所述第一FinFET器件具有在源极区域和漏极区域之间延伸并且设置在第一栅电极下方的第一鳍，所述第一鳍包括不分层鳍轮廓；以及第二FinFET器件，由所述衬底支撑，所述第二FinFET器件具有在源极区域和漏极区域之间延伸并且设置在第二栅电极下方的第二鳍，所述第二FinFET器件包括具有分层鳍轮廓的第二鳍。
在所述的集成电路中，具有所述分层鳍轮廓的所述第二鳍的下层的宽度是所述第二鳍的上层的宽度的至少两倍。
在所述的集成电路中，所述第一鳍的不分层轮廓沿着所述第一鳍的长度是不一致的。
在所述的集成电路中，所述第二鳍的上层的高度小于大约50纳米。
在所述的集成电路中，所述第一FinFET器件形成在具有第一掺杂类型的第一阱上方，并且所述第二FinFET器件形成在具有与所述第一掺杂类型不同的第二掺杂类型的第二阱上方。
在所述的集成电路中，所述第一FinFET器件包括在源极区域和漏极区域之间延伸并且设置在所述第一栅电极下方的伪鳍。
在所述的集成电路中，所述第一FinFET器件形成上拉晶体管。
在所述的集成电路中，所述第二FinFET器件形成下拉晶体管和传输门栅晶体管中的至少一个。
根据本发明的又一方面，提供了一种形成集成电路的方法，包括：在衬底上方形成第一FinFET器件，所述第一FinFET器件包括具有不分层鳍轮廓的第一鳍；以及在所述衬底上方形成第二FinFET，所述第二FinFET包括具有分层鳍轮廓的第二鳍。
在所述的方法中，还包括：在所述第一鳍和所述第二鳍的相对端部附近形成源极区域和漏极区域。
在所述的方法中，还包括：在所述第一鳍上方形成第一栅电极，以及在所述第二鳍上方形成第二栅电极。
附图说明
为了更全面地理解实施例及其优势，现将结合附图所进行的描述作为参考，其中：
图1示出了具有一个不分层的鳍的实施例FinFET；
图2示出了具有多个不分层的鳍的实施例FinFET；
图3示出了具有多个分层的鳍的实施例FinFET；
图4A和图4B示出了一个实施例集成电路器件，该集成电路器件包括有位于单个衬底上的图1的带有不分层的鳍的FinFET以及图3的带有分层的鳍的FinFET；
图5A和图5B示出了一个实施例集成电路器件，该集成电路器件包括有位于单个衬底上的带有图1的非均匀不分层的鳍的FinFET以及图3的带有分层的鳍的FinFET；
图6-图7示出了如何实现包括有图1的带有不分层的第一鳍的第一FinFET以及图3的具有分层的鳍的第三FinFET的实施例集成电路器件，从而形成SRAM单体单元的一个实例；
图8-图9示出了如何实现包括有图1的带有不分层的第一鳍的第一FinFET以及图3的具有分层的鳍的第三FinFET的实施例集成电路器件，从而形成SRAM单体单元的另一个实例；
图10-图11示出了如何实现包括有图1的带有不分层的第一鳍的第一FinFET以及图3的具有分层的鳍的第三FinFET的实施例集成电路器件，从而形成SRAM单体单元的又一个实例
图12-图14示出了包括有图1的带有不分层的第一鳍的第一FinFET以及图3的具有分层的鳍的第三FinFET的实施例集成电路，以及器件的外延轮廓；
图15-图17示出了可以应用于实施例SRAM单体单元的线末端(BEOL)布线方案的实施例；
图18a-图18f示意性地示出了一种形成实施例集成电路的方法，该集成电路在共用的衬底上具有图1的带有不分层的鳍的第一FinFET以及图3的带有分层的鳍的第三FinFET。
除非另行指出，不同的视图中的相应的标号和标记大体上涉及了相应的部分。视图被绘制用于清楚地示出各个实施例的相关方面，无需按比例进行绘制。
具体实施方式
下面，详细讨论本发明各实施例的制造和使用。然而，应该理解，本发明提供了许多可以在各种具体环境中实现的可应用的概念。所讨论的具体实施例仅仅示出了制造和使用本发明的具体方式，而不用于限制本发明的范围。
将借助实施例在具体的语境，即，被单个衬底所支撑，但每个鳍均具有不同的鳍轮廓的双鳍式场效应晶体管(FinFET)中描述本发明。然而，本发明的实施例也可以应用于多种半导体器件。在下文中，将借助附图详细解释多个实施例。
现参考图1，示出了第一FinFET 10。第一FinFET器件10包括从下面的衬底14中向外突起并且嵌在氧化层16或其他适合的绝缘区域(例如，浅沟槽隔离(STI)区域)内的第一鳍12。另外，第一FinFET器件10还包括形成在位于源极/漏极区域20之间的第一鳍12上方的栅电极结构18。如所示，第一鳍12的鳍轮廓22(即，周边)从顶部到底部大体上是一致的。换言之，第一鳍22的相对的侧壁不包括台阶或凸肩。例如，第一鳍12在此被称为具有不分层的鳍轮廓。
现参考图2，示出了第二FinFET 24。第二FinFET 24包括多个从下面的衬底28中向外突起并且嵌在氧化层30或其他适合的绝缘区域(例如，浅沟槽隔离(STI)区域)之内的第二鳍26。虽未示出，但第二FinFET 24器件也包括一个或多个形成在位于源极/漏极区域之间的第二鳍26上方的栅电极结构。如所示，每个第二鳍26均具有鳍轮廓32，该鳍轮廓32在第二鳍26的两侧上没有台阶或凸肩。换言之，第二鳍26的侧壁不包括台阶或凸肩。由此，第二鳍26在本文中还称为具有不分层(non-tiered)鳍轮廓。
现参考图3，示出了第三FinFET 34。第三FinFET 34包括多个从下面的衬底38中向外突起并且嵌在氧化层40或其他适合的绝缘区域(例如，浅沟槽隔离(STI)区域)之内的第三鳍36。第三FinFET 34还包括形成在位于源极/漏极区域(未示出)之间的第三鳍36上方的栅电极结构42。如所示，第三鳍36的鳍轮廓44从顶部到底部不一致。换言之，第三鳍36的相对的侧壁分别包括台阶或凸肩46。例如，第三鳍36在此被称为具有分层的鳍轮廓。
如图3所示，第三鳍36的上层50(即，第一段)的宽度48小于下层54(即，第二段)的宽度52。显然，在上层50和下层54在凸肩46处相交或具有界面。在一个实施例中，第三鳍36的下层54的宽度52是上层50的宽度48的至少两倍。在一个实施例中，上层50的高度56小于大约50纳米(50nm)。
如图3所示，一些第三鳍36可以设置在形成在衬底38中的p阱58上，而其他第三鳍36则设置在n阱60上。应该理解，取决于例如第一、第二和第三FinFET 10、24、34的掺杂，也可以想到其他阱配置。
现参考图4A和图4B，示出了实施例集成电路62。集成电路62在单个衬底64(图4A和图4B中分两部分示出)上包括带有不分层的鳍的FinFET(例如，图1的FinFET 10或图2的FinFET 24)以及另一个带有分层的鳍的FinFET(例如，图3的FinFET)。处于说明性目的，图4A和图4B中包括的FinFET与图1的FinFET与类似。尽管如此，应该理解，在另一个实施例中，与图2的FinFET 24类似的FinFET可以替代图1的FinFET10。
如下面将更全面地解释的那样，使用带有两个分层的和不分层的鳍的FinFET的集成电路62的配置允许在共享的衬底64上形成高密度电路(例如，静态随机存储(SRAM)单元，动态随机存储(DRAM)单元，闪存单元(fresh cell)，或SRAM上拉晶体管)以及速度临界电路(例如，逻辑器件、SRAM下拉晶体管，SRAM传输门栅晶体管)两者。例如，图4的集成电路提供了区域和器件两者的性能优化。
仍参考图4A和图4B，实施例集成电路器件62包括位于相同的衬底68上的第一FinFET 10(图1)和第三FinFET(图3)两者。因此，集成电路62包括多个其鳍轮廓22是不分层的第一鳍12以及多个其鳍轮廓44是分层的第三鳍36。如所示，部分地嵌入到STI区域66中的第一鳍12和第三鳍36均被栅电极结构68覆盖，并且均包括沟道区域70。另外，在第一鳍12和第三鳍36中形成了阱区域72。
另外，在一个实施例中，第一、第二和第三FinFET 10、24、34可以是p型的或n型的MOSFET器件。在一个实施例中，第一和第二FinFET 10、24两者以及第三FinFET 34都是p型的MOSFET。在一个实施例中，第一、第二和第三FinFET 10、24、34的源极/漏极区域可以由硅(Si)、锗(Ge)、硅锗(SiGe)、硅锗碳(SiGeC)或其一些组合形成。
在一个实施例中，图4中的第一鳍12具有从顶部到底部增大的宽度74。换言之，宽度74随着第一鳍12远离衬底64地突出而逐渐变尖或缩小。在另一个实施例中，第一鳍12可以具有在整个长度76上大体上保持不变的宽度74。
如图4A和图4B所示，在一个实施例中，多个第三鳍36的下层54(以虚线示出)合并在一起。尽管如此，每个第三鳍36在上层50和下层54的界面处仍包括台阶或凸肩46。合并的下层54的整体宽度78在大约30nm和大约5000nm之间，而上层50的宽度80在大约3nm和大约20nm之间。
现参考图5A和图5B，在一个实施例中，第一鳍12的鳍轮廓22在长度76上是不一致的。正如图5A和图5B所示，由鳍的底面和鳍的左侧壁形成的轮廓角约为75度，而由顶面和左侧壁形成的轮廓角约为90度。图5中的第一鳍12的中部82中的轮廓角约为84度。尽管角度不同，但图5中的鳍轮廓从顶部到底部仍是缓慢地过渡，由此第一鳍12被视为不分层的。换言之，第一鳍12不包括台阶或凸肩。仍参考图5，在一个实施例中，合并的第三鳍36的下层54的宽度84可以随着第三鳍36朝向衬底64而变大。
现参考图6-图7的一个实例，即，如何实现包括有带有不分层的第一鳍12的第一FinFET 10以及具有分层的鳍36的第三FinFET34的实施例集成电路86，从而形成SRAM的单体单元(unit cell)88。如所示，来自设置在衬底64中的n阱60上的第一FinFET 10的不分层的第一鳍12形成了上拉晶体管(PU-1，PU-2)。另外，来自设置在衬底64中的p阱58上的第三FinFET 34的分层的第三鳍36形成了下拉晶体管和通栅(pass gate)晶体管(PD-1，PD-2，PG-1，PG-2)。在一个实施例中，第一鳍12之一是伪鳍。
现参考图8-图9的另一个实例，即，如何实现包括有图1的带有不分层的第一鳍12的第一FinFET 10以及具有分层的鳍36的第三FinFET 34的实施例集成电路90，从而形成SRAM单体单元92。如所示，来自设置在衬底64中的n阱60上的第一FinFET 10的不分层的第一鳍12形成了上拉晶体管(PU-1，PU-2)。另外，来自已经合并并且设置在衬底64中的p阱58上的第三FinFET 34的分层的第三鳍36形成了下拉晶体管和传输门栅晶体管(PD-1，PD-2，PG-1，PG-2)。在一个实施例中，第一鳍12之一是伪鳍。
现参考图10-图11的另一个实例，即，如何实现包括有带有不分层的第一鳍12的第一FinFET 10以及具有分层的鳍36的第三FinFET 34的实施例集成电路94，从而形成SRAM单体单元96。图10-图11的集成电路94与图8-图9的集成电路90类似，除了如图10所示的形成了传输门栅晶体管(PG-1)的分层的鳍36之一在BL节点附近被截短以外。例如，被截短的鳍36并不延伸穿过PG-1附近的栅电极。因为被截短的鳍36较短，所以单体单元96的离子比可以具有改善的稳定性。在一个实施例中，第一鳍12之一是伪鳍。
现参考图12-图14，示出了包括有带有不分层的第一鳍12的第一FinFET 10以及带有第三鳍36的第三FinFET 34的实施例集成电路98。如图14所示，第一FinFET 10的沟道区域102上的源极/漏极区域100可以具有相对于第三FinFET 34的沟道区域106上的源极/漏极区域104较小的轮廓。应该意识到，具有各种不同形状和尺寸的不同轮廓可以被用在第一、第二和第三FinFET 10，24，34中。
现参考图15，在一个实施例中，可以将后段工艺(BEOL)布线方案108应用于SRAM单体单元，诸如，在本文中所公开的单体单元88，92，96。在另一个实施例中，可以使用图16所示的后段工艺(BEOL)布线方案或图17所示的后段工艺(BEOL)布线方案112。
整体参考图18a-图18f，示意性地示出了一种形成实施例集成电路的方法，该集成电路在共用的衬底上具有带有不分层的鳍的第一FinFET以及带有分层的鳍的第三FinFET。在图18a中，光刻胶114被放置在设置在衬底118上方的硬掩模层116上并且执行硬掩模蚀刻来图案化该硬掩模层。在图18b中，光刻胶114被去除，从而留下了部分硬掩模层116。然后，在图18c中，执行覆盖式蚀刻来部分地限定鳍120。在图18d中，第二光刻胶122被放置在部分地形成的鳍120和部分衬底118上。然后，执行硅蚀刻来蚀刻衬底118，从而限定出STI区域，进一步限定出鳍轮廓并且去除不使用的鳍、伪鳍、或不使用的晶体管。在图18c中，在部分结构上方形成了第三光刻胶126，从而保护分层的鳍，并且执行另一蚀刻来制造不分层的鳍。然后，如图18f所示，利用例如氧化物填充STI区域124，并且去除硬掩模层116的剩余部分，从而留下了在共用的衬底上具有带有不分层的鳍的第一FinFET 10以及带有分层的鳍的第三FinFET 34的集成电路。
在一个实施例中，提供了一种集成电路。该集成电路包括：衬底，由衬底支撑的第一FinFET器件，具有带有不分层轮廓(non-tiered fin profile)的第一鳍的第一FinFET器件，以及由衬底支撑的第二FinFET，具有带有分层鳍轮廓(tiered fin profile)的第二鳍的第二FinFET。
在一个实施例中，提供了一种集成电路，该集成电路包括：衬底，由衬底支撑的第一FinFET器件，具有在源极和漏极区域之间延伸并且设置在第一栅电极下方的第一鳍的第一FinFET器件，包括不分层鳍轮廓的第一鳍，以及由衬底支撑的第二FinFET，该第二FinFET器件具有在源极和漏极区域之间延伸并且设置在第二栅电极下方的第二鳍，该第二FinFET器件具有带有分层鳍轮廓的第二鳍。
在一个实施例中，提供了一种形成集成电路的方法。该方法包括在衬底上方形成第一FinFET，该第一FinFET具有带有不分层鳍轮廓的第一鳍，以及在衬底上方形成第二FinFET，该第二FinFET具有带有分层鳍轮廓的第二鳍。
尽管已经详细地描述了本发明及其优势，但应该理解，可以在不背离所附权利要求限定的本发明主旨和范围的情况下，做各种不同的改变，替换和更改。
而且，本申请的范围并不仅限于本说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员应理解，通过本发明，现有的或今后开发的用于执行与根据本发明所采用的所述相应实施例基本相同的功能或获得基本相同结果的工艺、机器、制造，材料组分、装置、方法或步骤根据本发明可以被使用。因此，所附权利要求应该包括在这样的工艺、机器、制造、材料组分、装置、方法或步骤的范围内。

Claims (10)

1.一种集成电路，包括：
衬底；
第一FinFET器件，由所述衬底支撑，所述第一FinFET器件包括具有不分层鳍轮廓的第一鳍；以及
第二FinFET器件，由所述衬底支撑，所述第二FinFET器件包括具有分层鳍轮廓的第二鳍。
2.根据权利要求1所述的集成电路，其中，所述第二鳍是具有分层鳍轮廓的所述第二FinFET器件的多个第二鳍中的一个。
3.根据权利要求1所述的集成电路，其中，所述第一FinFET器件应用于静态随机存取存储器单元、动态随机存取存储器单元、闪存单元和静态随机存取存储器上拉晶体管中的一种。
4.根据权利要求1所述的集成电路，其中，所述第二FinFET器件应用于逻辑器件、下拉晶体管和传输门晶体管中的一种。
5.根据权利要求1所述的集成电路，其中，所述第一FinFET器件和所述第二FinFET器件均是p型金属氧化物半导体场效应晶体管。
6.根据权利要求1所述的集成电路，其中，所述第一FinFET器件是用作第一静态随机存取存储器中的上拉晶体管的p型金属氧化物半导体场效应晶体管，而所述第二FinFET器件是用作第二静态随机存取存储器中的下拉晶体管和传输门晶体管中的一种的n型金属氧化物半导体场效应晶体管。
7.根据权利要求1所述的集成电路，其中，所述第一鳍的不分层轮廓沿着所述第一鳍的长度是不一致的。
8.根据权利要求1所述的集成电路，其中，所述第一FinFET器件是具有多个第一鳍的多栅极场效应晶体管，所述多个第一鳍具有不分层轮廓。
9.一种集成电路，包括：
衬底；
第一FinFET器件，由所述衬底支撑，所述第一FinFET器件具有在源极区域和漏极区域之间延伸并且设置在第一栅电极下方的第一鳍，所述第一鳍包括不分层鳍轮廓；以及
第二FinFET器件，由所述衬底支撑，所述第二FinFET器件具有在源极区域和漏极区域之间延伸并且设置在第二栅电极下方的第二鳍，所述第二FinFET器件包括具有分层鳍轮廓的第二鳍。
10.一种形成集成电路的方法，包括：
在衬底上方形成第一FinFET器件，所述第一FinFET器件包括具有不分层鳍轮廓的第一鳍；以及
在所述衬底上方形成第二FinFET，所述第二FinFET包括具有分层鳍轮廓的第二鳍。
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