TWI509778B - 積體電路及其製造方法 - Google Patents

積體電路及其製造方法 Download PDF

Info

Publication number
TWI509778B
TWI509778B TW102120057A TW102120057A TWI509778B TW I509778 B TWI509778 B TW I509778B TW 102120057 A TW102120057 A TW 102120057A TW 102120057 A TW102120057 A TW 102120057A TW I509778 B TWI509778 B TW I509778B
Authority
TW
Taiwan
Prior art keywords
fin
field effect
effect transistor
layered
fin field
Prior art date
Application number
TW102120057A
Other languages
English (en)
Other versions
TW201401488A (zh
Inventor
Jhon Jhy Liaw
Original Assignee
Taiwan Semiconductor Mfg Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Mfg Co Ltd filed Critical Taiwan Semiconductor Mfg Co Ltd
Publication of TW201401488A publication Critical patent/TW201401488A/zh
Application granted granted Critical
Publication of TWI509778B publication Critical patent/TWI509778B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/6681—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Description

積體電路及其製造方法
本發明係關於半導體製作，且特別是關於一種積體電路及其製造方法。
於如電腦、行動電話與其他之極大多數的電子裝置之中已有半導體裝置的應用。半導體裝置包括形成於半導體晶圓上之數個積體電路，而此些積體電路係由沉積多種材料之薄膜於半導體晶圓上及圖案化此些材料之薄膜所形成。上述積體電路包括了如金氧半導體電晶體(MOS transistor)之場效電晶體(FET)。
半導體工業之眾多目標之一為持續縮減單一場效電晶體之尺寸及增加其速度。為了達成此些目標，便發展出了鰭型場效電晶體(FinFET)或多重閘場效電晶體(multiple gate FET)。此些裝置不僅改善了元件密度，還改善閘極對通道的控制情形。
依據一實施例，本發明提供了一種積體電路，包括：一基板；一第一鰭型場效電晶體裝置，為該基板所支撐，該第一鰭型場效電晶體裝置包括具有一非分層鰭外型之一第一鰭部；以及一第二鰭型場效電晶體裝置，為該基板所支撐，該第二鰭型場效電晶體裝置包括具有一分層鰭外型之一第二 鰭部。
依據另一實施例，本發明提供了一種積體電路，包括：一基板；一第一鰭型場效電晶體，為該基板所支撐，該第一鰭型場效電晶體具有延伸於源極與汲極區域之間且設置於一第一閘電極下方之一第一鰭部，該第一鰭部具有一非分層鰭外型；以及一第二鰭型場效電晶體，為該基板所支撐，該第二鰭型場效電晶體具有延伸於源極與汲極區域之間且設置於一第二閘電極下方之一第二鰭部，該第二鰭部具有一分層鰭外型。
依據一實施例，本發明提供了一種積體電路之製造方法，包括：形成一第一鰭型場效電晶體於一基板上，該第一鰭型場效電晶體包括具有一非分層鰭外型之一第一鰭部；以及形成一第二鰭型場效電晶體於該基板上，該第二鰭型場效電晶體包括具有一分層鰭外型之一第二鰭部。
為讓本發明之上述目的、特徵及優點能更明顯易懂，下文特舉一較佳實施例，並配合所附的圖式，作詳細說明如下。
10‧‧‧第一鰭型場效電晶體
12‧‧‧第一鰭部
14‧‧‧基板
16‧‧‧氧化物層
18‧‧‧閘電極結構
20‧‧‧源極/汲極區
22‧‧‧鰭外型
24‧‧‧第二鰭型場效電晶體
26‧‧‧第二鰭部
28‧‧‧第二鰭型場效電晶體
30‧‧‧氧化物層
32‧‧‧鰭外型
34‧‧‧第三鰭型場效電晶體
36‧‧‧第三鰭部
38‧‧‧基板
40‧‧‧氧化物層
42‧‧‧閘電極結構
44‧‧‧鰭外型
46‧‧‧肩部
48‧‧‧寬度
50‧‧‧上方層
52‧‧‧寬度
54‧‧‧下方層
56‧‧‧高度
58‧‧‧p型井區
60‧‧‧n型井區
62‧‧‧積體電路
64‧‧‧基板
66‧‧‧淺溝槽隔離區
68‧‧‧閘電極結構
70‧‧‧通道區
72‧‧‧井區
74‧‧‧寬度
76‧‧‧長度
78‧‧‧寬度
80‧‧‧寬度
82‧‧‧中央部
84‧‧‧寬度
86‧‧‧積體電路
88‧‧‧記憶胞單元
90‧‧‧積體電路
92‧‧‧記憶胞單元
94‧‧‧積體電路
96‧‧‧記憶胞單元
98‧‧‧積體電路
100‧‧‧源極/汲極區
102‧‧‧通道區
104‧‧‧源極/汲極區
106‧‧‧通道區
108、110、112‧‧‧後段導線繞線機制
114‧‧‧光阻層
116‧‧‧硬罩幕層
118‧‧‧基板
120‧‧‧鰭部
122‧‧‧第二光阻層
124‧‧‧淺溝槽隔離區
126‧‧‧第三光阻層
128‧‧‧氧化物
第1圖顯示了依據本發明之一實施例之一種鰭型場效電晶體，其具有一非分層型鰭部；第2圖顯示了依據本發明之一實施例之一種鰭型場效電晶體，其具有數個非分層型鰭部；第3圖顯示了依據本發明之一實施例之一種鰭型場效電晶 體，其具有數個分層型鰭部；第4A-4B圖顯示了依據本發明之一實施例之一種積體電路裝置，其包括了位於一單一基板上之如第1圖所示之數個非分層型鰭部與如第3圖所示之數個分層型鰭部；第5A-5B圖顯示了依據本發明之一實施例之一種積體電路裝置，其包括了位於一單一基板上之如第1圖所示之數個非分層型鰭部與如第3圖所示之數個分層型鰭部；第6-7圖顯示了依據本發明之一實施例之一種積體電路裝置，顯示了如何於一單一基板上使用包括了如第1圖所示之數個非分層型鰭部與如第3圖所示之數個分層型鰭部以形成一靜態隨機存取記憶體(SRAM)之一記憶胞單元；第8-9圖顯示了依據本發明之另一實施例之一種積體電路裝置，顯示了如何於一單一基板上使用包括如第1圖所示之數個非分層型鰭部與如第3圖所示之數個分層型鰭部以形成一靜態隨機存取記憶體(SRAM)之一記憶胞單元；第10-11圖顯示了依據本發明之又一實施例之一種積體電路裝置，顯示了如何於一單一基板上使用包括如第1圖所示之數個非分層型鰭部與如第3圖所示之數個分層型鰭部以形成一靜態隨機存取記憶體(SRAM)之一記憶胞單元；第12-14圖顯示了依據本發明之一實施例之一種積體電路裝置，顯示了包括如第1圖所示之數個非分層型鰭部以及如第3圖所示之數個分層型鰭部，以及裝置之磊晶外型；第15-17圖顯示了後段導線製作之繞線機制之一實施例，其適用於SRAM記憶胞單元之實施例；以及 第18a-18f圖示意地繪示了一種積體電路之製造方法，其包括了如第1圖所示之數個非分層型鰭部與如第3圖所示之數個分層型鰭部。
本發明將藉由下文中包括為一單一基板所支撐之分別具有不同鰭外型之兩種鰭部之兩種鰭型場效電晶體之特定實施例進行描述。然而，本發明之實施例亦可用於多種的半導體裝置中。於下文中，將透過相關圖式以解說本發明之多個實施例。
請參照第1圖，顯示了一第一鰭型場效電晶體(FinFET)10。第一鰭型場效電晶體10包括自下方基板14朝上延伸且埋設於氧化物層16或其他適當區域(例如淺溝槽隔離物區)內之一第一鰭部(fin)12。此外，第一鰭型場效電晶體10亦包括形成於介於源極/汲極區20之間之第一鰭部12之上之一閘電極(gate electrode)結構18。如圖所示，第一鰭部12的鰭外型22(例如周圍)為自其頂部至底部為一致的。換句話說，第一鰭部12之相對側壁並不包括一步階(step)或一肩部(shoulder)。因此，第一鰭部12於下文中將稱做一非分層型(non-tiered)鰭外型。
請參照第2圖，顯示了一第二鰭型場效電晶體24。第二鰭型場效電晶體24包括了由下方基板28朝上形成且埋設於氧化物層30或其他隔離區(例如淺溝槽隔離物區)內之數個第二鰭部26。雖然並未顯示，第二鰭型場效電晶體24亦包括形成於介於源極/汲極區之間之此些第二鰭部26之上之一或多個閘電極結構。如圖所示，此些第二鰭部26分別包括於第二鰭部26 之相對側上不具有一步階(step)或一肩部(shoulder)之一鰭外型32。換句話說，第二鰭部26之此些側壁並不包括一步階或一肩部。因此，第二鰭部26於下文中將稱作一非分層型(non-tiered)鰭外型。
請參照第3圖，顯示了一第三鰭型場效電晶體34。此第三鰭型場效電晶體34包括了由下方基板38朝上形成且埋設於氧化物層40或其他隔離區(例如淺溝槽隔離物區)內之數個第三鰭部36。第三鰭型場效電晶體34亦包括形成於介於源極/汲極區(未顯示)之間之此些第三鰭部36之上之一或多個閘電極結構42。如圖所示，此些第三鰭部36分別具有由下往上為非一致之一鰭外型44。換句話說，第三鰭部36之此些側壁分別包括一步階(step)或一肩部(shoulder)。因此，第三鰭部36於下文中將稱作一分層型鰭外型。
如第3圖所示，第三鰭部36之一上方層50(即第一步階)之一寬度48係少於一下方層54(即第二步階)之一寬度52。特別地，上方層50與下方層54相交或於肩部46處具有一介面。於一實施例中，此些第三鰭部36之下方層54之寬度52至少為上方層50之寬度48的兩倍。於一實施例中，上方層50之高度56係少於約50奈米。
如第3圖所示，部分之此些第三鰭部36可沉積於形成於基板38內之一p型井區58之上，而其餘之第三鰭部36則位於一n型井區60之上。可以理解的是，亦可視第一鰭型場效電晶體10、第二鰭型場效電晶體24與第三鰭型場效電晶體34之摻雜情形而考量其他之井區型態的應用。
請參照第4圖，顯示了一積體電路62之實施例。積體電路62包括位於單一基板64上(顯示於第4圖內之兩個部分內)之具有數個非分層型鰭部之一鰭型場效電晶體(例如第1圖所示之鰭型場效電晶體10或第2圖所示之鰭型場效電晶體24)以及具有數個分層型鰭部之另一鰭型場效電晶體(例如第3圖所示之鰭型場效電晶體34)。基於解說之目的，於第4圖中繪示了相似於第1圖所示之鰭型場效電晶體10之一鰭型場效電晶體。即使如此，可以理解的是，於另一實施例中亦可採用相似於第2圖內之鰭型場效電晶體24以取代第1圖內之鰭型場效電晶體10。
於下文中將詳細解說此積體電路62之型態，其採用可形成於共用基板64上之兼具分層型鰭部與非分層型鰭部之數個鰭型場效電晶體、具有了高密度電路(例如靜態隨機存取記憶、動態隨機存取記憶體胞、一快閃記憶胞或一靜態隨機存取記憶體上拉電晶體)以及快速關鍵電路(例如邏輯裝置、一靜態隨機存取記憶體下拉電晶體、一靜態隨機存取記憶體開關電晶體)。因此，如第4圖所示之積體電路62提供了區域表現與裝置表現之最佳化情形。
請繼續參照第4圖，積體電路62包括了位於相同基板64上之第一鰭型電晶體10(第1圖所示)以及第三鰭型電晶體34(第3圖所示)。如此，積體電路62包括了鰭外型22為非分層型之數個第一鰭部12，以及鰭外形44為分層型之數個第三鰭部36。如圖所示，此些第一鰭部36與此些第三鰭部36係部分地埋設於淺溝槽隔離區66之下，且為一閘電極結構68所覆蓋並包括 一通道區70。此外，於此些第一鰭部12與此些第三鰭部36之內形成有數個井區72。
此外，於一實施例中，第一鰭型場效電晶體10、第二鰭型場效電晶體24與第三鰭形場效電晶體34可為P型或N型之金氧半導體場效電晶體(MOSFET)裝置。於一實施例中，第一鰭型場效電晶體10與第二鰭型場效電晶體24以及第三鰭型場效電晶體34皆為P型金氧半導體場效電晶體。於一實施例中，第一鰭型場效電晶體10、第二鰭型場效電晶體24與第三鰭型場效電晶體34之源極/汲極區可由矽、鍺、矽鍺、矽鍺碳(SiGeC)或其組合所形成。
於一實施例中，第4圖內之此些第一鰭部12具有由上往下增加之一寬度74。換句話說，此寬度74沿自第一鰭部12遠離基板64之一方向逐漸變細或消失。於一實施例中，此些第一鰭部12可具有仍沿著一長度76上維持固定之一寬度74。
如第4圖所示，於一實施例中，數個第三鰭部36(其採用虛線顯示)之下方層54係聚合在一起。縱使如此，此些第三鰭部36仍分別包括上方層50與下方層54之一介面處之一步階或一肩部。聚合的下方層54之整體寬度78約介於30-5000奈米，而上分層50之寬度80則約為3-20奈米。
請參照第5圖，於一實施例中，第一鰭部12之一鰭外型22於長度76上為非一致的。的確，如第5圖所示，由鰭部之底面與鰭部之左方側壁所形成之一夾角約為75度，而由頂面與一左方側壁所形成之夾角約為90度。於第5圖內第一鰭部12之一中央部82之夾角位約為84度。不管此些不同的角度，第5 圖內之鰭外型仍自上至下順應地變化，因而使得第一鰭部12仍可視為非分層型。換句話說，第一鰭部12並不包括一步階或一肩部。請繼續參照第5圖，於一實施例中，聚合的第三鰭部36之下方層54之寬度84可隨著此些第三鰭部36朝向接近基板62之方向而增加。
請參照第6-7圖，顯示了如何採用包括具有非分層型之數個第一鰭部12之第一鰭型場效電晶體10以及具有分層型之數個第三鰭部36之第三鰭型場效電晶體34之一積體電路86以形成一靜態隨機存取記憶體(SRAM)之一記憶胞單元88之一範例。如圖所示，第一鰭型場效電晶體10之非分層型之第一鰭部12係設置於基板64內之一N型井區60之上，以形成了數個上拉電晶體(pull-up transistors，PU-1、PU-2)。此外，第三鰭型場效電晶體之分層型之數個第三鰭部36係設置於基板64內之一P型井區58之上，以形成了數個下拉與開關電晶體(pull-down and pass gate transistors，PD-1、PD-2、PG-1、PG-2)。於一實施例中，此些第一鰭部12其中之一為一假鰭部(dummy fin)。
請參照第8-9圖，顯示了如何採用包括具有非分層型之數個第一鰭部12之第一鰭型場效電晶體10以及具有分層型之數個第三鰭部36之第三鰭型場效電晶體34之一積體電路90以形成一靜態隨機存取記憶體(SRAM)之一記憶胞單元92之另一範例。如圖所示，第一鰭型場效電晶體10之非分層型之數個第一鰭部12係設置於基板64內之一N型井區60之上，以形成了數個上拉電晶體(PU-1、PU-2)。此外，第三鰭型場效電晶體 之分層型之數個第三鰭部36已聚合在一起並設置於基板64內之一P型井區58之上，以形成了數個下拉與開關電晶體(PD-1、PD-2、PG-1、PG-2)。於一實施例中，此些第一鰭部12其中之一為一假鰭部。
請參照第10-11圖，顯示了如何採用包括具有非分層型之數個第一鰭部12之第一鰭型場效電晶體10以及具有分層型之數個第三鰭部36之第三鰭型場效電晶體34之一積體電路94以形成一靜態隨機存取記憶體(SRAM)之一記憶胞單元96之又一範例。如第10-11圖之積體電路92相似於如第7-9圖所示之積體電路86與90，除了如第10圖所示之數個分層型鰭部36所形成之鄰近於位元線節點之一開關電晶體(PG-1)為縮短的。如此，經縮短之分層型鰭部36並未延伸穿過鄰近於PG-1之閘電極。由於經縮短之分層型鰭部36為較短的，記憶胞單元96之離子比例(ion ratio)可具有較佳之穩定度。於一實施例中，此些第一鰭部12之一為一假鰭部。
請繼續參照第12-14圖，顯示了包括具有非分層型之數個第一鰭部12之第一鰭型場效電晶體10以及具有分層型之數個第三鰭部36之第三鰭型場效電晶體34之一積體電路98。如第14圖所示，位於第一鰭型場效電晶體10之通道區102之上的源極/汲極區100相較於位於第三鰭型場效電晶體34之通道區106之上的源極/汲極區104具有較小之外型。可以理解的是，於第一鰭型場效電晶體10、第二鰭型場效電晶體24與第三鰭型場效電晶體34內使用多種不同形狀與尺寸之不同外型。
請參照第15圖，顯示了可用於如在此揭示之記憶 胞單元88、92、96之SRAM記憶胞單元之後段導線(BEOL)繞線機制108之一實施例。於另一實施例中，可採用如第16圖所示之一後段導線繞線機制110，或如第17圖所示之後段導線繞線機制112。
請參照第18a-18f圖，示意地繪示了一種積體電路之製造方法，上述積體電路包括了數個非分層型鰭部之第一鰭型場效電晶體以及數個分層型鰭部之第二鰭型場效電晶體。請參照第18a圖，於設置於一基板118上之硬罩幕層116上沉積一光阻層114並施行一硬罩幕蝕刻以圖案化此硬罩幕層。請參照第18b圖，移除光阻層114以於硬罩幕層116上留下數個部分。接著，於第18c圖中，施行一坦覆性蝕刻以部分地定義出數個鰭部120。請參照第18d圖，於此些部份形成之鰭部120與基板118之一部分上形成一第二光阻層122。接著，施行一矽蝕刻以蝕刻基板118以定義出數個淺溝槽隔離區124，且更定義出鰭外型且移除不使用之鰭部、假鰭部、或不使用之電晶體。請參照第18e圖，於此結構之上數個部分上形成一第三光阻層126以保護分層型鰭部，並施行另一蝕刻以製作出非分層型鰭部。接著，如第18f圖所示，於此些淺溝槽隔離區124內填入氧化物128，並移除其餘部分之硬罩幕層116，進而於共用基板上留下了具有具有非分層型鰭部之第一鰭型場效電晶體10以及具有數個分層型鰭部之第三鰭型場效電晶體34之一積體電路。
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何熟習此項技藝者，在不脫離本發明之精神和範圍內，當可作更動與潤飾，因此本發明之保護範圍當視 後附之申請專利範圍所界定者為準。
10‧‧‧第一鰭型場效電晶體
12‧‧‧第一鰭部
22‧‧‧鰭外型
34‧‧‧第三鰭型場效電晶體
36‧‧‧第三鰭部
44‧‧‧鰭外型
46‧‧‧肩部
50‧‧‧上方層
54‧‧‧下方層
62‧‧‧積體電路
64‧‧‧基板
66‧‧‧淺溝槽隔離區
68‧‧‧閘電極結構
70‧‧‧通道區
72‧‧‧井區
76‧‧‧長度
74、78、80‧‧‧寬度

Claims (10)

  1. 一種積體電路，包括：一基板；一第一鰭型場效電晶體裝置，為該基板所支撐，該第一鰭型場效電晶體裝置包括具有一非分層鰭外型之一第一鰭部；一第二鰭型場效電晶體裝置，為該基板所支撐，該第二鰭型場效電晶體裝置包括具有一分層鰭外型之一第二鰭部與一第三鰭部，且該第二鰭部與該第三鰭部各自具有一上方層；以及一介電層，自該第二鰭部的該上方層連續性地延伸至該第三鰭部的該上方層。
  2. 如申請專利範圍第1項所述之積體電路，其中該第一鰭型場效電晶體裝置係用於一靜態隨機存取記憶胞、一動態隨機存取記憶胞與一靜態隨機存取記憶上拉電晶體其中之一內，而該第二鰭型場效電晶體係用於一邏輯裝置、一下拉電晶體與一存取記憶體其中之一內。
  3. 如申請專利範圍第1項所述之積體電路，其中該第一鰭型場效電晶體裝置與該第二鰭型場效電晶體裝置皆為P型金氧半導體場效電晶體。
  4. 如申請專利範圍第1項所述之積體電路，其中該第一鰭型場效電晶體裝置為一P型金氧半導體場效電晶體，以作為一第一靜態隨機存取記憶體內之一上拉電晶體，而該第二鰭型場效電晶體裝置為一N型金氧半導體場效電晶體，以作為一 第二靜態隨機存取記憶體內之一下拉電晶體與一開關電晶體其中之一。
  5. 如申請專利範圍第1項所述之積體電路，其中該第一鰭部之該非分層鰭外型於該第一鰭部之一長度上為非一致的，而具有該分層鰭外型之該第二鰭部之一下方層之一寬度至少為該第二鰭部之一上方層之一寬度的兩倍。
  6. 一種積體電路，包括：一基板；一第一鰭型場效電晶體，為該基板所支撐，該第一鰭型場效電晶體具有延伸於源極與汲極區域之間且設置於一第一閘電極下方之一第一鰭部，該第一鰭部具有一非分層鰭外型；以及一第二鰭型場效電晶體，為該基板所支撐，該第二鰭型場效電晶體具有延伸於源極與汲極區域之間且設置於一第二閘電極下方之一第二鰭部，該第二鰭部具有一分層鰭外型，其中該第二閘電極僅圍繞該第二鰭部的一上方層。
  7. 如申請專利範圍第6項所述之積體電路，其中具有該分層鰭外型之該第二鰭部之一下方層之一寬度至少為該第二鰭部之一上方層之一寬度之兩倍，該第一鰭部之該非分層鰭外型於該第一鰭部之一長度上為非一致的。
  8. 如申請專利範圍第6項所述之積體電路，其中該第一鰭型場效電晶體裝置係位於具有一第一摻雜類型之一第一井區之上，而該第二鰭型場效電晶體係位於具有一第二摻雜類型之一第二井區之上。
  9. 如申請專利範圍第6項所述之積體電路，其中該第一鰭型場效電晶體形成了一上拉電晶體，該第二鰭型場效電晶體至少形成了一下拉電晶體與一開關電晶體其中之一。
  10. 一種積體電路之製造方法，包括：形成一第一鰭型場效電晶體於一基板上，該第一鰭型場效電晶體包括具有一非分層鰭外型之一第一鰭部；形成一第二鰭型場效電晶體於該基板上，該第二鰭型場效電晶體包括具有一分層鰭外型之一第二鰭部與一第三鰭部，且該第二鰭部與該第三鰭部各自具有一上方層；以及形成一介電層，該介電層自該第二鰭部的該上方層連續性地延伸至該第三鰭部的該上方層。
TW102120057A 2012-06-29 2013-06-06 積體電路及其製造方法 TWI509778B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US13/537,770 US9583398B2 (en) 2012-06-29 2012-06-29 Integrated circuit having FinFETS with different fin profiles

Publications (2)

Publication Number Publication Date
TW201401488A TW201401488A (zh) 2014-01-01
TWI509778B true TWI509778B (zh) 2015-11-21

Family

ID=49754248

Family Applications (1)

Application Number Title Priority Date Filing Date
TW102120057A TWI509778B (zh) 2012-06-29 2013-06-06 積體電路及其製造方法

Country Status (5)

Country Link
US (2) US9583398B2 (zh)
KR (1) KR101393947B1 (zh)
CN (1) CN103515390B (zh)
DE (1) DE102013105074B4 (zh)
TW (1) TWI509778B (zh)

Families Citing this family (53)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8987835B2 (en) * 2012-03-27 2015-03-24 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET with a buried semiconductor material between two fins
EP2717316B1 (en) * 2012-10-05 2019-08-14 IMEC vzw Method for producing strained germanium fin structures
US8753940B1 (en) * 2013-03-15 2014-06-17 Globalfoundries Inc. Methods of forming isolation structures and fins on a FinFET semiconductor device
US9048123B2 (en) * 2013-09-19 2015-06-02 International Business Machines Corporation Interdigitated finFETs
US9209178B2 (en) * 2013-11-25 2015-12-08 International Business Machines Corporation finFET isolation by selective cyclic etch
US9318488B2 (en) * 2014-01-06 2016-04-19 Taiwan Semiconductor Manufacturing Company Limited Semiconductor device and formation thereof
US9793268B2 (en) * 2014-01-24 2017-10-17 Taiwan Semiconductor Manufacturing Company, Ltd. Method and structure for gap filling improvement
KR102193493B1 (ko) * 2014-02-03 2020-12-21 삼성전자주식회사 반도체 장치 및 그 제조 방법
WO2015157501A1 (en) * 2014-04-10 2015-10-15 Alphabet Energy, Inc. Ultra-long silicon nanostructures, and methods of forming and transferring the same
US9941406B2 (en) 2014-08-05 2018-04-10 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs with source/drain cladding
US9324619B2 (en) 2014-08-25 2016-04-26 Samsung Electronics Co., Ltd. Semiconductor device and method of fabricating the same
US9299706B1 (en) 2014-09-25 2016-03-29 International Business Machines Corporation Single source/drain epitaxy for co-integrating nFET semiconductor fins and pFET semiconductor fins
KR102284888B1 (ko) 2015-01-15 2021-08-02 삼성전자주식회사 반도체 장치
KR102352155B1 (ko) * 2015-04-02 2022-01-17 삼성전자주식회사 반도체 소자 및 그 제조방법
CN106158748B (zh) * 2015-04-07 2022-01-18 联华电子股份有限公司 半导体元件及其制作方法
KR102310076B1 (ko) * 2015-04-23 2021-10-08 삼성전자주식회사 비대칭 소스/드레인 포함하는 반도체 소자
KR102389813B1 (ko) 2015-05-19 2022-04-22 삼성전자주식회사 반도체 소자
US9318392B1 (en) 2015-06-18 2016-04-19 International Business Machines Corporation Method to form SOI fins on a bulk substrate with suspended anchoring
WO2016207930A1 (ja) * 2015-06-24 2016-12-29 ルネサスエレクトロニクス株式会社 半導体装置
TWI647764B (zh) * 2015-07-01 2019-01-11 聯華電子股份有限公司 半導體元件及其製作方法
US9735164B2 (en) * 2015-10-15 2017-08-15 Globalfoundries Singapore Pte. Ltd. Low power embedded one-time programmable (OTP) structures
CN106601683B (zh) * 2015-10-15 2019-09-27 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制备方法、电子装置
KR102432464B1 (ko) 2015-11-18 2022-08-16 삼성전자주식회사 ＦｉｎＦＥＴ과 상기 ＦｉｎＦＥＴ의 핀 생성 방법
US9786505B2 (en) * 2015-12-30 2017-10-10 Taiwan Semiconductor Manufacturing Co., Ltd. FinFET device using dummy fins for smooth profiling
CN108431928B (zh) * 2015-12-31 2023-07-25 上海凯世通半导体股份有限公司 FinFET的掺杂方法
US10050043B2 (en) 2016-01-29 2018-08-14 Taiwan Semiconductor Manufacturing Co., Ltd. Static random access memory (SRAM) using FinFETs with varying widths of fin structures
KR102637621B1 (ko) 2016-05-25 2024-02-20 삼성전자주식회사 반도체 소자의 제조 방법
US10297555B2 (en) * 2016-07-29 2019-05-21 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit structure having crown-shaped semiconductor strips and recesses in the substrate from etched dummy fins
US10355110B2 (en) * 2016-08-02 2019-07-16 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET and method of forming same
US10032877B2 (en) * 2016-08-02 2018-07-24 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET and method of forming same
US10217741B2 (en) 2016-08-03 2019-02-26 Taiwan Semiconductor Manufacturing Company, Ltd. Fin structure and method of forming same through two-step etching processes
CN107706111B (zh) * 2016-08-09 2020-07-10 中芯国际集成电路制造(上海)有限公司 半导体器件的形成方法
US11088033B2 (en) * 2016-09-08 2021-08-10 International Business Machines Corporation Low resistance source-drain contacts using high temperature silicides
KR102330087B1 (ko) * 2017-04-03 2021-11-22 삼성전자주식회사 반도체 장치 및 이의 제조 방법
US10074732B1 (en) 2017-06-14 2018-09-11 Globalfoundries Inc. Methods of forming short channel and long channel finFET devices so as to adjust threshold voltages
CN109148451B (zh) * 2017-06-27 2021-09-07 联华电子股份有限公司 静态随机存取存储器单元阵列及其形成方法
US10658490B2 (en) 2017-07-28 2020-05-19 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of isolation feature of semiconductor device structure
US10276720B2 (en) * 2017-08-31 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming fin field effect transistor (FINFET) device structure
US10325811B2 (en) * 2017-10-26 2019-06-18 Globalfoundries Inc. Field-effect transistors with fins having independently-dimensioned sections
US10529712B2 (en) * 2017-11-07 2020-01-07 Samsung Electronics Co., Ltd. Semiconductor device
CN109994471B (zh) * 2017-12-29 2020-12-22 中芯国际集成电路制造(上海)有限公司 半导体器件及其形成方法
CN109994548B (zh) * 2017-12-29 2021-12-14 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
US11404423B2 (en) * 2018-04-19 2022-08-02 Taiwan Semiconductor Manufacturing Co., Ltd Fin-based strap cell structure for improving memory performance
US10475791B1 (en) * 2018-05-31 2019-11-12 Globalfoundries Inc. Transistor fins with different thickness gate dielectric
US11177256B2 (en) * 2018-06-28 2021-11-16 Taiwan Semiconductor Manufacturing Company, Ltd. Odd-fin height cell regions, semiconductor device having the same, and method of generating a layout diagram corresponding to the same
US10964684B2 (en) * 2018-06-29 2021-03-30 Taiwan Semiconductor Manufacturing Company Ltd. Multiple fin height integrated circuit
CN110690218B (zh) * 2018-07-05 2022-07-05 中芯国际集成电路制造(上海)有限公司 半导体器件及其形成方法
CN111129142B (zh) * 2018-11-01 2023-06-13 中芯国际集成电路制造(上海)有限公司 半导体器件及其形成方法
US11264268B2 (en) * 2018-11-29 2022-03-01 Taiwan Semiconductor Mtaiwananufacturing Co., Ltd. FinFET circuit devices with well isolation
US10879125B2 (en) * 2018-12-27 2020-12-29 Nanya Technology Corporation FinFET structure and method of manufacturing the same
KR102582074B1 (ko) 2018-12-28 2023-09-21 삼성전자주식회사 반도체 장치 및 그 제조 방법
CN113555361A (zh) * 2020-04-23 2021-10-26 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
US11302567B2 (en) * 2020-06-30 2022-04-12 Taiwan Semiconductor Manufacturing Co., Ltd. Shallow trench isolation forming method and structures resulting therefrom

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080296702A1 (en) * 2007-05-30 2008-12-04 Tsung-Lin Lee Integrated circuit structures with multiple FinFETs
US20080308848A1 (en) * 2007-05-15 2008-12-18 Satoshi Inaba Semiconductor device
US20090039418A1 (en) * 2005-10-25 2009-02-12 Freescale Semiconductor, Inc. Multiple device types including an inverted-t channel transistor and method therefor

Family Cites Families (42)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7378710B2 (en) * 2002-12-19 2008-05-27 International Business Machines Corporation FinFET SRAM cell using inverted FinFET thin film transistors
US6909147B2 (en) * 2003-05-05 2005-06-21 International Business Machines Corporation Multi-height FinFETS
US6960517B2 (en) * 2003-06-30 2005-11-01 Intel Corporation N-gate transistor
KR100496891B1 (ko) * 2003-08-14 2005-06-23 삼성전자주식회사 핀 전계효과 트랜지스터를 위한 실리콘 핀 및 그 제조 방법
US7211864B2 (en) * 2003-09-15 2007-05-01 Seliskar John J Fully-depleted castellated gate MOSFET device and method of manufacture thereof
KR100555518B1 (ko) * 2003-09-16 2006-03-03 삼성전자주식회사 이중 게이트 전계 효과 트랜지스터 및 그 제조방법
JP2005116969A (ja) * 2003-10-10 2005-04-28 Toshiba Corp 半導体装置及びその製造方法
KR100518602B1 (ko) * 2003-12-03 2005-10-04 삼성전자주식회사 돌출된 형태의 채널을 갖는 모스 트랜지스터 및 그 제조방법
US7098477B2 (en) * 2004-04-23 2006-08-29 International Business Machines Corporation Structure and method of manufacturing a finFET device having stacked fins
US7719043B2 (en) * 2004-07-12 2010-05-18 Nec Corporation Semiconductor device with fin-type field effect transistor and manufacturing method thereof.
US7071064B2 (en) * 2004-09-23 2006-07-04 Intel Corporation U-gate transistors and methods of fabrication
US6949768B1 (en) 2004-10-18 2005-09-27 International Business Machines Corporation Planar substrate devices integrated with finfets and method of manufacture
KR100612419B1 (ko) 2004-10-19 2006-08-16 삼성전자주식회사 핀 트랜지스터 및 평판 트랜지스터를 갖는 반도체 소자 및그 형성 방법
KR100645053B1 (ko) * 2004-12-28 2006-11-10 삼성전자주식회사 증가된 활성영역 폭을 가지는 반도체 소자 및 그 제조 방법
KR100696197B1 (ko) * 2005-09-27 2007-03-20 한국전자통신연구원 실리콘 기판을 이용한 다중 게이트 모스 트랜지스터 및 그제조 방법
KR100675288B1 (ko) * 2005-11-04 2007-01-29 삼성전자주식회사 다중 채널 트랜지스터들을 갖는 반도체 소자의 제조방법들및 그에 의해 제조된 반도체 소자들
KR100675290B1 (ko) * 2005-11-24 2007-01-29 삼성전자주식회사 다중채널 전계효과트랜지스터 및 핀 전계효과트랜지스터를갖는 반도체소자의 제조방법 및 관련된 소자
US7754560B2 (en) * 2006-01-10 2010-07-13 Freescale Semiconductor, Inc. Integrated circuit using FinFETs and having a static random access memory (SRAM)
US7723805B2 (en) * 2006-01-10 2010-05-25 Freescale Semiconductor, Inc. Electronic device including a fin-type transistor structure and a process for forming the electronic device
DE102006001680B3 (de) * 2006-01-12 2007-08-09 Infineon Technologies Ag Herstellungsverfahren für eine FinFET-Transistoranordnung und entsprechende FinFET-Transistoranordnung
KR100739656B1 (ko) 2006-06-08 2007-07-13 삼성전자주식회사 반도체 장치의 제조 방법
JP2007335821A (ja) 2006-06-19 2007-12-27 Ricoh Co Ltd 半導体記憶装置
US7678648B2 (en) * 2006-07-14 2010-03-16 Micron Technology, Inc. Subresolution silicon features and methods for forming the same
US7880232B2 (en) * 2006-11-01 2011-02-01 Micron Technology, Inc. Processes and apparatus having a semiconductor fin
US20080157225A1 (en) * 2006-12-29 2008-07-03 Suman Datta SRAM and logic transistors with variable height multi-gate transistor architecture
US7737501B2 (en) * 2007-07-11 2010-06-15 International Business Machines Corporation FinFET SRAM with asymmetric gate and method of manufacture thereof
JP2009130210A (ja) * 2007-11-26 2009-06-11 Toshiba Corp 半導体装置
US8288756B2 (en) * 2007-11-30 2012-10-16 Advanced Micro Devices, Inc. Hetero-structured, inverted-T field effect transistor
EP2073256A1 (en) * 2007-12-20 2009-06-24 Interuniversitair Microelektronica Centrum vzw ( IMEC) Method for fabricating a semiconductor device and the semiconductor device made thereof
US7994020B2 (en) * 2008-07-21 2011-08-09 Advanced Micro Devices, Inc. Method of forming finned semiconductor devices with trench isolation
US8058692B2 (en) * 2008-12-29 2011-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Multiple-gate transistors with reverse T-shaped fins
JP2011009296A (ja) 2009-06-23 2011-01-13 Panasonic Corp 半導体装置及びその製造方法
US8264032B2 (en) * 2009-09-01 2012-09-11 Taiwan Semiconductor Manufacturing Company, Ltd. Accumulation type FinFET, circuits and fabrication method thereof
US8110466B2 (en) * 2009-10-27 2012-02-07 Taiwan Semiconductor Manufacturing Company, Ltd. Cross OD FinFET patterning
CN201628899U (zh) 2009-12-01 2010-11-10 鸿富锦精密工业（深圳）有限公司 扩充卡固定装置
US8426923B2 (en) 2009-12-02 2013-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Multiple-gate semiconductor device and method
US8258572B2 (en) * 2009-12-07 2012-09-04 Taiwan Semiconductor Manufacturing Company, Ltd. SRAM structure with FinFETs having multiple fins
US9130058B2 (en) * 2010-07-26 2015-09-08 Taiwan Semiconductor Manufacturing Company, Ltd. Forming crown active regions for FinFETs
US8349692B2 (en) * 2011-03-08 2013-01-08 Globalfoundries Singapore Pte. Ltd. Channel surface technique for fabrication of FinFET devices
KR101850703B1 (ko) * 2011-05-17 2018-04-23 삼성전자 주식회사 반도체 장치 및 그 제조 방법
US8609499B2 (en) * 2012-01-09 2013-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs and the methods for forming the same
US8603893B1 (en) * 2012-05-17 2013-12-10 GlobalFoundries, Inc. Methods for fabricating FinFET integrated circuits on bulk semiconductor substrates

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090039418A1 (en) * 2005-10-25 2009-02-12 Freescale Semiconductor, Inc. Multiple device types including an inverted-t channel transistor and method therefor
US20080308848A1 (en) * 2007-05-15 2008-12-18 Satoshi Inaba Semiconductor device
US20080296702A1 (en) * 2007-05-30 2008-12-04 Tsung-Lin Lee Integrated circuit structures with multiple FinFETs

Also Published As

Publication number Publication date
US20170194323A1 (en) 2017-07-06
US9583398B2 (en) 2017-02-28
CN103515390B (zh) 2016-10-05
TW201401488A (zh) 2014-01-01
US10340270B2 (en) 2019-07-02
CN103515390A (zh) 2014-01-15
KR101393947B1 (ko) 2014-05-12
US20140001562A1 (en) 2014-01-02
KR20140002449A (ko) 2014-01-08
DE102013105074A1 (de) 2014-01-02
DE102013105074B4 (de) 2022-11-10

Similar Documents

Publication Publication Date Title
TWI509778B (zh) 積體電路及其製造方法
US11342337B2 (en) Structure and method for FinFET SRAM
US10770467B2 (en) Semiconductor device and method for fabricating the same
US9502531B2 (en) Semiconductor device having fin-type field effect transistor and method of manufacturing the same
TWI692813B (zh) 半導體裝置的製造方法
KR101531795B1 (ko) ＦｉｎＦＥＴ를 위한 구조
TWI615945B (zh) 積體電路
TWI742626B (zh) 積體電路及形成半導體結構的方法
US10763863B2 (en) Semiconductor device for logic and memory co-optimization
US9520297B2 (en) Semiconductor device and method of fabricating the same
US20180006040A1 (en) Static random-access memory (sram) cell array and forming method thereof
US9455255B2 (en) Fin-type field effect transistor and manufacturing method thereof
US9941288B2 (en) Static random-access memory (SRAM) cell array
JP2022541409A (ja) ナノシートの直接印刷および自己整合ダブル・パターニング
US20220209774A1 (en) Semiconductor Device For Logic and Memory Co-Optimization
US9627389B1 (en) Methods to form merged spacers for use in fin generation in IC devices
CN109979881B (zh) 静态随机存取存储器的结构及其形成方法
CN109979942B (zh) 静态随机存取存储器及其形成方法
US8653571B2 (en) Semiconductor device
Singh et al. FinFET Fin-Trimming During Replacement Metal Gate for an Asymmetric Device Toward STT MRAM Performance Enhancement
US20190172832A1 (en) Finfet sram layout and method of making the same