CN101836191A - 使用多校验节点算法的纠错解码器 - Google Patents
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Abstract
在一个实施例中,一种LDPC解码器具有控制器和一个或更多个校验节点单元(CNU)。CNU使用缩放最小和算法、偏移最小和算法、或缩放和偏移最小和算法来生成校验节点消息。在最初时,控制器选择缩放因子和偏移值。对于无缩放,缩放因子可被设定为1,并且对于无偏移,偏移值可被设定为0。如果解码器未能正确地对码字解码,则(i)控制器选择新的缩放因子和/或偏移值,以及(ii)解码器尝试使用新的缩放和偏移值来对码字正确解码。通过改变缩放因子和/或偏移值,较之仅使用固定的缩放因子或没有缩放因子或者仅使用固定的偏移因子或没有偏移因子的LDPC解码器,本发明的LDPC解码器能够改进错误平层特性。
Description
相关申请的交叉引用
本申请要求在2008年8月15日提交的美国临时申请No.61/089,297、代理人案号08-0241的优先权,通过引用将其整体教导合并于此。
本申请的主题内容涉及在2008年5月1日提交的美国专利申请No.12/113,729、在2008年5月1日提交的美国专利申请No.12/113,755、在2008年11月26日提交的美国专利申请No.12/323,626、在2009年3月10日提交的美国专利申请No.12/401,116、在2008年12月12日提交的PCT专利申请No.PCT/US08/86523和在2008年12月12日提交的PCT专利申请No.PCT/US08/86537,通过引用将其整体教导合并于此。
技术领域
本发明涉及信号处理,并具体地,涉及诸如低密度奇偶校验(LDPC)编码和解码的纠错编码和解码技术。
背景技术
在对码字解码时,低密度奇偶校验(LDPC)解码器可能遇到一个或更多个陷阱集(trapping set),其阻碍解码器正确地对码字解码。陷阱集表示LDPC码的Tanner图中的子图,由于陷阱集可迫使解码器收敛于不正确的结果,因此陷阱集典型地对LDPC码的错误平层(error-floor)特性有强烈的影响。为了改进错误平层特性,LDPC解码器可以使用不同的技术打破主陷阱集(即典型地对错误平层特性有最显著的影响的陷阱集)。这些主陷阱集基于诸如解码器字符表(decoderalphabet)、解码器算法、解码器校验节点单元更新、信道条件和信号条件等解码器的操作条件而广泛地变化。
发明内容
在一个实施例中,本发明是一种用于对纠错(EC)编码的码字解码以恢复正确码字的方法。该方法选择缩放因子和偏移值,以及从上游处理器接收初始值的初始集合。初始值的初始集合对应于EC编码的码字,并且初始集合中的每个初始值对应于EC编码的码字的不同比特。基于初始值的初始集合生成第一消息集合,以及基于缩放因子和偏移值将第一消息集合转换为经缩放和偏移的消息。
在另一实施例中,本发明是一种用于执行上述方法的装置。该装置包括纠错(EC)解码器,用于对EC编码的码字解码以恢复正确码字。解码器生成第一消息集合,并包括:(i)一个或更多个模块,适于基于缩放因子和偏移值将第一消息集合转换为经缩放和偏移的消息,以及(ii)控制器,适于选择缩放因子和偏移值。
附图说明
通过以下详细描述、所附权利要求和附图,本发明的其他方面、特征和优点将变得更加明显,在附图中相同的附图标记表示相似或相同的要素。
图1示出了可用于实现正则的、准循环(quasi-cyclic,QC)低密度奇偶校验(LDPC)码的奇偶校验H矩阵的一个实现方案;
图2示出了根据本发明的一个实施例的LDPC解码器的简化框图,该解码器可用于对使用H矩阵(诸如图1的H矩阵)编码的信号进行解码;以及
图3示出了校验节点单元(CNU)的一个实现方案的简化框图,该校验节点单元可用于实现图2的LDPC解码器的每个CNU。
具体实施方式
此处提到“一个实施例”或“实施例”意指结合实施例描述的特定特征、结构或特性可包括在本发明的至少一个实施例中。在本说明书各处出现的用语“在一个实施例中”并不必然都意指同一实施例,分立的或替选的实施例也并不必然互相排斥其他的实施例。这同样适用于术语“实现方案”。
通过改变LDPC解码器使用的校验节点算法可以改进LDPC解码器的错误平层特性。典型地,使用特定的校验节点算法导致的陷阱集不同于使用其他校验节点算法导致的陷阱集。因此,例如,可以通过使校验节点算法从偏移最小和(offset min-sum)算法改变为缩放最小和(scaled min-sum)算法,获得不同的陷阱集。也可以通过改变偏移最小和算法使用的偏移值,或者通过改变缩放最小和算法使用的缩放因子,获得不同的陷阱集。
图1示出了可用于实现正则的、准循环(QC)低密度奇偶校验(LDPC)码的奇偶校验矩阵100的一个实现方案。奇偶校验矩阵100通常被称为H矩阵,包括40个循环矩阵(circulant)Bj,k,它们被排列为r=4个循环矩阵行(即,块行),其中j=1、...、r,和c=10个循环矩阵列(即,块列),其中k=1、...、c。循环矩阵是子矩阵,该子矩阵是单位矩阵或者是通过对单位矩阵循环移位而获得的,并且准循环LDPC码是其中所有子矩阵均为循环矩阵的LDPC码。在H矩阵100中,每个循环矩阵Bj,k是p×p的子矩阵,其可以通过对单个p×p单位矩阵循环移位而获得。出于这里讨论的目的,假设p=72,从而使H矩阵100具有总共p×r=72×4=288个行以及总共p×c=72×10=720个列。由于每个循环矩阵Bj,k是单位矩阵的置换,因此循环矩阵中的每个列的汉明权重(即,具有值1的元的数目)以及循环矩阵中的每个行的汉明权重均等于1。因此,H矩阵100的每个行的总汉明权重wr等于1×c=1×10=10,并且H矩阵100的每个列的总汉明权重wc等于1×r=1×4=4。H矩阵100的288个行中的每个行对应于第m个校验节点,其中m的范围是0、...、287,并且H矩阵100的720个列中的每个列对应于第n个变量节点(也被称为比特节点),其中n的范围是0、...、719。再者,每个校验节点连接到如行中的l所表示的wr=10个变量节点,并且每个变量节点连接到如列中的l表示的wc=4个校验节点。由于H矩阵100的所有行具有相同的汉明权重wr并且H矩阵100的所有列具有相同的汉明权重wc,因此H矩阵100可被描述为正则LDPC码。
图2示出了根据本发明的一个实施例的LDPC解码器200的简化框图,该解码器可用于对使用H矩阵(诸如图1的H矩阵100)编码的码字进行解码。对于接收到的每个码字,LDPC解码器200(i)从可以执行例如射频处理、模数转换、均衡、诸如Viterbi检测的信道检测、或适于生成软输出值的其他处理的上游处理器接收720个软值(例如,对数似然比(LLR))Ln (0),并且(ii)将这些软值Ln (0)存储在软值存储器202中。上游处理器执行的处理可以取决于其中实现LDPC解码器200的特定应用。每个软值Ln (0)对应于码字的一个比特,并且使用消息传递算法迭代地对每个码字解码。对于这里的讨论,假设每个软值Ln (0)具有五个比特,包括一个硬判决比特和四比特的置信值。
通常,LDPC解码器200使用块串行消息传递方案(block-serialmessage-passing schedule)对720个软值Ln (0)(即,消息)解码。使用以下更新消息:(i)288个校验节点单元(CNU)210,其中每个CNU210执行关于H矩阵100的一个行(即,第m个校验节点)的校验节点更新,和(ii)72个五比特的变量节点单元(VNU)204,其中每个VNU 204执行关于H矩阵100的十个列(即,第n个变量节点)的变量节点更新。CNU 210(0)、...、210(287)一次一个块列地执行对于H矩阵100的288个行的校验节点(即,行)更新,从而执行对于第一块列(即,循环矩阵B1,1、B2,1、B3,1和B4,1)的校验节点更新,随后执行对于第二块列(即,循环矩阵B1,2、B2,2、B3,2和B4,2)的校验节点更新,随后执行对于第三块列(即,循环矩阵B1,3、B2,3、B3,3和B4,3)的校验节点更新,以此类推。然后VNU 204(0)、...、204(71)一次一个块列地执行对于H矩阵100的720个列的变量节点(即,列)更新,从而执行对于第一块列(即,循环矩阵B1,1、B2,1、B3,1和B4,1)的变量节点更新,随后执行对于第二块列(即,循环矩阵B1,2、B2,2、B3,2和B4,2)的变量节点更新,随后执行对于第三块列(即,循环矩阵B1,3、B2,3、B3,3和B4,3)的变量节点更新,以此类推。在所有校验节点更新和变量节点更新均被执行之后,LDPC解码器200的迭代(即,局部迭代)完成。
在最初时,以每个时钟周期72个软值Ln (0)的速率向四个多路复用器206(0)、...、206(3)提供720个五比特的软值Ln (0),从而使每个多路复用器206接收集合中的所有72个软值Ln (0)。每个多路复用器206还从VNU 204(0)、...、204(71)接收72个五比特的变量节点消息(在此处被称为Q消息),该消息是如下文更详细讨论的而生成的。在LDPC解码器200的首次迭代期间,多路复用器206(0)、...、206(3)分别选择它们接收的72个五比特的软值Ln (0)的集合,以分别向72路循环移位器208(0)、...、208(3)输出。未被选择的初始的Q消息可以是针对先前考虑的码字而生成的Q消息。在LDPC解码器200的随后的迭代期间,多路复用器206(0)、...、206(3)分别选择它们从VNU 204(0)、...、204(71)接收的72个五比特的Q消息的集合,以分别向72路循环移位器208(0)、...、208(3)输出。对于后面的讨论,将理解,任何对Q消息的引用适用于在LDPC解码器200的首次迭代期间的软值Ln (0)。
循环移位器208(0)、...、208(3)基于可以从例如控制器214接收的循环移位信号,使它们接收的72个五比特的Q消息的集合循环移位。该循环移位信号对应于图1的H矩阵100的循环矩阵的循环移位因子。例如,在LDPC解码器200的迭代的首个时钟周期期间,循环移位器208(0)、...、208(3)可以分别基于图1的H矩阵100的循环矩阵B1,1、B2,1、B3,1和B4,1的移位因子,使它们各自的72个五比特的Q消息的集合移位。在LDPC解码器200的迭代的第二个时钟周期期间,循环移位器208(0)、...、208(3)分别基于循环矩阵B1,2、B2,2、B3,2和B4,2的移位因子,使它们各自的72个五比特的Q消息的集合移位。循环移位器208(0)、...、208(3)随后向CNU 210(0)、...、210(287)提供它们各自的72个经循环移位的五比特的Q消息,从而使每个CNU 210接收Q消息中的不同的一个Q消息。
每个CNU 210(i)以每个时钟周期一个Q消息的速率接收数目等于H矩阵100的行的汉明权重wr(例如,10)的五比特的Q消息,并且(ii)生成wr个五比特的校验节点消息(此处被称为R消息)。每个CNU 210是可有选择地配置为使用如下算法生成R消息的:(i)偏移最小和校验节点算法、(ii)缩放最小和校验节点算法、或(iii)应用于偏移和缩放两者的最小和校验节点算法。每个R消息可被表示为如下所示的式(1)、(2)和(3):
其中(i)Rmn (i)表示用于LDPC解码器200的第i次迭代的与图1的H矩阵100的第m个校验节点(即,行)和第n个变量节点(即,列)对应的R消息,(ii)Qnm (i-1)表示用于第(i-1)次迭代的与H矩阵100第n个变量节点和第m个校验节点对应的Q消息,(iii)α表示缩放因子,其范围为0~1,(iv)β表示偏移值,其范围是0~15,以及(v)函数sign表示对Qnm (i-1)消息的符号执行乘法运算(即,II)。假设n′是除了第n个变量节点外的连接到第m个校验节点的所有变量节点的集合N(m)/n中的变量节点(即,n′∈N(m)/n)。对应于第m个校验节点(即,行)的CNU 210基于在先前的第(i-1)次迭代期间从集合N(m)/n接收的所有Q消息生成消息Rmn (i)。因此,在图2的实施例中,基于N(m)/n=9个Q消息(即,wr-1=10-1)生成每个R消息。应当注意,对于首次迭代,在式(2)和(3)中使用从软值存储器202接收到的软值Ln (0)代替用于前一次迭代的Q消息(即,)。
例如,可由控制器214选择每个CNU 210使用的特定算法。例如,为了实现无缩放的偏移最小和校验节点算法,控制器214可以选择1的缩放因子α,从而使CNU 210不执行缩放,并且选择除0以外的偏移值β。为了实现无偏移的缩放最小和校验节点算法,控制器214可以选择0的偏移值β,从而使CNU 210不执行偏移,并且选择除1以外的缩放因子α。为了实现执行缩放和偏移两者的最小和校验节点算法,控制器214可以选择除0以外的偏移值β和除1以外的缩放因子α。在最初时,控制器214选择所期望的偏移和缩放因子。随后,控制器214可以例如从LDPC解码器200的一次迭代(即,一次局部迭代)到下一次迭代地,从LDPC码的一个层到下一个层地,从一个码字到下一个码字地,以及从一次全局迭代(下文进一步描述)到下一次全局迭代地,改变偏移和缩放因子。
图3示出了根据本发明的一个实施例的CNU 300的简化框图,其可用于实现图2的LDPC解码器200的每个CNU 210。通常,CNU300生成10个五比特的R消息,其中每个五比特的R消息是使用N(m)/n=9个Q消息(如上文所述排除了一个消息)的集合而生成的。对于这10个五比特的R消息中的9个消息,使用式(2)生成的Q消息的最小幅度(magnitude)是相同的。对于这些R消息中的一个消息,由于Q消息的最小幅度将被如上所述从计算排除,因此Q消息的最小幅度将是Q消息的第二小幅度。不同于执行式(2)10次,对于10个五比特的R消息中的每个R消息执行一次,CNU 300实现了值再利用技术,其中CNU 300(i)使用M1_M2寻找器302确定具有最小和第二小的幅度的Q消息并且(ii)基于最小和第二小的幅度生成10个五比特的R消息。
在最初的10个时钟周期中的每个时钟周期期间,M1_M2寻找器302接收具有2的补码格式的五比特的Q消息。可以使用缩放和偏移逻辑模块310来使五比特的Q消息缩放和/或偏移。可以在CNU 300中的多种位置应用缩放和/或偏移。例如,可以由缩放和偏移逻辑模块334或346应用缩放和/或偏移,替代由缩放和偏移逻辑模块310执行的缩放和/或偏移。可替选地,可以由缩放和偏移逻辑模块310、334和346中的两个或更多个缩放和偏移逻辑模块应用缩放和/或偏移。缩放因子(例如,α1、α2、α3)和/或偏移值(例如,β1、β2、β3)可由例如图2的控制器214提供。当使用缩放和偏移逻辑模块310、334和346中的两个或更多个缩放和偏移逻辑模块时,从一个缩放和偏移逻辑模块到下一个缩放和偏移逻辑模块,缩放因子和偏移值可以是不同的。作为另一替选方案,可以在与偏移不同的位置应用缩放。当在不同位置中由不同模块执行缩放和偏移时,可以称之为,不同的模块基于缩放因子和偏移值将消息转换为经缩放和偏移的消息。例如,如果模块310执行缩放并且模块346执行偏移,则模块310和346可被称为将Q消息转换为经缩放和偏移的R消息。
M1_M2寻找器302使用2的补码到符号-幅度(2TSM)转换器312将每个可能经缩放和/或偏移的Q消息从2的补码格式转换为五比特的符号-幅度值。符号-幅度值的符号比特326被提供给符号处理逻辑328,该符号处理逻辑328(i)生成所有10个Q消息的符号比特326的积并且(ii)将每个符号比特326乘以该积以对于10个R消息中的每个R消息生成不同的符号比特332。五比特的符号-幅度值Q[4:0]的四比特的幅度|Q|[3:0]连同分别存储在部分状态存储器304的部分状态寄存器330(0)和330(1)中的四比特的最小幅度值M1和四比特的第二小幅度值M2被一起提供给多路复用器(MUX)320。此外,四比特的幅度值|Q|[3:0]被提供给触发器(FF)314,该FF 314使CNU 300的时序与LDPC解码器200的时钟信号同步。
最小值运算器316(0)将幅度值|Q|与寄存器330(0)中存储的最小幅度值M1比较。如果幅度值|Q|小于最小幅度值M1,则最小值运算器316(0)断言(assert)控制信号318(0)(即,将318(0)设定为等于1)。否则,最小值运算器316(0)去断言(de-assert)控制信号318(0)(即,将318(0)设定为等于0)。类似地,最小值运算器316(1)将幅度值|Q|与寄存器330(1)中存储的第二小幅度值M2比较。如果幅度值|Q|小于M2,则断言控制信号318(1)。否则,将控制信号318(1)去断言。应当注意,出于本申请的目的,最小幅度值M1和第二小幅度值M2被认为是消息。为了进一步理解MUX 320的操作,考虑用于幅度值|Q|的表I的逻辑表。
表I示出了,如果控制信号318(0)和318(1)均被去断言(即,|Q|≥M1和M2),则幅度值|Q|被丢弃,并且先前存储的最小和第二小的幅度值M1和M2被分别存储在M1寄存器330(0)和M2寄存器330(1)中。如果控制信号318(0)被去断言并且控制信号318(1)被断言(即,M2>|Q|≥M1),则(i)最小幅度值M1被存储在M1寄存器330(0)中,(ii)幅度值|Q|被存储在M2寄存器330(1)中,并且(iii)先前存储的第二小幅度值M2被丢弃。如果控制信号318(0)和318(1)均被断言(即,|Q|<M1和M2),则(i)幅度值|Q|被存储在M1寄存器330(0)中,(ii)先前存储的最小值M1被存储在M2寄存器330(1)中,并且(iii)第二小值M2被丢弃。除了在M1寄存器330(0)中存储幅度值|Q|之外,还将M1_索引寄存器330(2)使能,与新的最小值M1对应的计数器值324(由计数器322生成)被存储在M1_索引寄存器330(2)中,并且先前存储在M1_索引寄存器330(2)中的计数器值被丢弃。应当注意,控制信号318(0)将被断言并且控制信号318(1)将被去断言的情况是不可能的,这是因为这将指示幅度值|Q|小于最小幅度值M1且大于第二小幅度值M2。此外,在首个时钟周期之前,最小和第二小的幅度值M1和M2被初始化为适当大的值(例如,二进制1111),并且M1_索引被初始化为0。
在所有10个Q消息均已被考虑之后,可以通过缩放和偏移逻辑模块334使最小幅度值M1和第二小幅度值M2缩放和/或偏移。符号-幅度到2的补码(SMT2)转换器338通过将正的符号比特附加到四比特的值M1′,来将可能经缩放和偏移的四比特的最小幅度值M1′转换为五比特的正的2的补码值,并且将五比特的结果(+M1′)存储在最终状态处理器306的寄存器336(0)中。SMT2转换器338还通过将负的符号比特附加到四比特的值M1′,来将可能经缩放和/或偏移的四比特的偏移最小幅度值M1′转换为五比特的负的2补码值,并且将该五比特的结果(-M1′)存储寄存器336(1)中。此外,如果来自符号处理逻辑328的符号比特332是正的符号比特(0),则SMT2转换器338将可能经缩放和/或偏移的四比特的第二小幅度值M2′转换为五比特的正的2补码值(+M2′),以存储在寄存器336(2)中。如果来自符号处理逻辑328的符号比特332是负的符号比特(1),则SMT2转换器338将可能经缩放和/或偏移的四比特的第二小幅度值M2′转换为五比特的负的2补码值(-M2′),以存储在寄存器336(2)中。最终状态处理器306的寄存器336(3)存储来自M1_索引寄存器330(2)的计数器值M1_INDEX。
在紧接的10个时钟周期中的每个时钟周期期间,R选择器308的MUX 344基于以下来输出五比特的R消息:(1)正的值(+M1′)、(2)负的值(-M1′)、(3)正的或负的值(±M2′)、(4)来自比较运算器340的比较比特342、和(5)符号处理逻辑328中存储的对应符号比特326。通过将当前的计数器值324与寄存器336(3)中存储的M1_索引值比较,生成了每个比较比特342。当两者相等时,比较比特342被断言,并且当两者不相等时,比较比特342被去断言。可以使用式(3)将每个符号比特332生成为δmn (i),或者可替选地,在使用FIFO实现符号处理逻辑328的情况中,通过将所存储的符号比特326在其从FIFO输出时乘以符号处理逻辑328中存储的所有符号比特326的积,来将每个符号比特332生成为δmn (i)。为了进一步理解如何从MUX 344输出R消息,考虑表II的逻辑表。
表II示出了,如果比较比特342和符号比特332均被去断言,则寄存器336(0)中存储的正的值(+M1′)将被输出作为五比特的R消息。如果比较比特342被去断言并且符号比特332被断言,则寄存器336(1)中存储的负的值(-M1′)将被输出作为五比特的R消息。如果比较比特342被断言并且符号比特332被去断言,则正的值(+M2′)将已被存储在存储器336(2)中,并且现将被输出作为五比特的R消息。如果比较比特342和符号比特332均被断言,则负的值(-M2′)将已被存储在存储器336(3)中,并且现将被输出作为五比特的R消息。随后可通过缩放和偏移逻辑346来使R消息缩放和/或偏移。
回来参照图2,循环移位器212(0)、...、212(3)从它们各自的CNU210接收72个五比特的R消息的集合,并且根据图1的H矩阵的循环矩阵Bj,k的循环移位来使72个五比特的R消息的集合循环移位。基本上,循环移位器212(0)、...、212(3)将循环移位器208(0)、...、208(3)的循环移位反转。例如,如果循环移位器208(0)、...、208(3)执行循环上移位,则循环移位器212(0)、...、212(3)执行循环下移位。
循环移位器212(0)、...、212(3)向VNU 204(0)、...、204(71)提供4×72个循环移位的五比特的R消息,从而使每个VNU 204接收四个R消息,即从每个循环移位器212接收一个R消息。每个VNU 204更新如式(4)中所示生成的4个五比特的Q消息中的每个Q消息:
其中m′是除了第m个校验节点以外的连接到第n个变量节点的所有校验节点的集合M(n)/m中的校验节点(即,m′∈M(n)/m)。第n个变量节点基于(i)在先前第(i-1)次迭代期间从集合M(n)/m接收的所有R消息和(ii)从与第n个变量节点对应的软值存储器202接收的初始软值Ln (0),生成消息Qnm (i)。可以使用加法器电路实现每个VNU 204,每个VNU 204输出其生成的4个更新的五比特的Q消息,从而向不同的对应的MUX 206提供四个消息中的不同的一个消息。
除输出4个更新的五比特的Q消息之外,每个VNU 204还输出(i)七比特的非本征(extrinsic)LLR值、(ii)硬判决输出比特、和(iii)八比特的P值。每个七比特的非本征LLR值可被表示为如式(5)中所示的:
其中m是连接到第n个变量节点的所有校验节点的集合M(n)中的校验节点(即,m∈M(n))。可以使用如下式(6)生成每个八比特的P值:
如果Pn≥0,则
如果Pn<0,则
通过将来自式(5)的非本征值添加到从与第n个变量节点对应的软值存储器202接收的初始软值Ln (0),确定关于每个变量节点的Pn。如式(7)中所示,如果Pn大于或等于0,则硬判决比特等于0。如式(8)中所示,如果Pn小于0,则硬判决比特等于1。
随后由例如控制器214利用硬判决值执行奇偶校验,以确定LDPC解码器200是否已收敛在有效码字。特别地,由在10个时钟周期期间从VNU 204(0)、...、204(71)输出的720个硬判决比特形成的720元素的向量与图1的H矩阵100的转置矩阵HT相乘以生成288比特的向量,其中288比特的向量中的每个比特对应于H矩阵100的288个校验节点(即,行)中的一个。如果得到的288比特的向量的每个元素等于0(即,),则LDPC解码器200已收敛在有效码字。另一方面,如果得到的288比特的向量的一个或更多个元素等于1(即,),则LDPC解码器200尚未收敛在有效码字。具有1的值的288比特的向量的每个元素被视为不满意的校验节点。如果并且当LDPC解码器200收敛在有效码字,则可由例如控制器214执行循环冗余校验(CRC)。如果CRC成功,则LDPC解码器200已收敛在有效的正确码字。如果CRC不成功,则LDPC解码器200已收敛在有效但不正确的码字。
如果LDPC解码器200未收敛在有效码字或收敛在有效但不正确的码字,则需要进一步的行动以恰当地恢复正确码字。例如,可以执行LDPC解码器200的随后的局部迭代以收敛在有效的正确码字。作为另一示例,可以执行全局迭代,由此(i)非本征LLR值被馈送回上游处理器,(ii)检测器生成新的720个五比特的软值Ln (0)的集合,以及(iii)LDPC解码器200尝试从该新的720个五比特的软值Ln (0)的集合恢复正确的码字。如果在预先限定的局部和/或全局迭代次数内LDPC解码器200未收敛在有效的正确码字,则接收器和/或LDPC解码器可以采取进一步的行动以恢复有效码字,诸如执行被设计用于打破陷阱集的其他方法。在一些情况中,LDPC解码器200可能不能恢复正确码字。作为另一示例,LDPC解码器200驻留其中的接收器可以请求数据重传。
对于每次随后的对码字解码的尝试(例如,每次随后的局部迭代、随后的全局迭代、或者重传),控制器214可以选择一个或更多个不同的缩放因子α、一个或更多个不同的偏移值β,或者一个或更多个不同的缩放因子α和一个或更多个不同的偏移值β。可以使用任何适当的方法选择缩放因子α和偏移值β。例如,可以基于在奇偶校验期间识别到的不满意的校验节点的数目来选择缩放因子α和偏移值β。当不满意的校验节点的数目相对小的时候,可以选择相对接近1的缩放因子α和相对接近0的偏移值β,以引发校验节点消息中相对小的改变。当不满意的校验节点的数目相对大的时候,可以选择较小的缩放因子α和/或较大的偏移值β,以引发校验节点消息中相对大的改变。随着缩放因子α从1减小,并且随着偏移值β从0增加,对校验节点消息的改变增加。
作为另一示例,在预定次数的迭代之后可以使缩放因子α和偏移值β渐增。可以按例如0.2的增量来调节缩放因子α,并且可以按例如1的增量来调节偏移值β。
通过改变缩放因子α和/或偏移值β,较之仅实现固定的缩放因子或没有缩放因子或者仅实现固定的偏移因子或没有偏移因子的LDPC解码器,本发明的LDPC解码器能够改进错误平层特性。当本发明的LDPC解码器遇到陷阱集时,解码器可以改变一个或更多个缩放因子α和/或一个或更多个偏移值β以尝试打破陷阱集,从而使LDPC解码器具有对码字正确解码的另一机会。
尽管已经针对图2的特定的非分层LDPC解码器配置200描述了本发明,但是本发明不限于此。对于使用消息传递的其他LDPC解码器结构,也可以设想本发明的各种实施例。例如,本发明可被实现用于其他非分层的或分层的解码器结构,以及使用不同于块串行消息传递方案的消息传递方案的解码器。作为另一示例,可以在不使用循环移位器的情况下实现本发明的LDPC解码器。在该实施例中,可以通过直接连接或使用执行非循环移位的排列器(permutator)在CNU和VNU之间传递消息。
根据各种实施例,可以使用不同于最小和算法的校验节点算法实现本发明。在这些实施例中,可以分别通过与缩放和偏移逻辑模块346和310类似的方式,将缩放和/或偏移应用于校验节点消息和/或变量节点消息。此外,与缩放和偏移逻辑模块334类似地,可以在生成校验节点消息之前通过校验节点算法应用缩放和/或偏移。
尽管已经针对图1的特定的H矩阵100描述了本发明,但是本发明不限于此。本发明可被实现用于具有与图1的矩阵100相同或不同的大小(size)的各种H矩阵。例如,本发明可被实现用于如下H矩阵,在该H矩阵中,列、块列、行、块行、层(包括仅具有一个层的实现方案)、每时钟周期处理的消息的数目,子矩阵的大小,层的大小,和/或列和/或行的汉明权重不同于H矩阵100的。该H矩阵可以是例如,循环、准循环、非循环、正则、或非正则H矩阵。此外,该H矩阵可以包括不同于循环矩阵的子矩阵,包括零矩阵。应当注意,VNU、桶式移位器(barrel shifter)和/或CNU的数目可以根据H矩阵的特性变化。
将进一步理解,本领域的技术人员可以对用以解释本发明的本质而描述和示出的部件的布置、细节、和材料进行各种变更,而不偏离如所附权利要求中表达的本发明的范围。例如,缩放和偏移逻辑模块可以在不同于图3中示出的三个位置(例如,不同于310、334、346)的位置实现,诸如在多路复用器320的幅度|Q|输入处或者在SMT2转换器338与最终状态寄存器336(0)、...、336(2)之间实现。缩放和偏移逻辑模块310还可以位于VNU(或者生成变量节点消息的加法器)的输出处,而不是作为CNU 300的部件,并且缩放和偏移逻辑模块346还可以位于VNU(或者生成变量节点消息的加法器)的输入处,而不是作为CNU300的部件。作为另一示例,不同于使用2的补码格式接收Q消息和输出R消息,CNU 300可以以另一格式(诸如,符号-幅度格式)来接收和输出消息。此外,2的补码到符号-幅度转换可由例如VNU执行。作为另一示例,本发明的LDPC解码器可以处理大小不是五比特的消息。
尽管已经在LDPC码的背景下描述了本发明的实施例,但是本发明不限于此。本发明的实施例可被实现用于可由图定义的任何码,例如tornado码和结构化IRA码,这是因为图定义的码受到陷阱集的困扰。
尽管已经针对电路的处理过程描述了本发明的示例性实施例,包括作为单个集成电路、多芯片模块、单个卡或多卡电路组件的可能的实现方案,但是本发明不限于此。如本领域的技术人员将认识到的,电路元件的各种功能也可被实现为软件程序中的处理模块。可以在例如数字信号处理器、微控制器或通用计算机中使用该软件。
此外,本发明不限于接收和处理对数似然比。可以设想其中处理诸如似然比的其他软值或者硬比特判决的本发明的各种实施例。
如说明书和权利要求书中使用的术语“渐增”应被理解为包括使值增加的情形和使值减小的情形。例如,使缩放因子渐增指定的缩放因子增量包括使缩放因子增加指定的缩放因子增量的情形和使缩放因子减小指定的缩放因子增量的情形。
如说明书和权利要求中使用的,即使在第一和第二值之间生成了中间值,但是第二值仍可被称为是“基于”第一值生成的。例如,即使在接收软值Ln (0)和生成校验节点消息之间生成了校验节点消息,但是变量节点消息仍可被称为是“基于”解码器接收的软值Ln (0)生成的。作为另一示例,在LDPC解码器的第二次局部迭代期间生成的校验节点消息可被称为是“基于”在第一次局部迭代期间接收的软值Ln (0)生成的,即使在接收软值Ln (0)和生成用于第二次局部迭代的校验节点消息之间生成了变量节点消息和其他校验节点消息。
本发明可被具体化为方法和用于实践这些方法的装置的形式。本发明还可被具体化为程序代码的形式,该程序代码在诸如磁记录介质、光记录介质、固态存储器、软盘、CD-ROM、硬盘驱动器或者任何其他机器可读存储介质的有形介质中具体化,其中,当该程序代码被加载到机器(诸如,计算机)中并由该机器执行时,该机器成为用于实践本发明的装置。本发明还可被具体化为程序代码的形式,而不管例如是存储在存储介质中的,加载到机器中和/或由机器执行的,或者在一些传送介质或载体上传送(诸如在电导线或线缆上传送、通过光纤传送或者经由电磁辐射传送)的,其中,当该程序代码被加载到机器(诸如,计算机)中并由该机器执行时,该机器成为用于实践本发明的装置。当在通用处理器上实现时,程序代码段与处理器组合以提供类似特定逻辑电路操作的唯一性的设备。本发明还可以具体化为使用本发明的方法和/或装置生成的通过介质电传送或光传送的比特流或者其他信号值序列、存储在磁记录介质中的磁场变化等形式。
除非另外明确说明,否则每个数值和范围应被解释为是大致的,如同在该值或范围的值之前具有词“约”或“大致”。
在权利要求中使用附图数字和/或附图参考标记,用于标识所要求保护的主题内容的一个或更多个可能的实施例,以便易于解释权利要求。该使用不应被解释为必须将这些权利要求的范围限制于对应附图中示出的实施例。
应当理解,此处阐述的示例性方法的步骤并不必须按照所描述的顺序执行,并且这些方法的步骤的顺序应被理解为仅是示例性的。同样地,这些方法中可以包括另外的步骤,并且在符合本发明的实施例的方法中,某些步骤可被省略或组合。
尽管按照具有相应标记的特定顺序叙述了所附方法权利要求中的要素,但是除非权利要求叙述另外指出用于实现一些或所有这些要素的特定顺序,否则这些要素并不必然限于按照该特定顺序实现。
Claims (20)
1.一种装置,包括用于对纠错(EC)编码的码字解码以恢复正确码字的EC解码器,其中:
所述解码器适于基于上游处理器所生成的初始值的初始集合生成第一消息集合,其中:
所述初始集合对应于所述EC编码的码字;以及
所述初始集合中的每个初始值对应于所述EC编码的码字的不同比特;以及
所述解码器包括:
一个或更多个模块,其适于基于缩放因子和偏移值将所述第一消息集合转换为经缩放和偏移的消息;以及
控制器,适于选择所述缩放因子和所述偏移值。
2.如权利要求1所述的装置,其中:
所述EC解码器包括变量节点单元,其适于生成变量节点消息;
所述第一消息集合是所述变量节点消息;以及
所述一个或更多个模块(例如,310)适于基于所述缩放因子和所述偏移值将所述变量节点消息转换为经缩放和偏移的变量节点消息。
3.如权利要求1所述的装置,其中:
所述EC解码器包括校验节点单元,其适于生成校验节点消息;
所述第一消息集合是所述校验节点消息;以及
所述一个或更多个模块(例如,346)适于基于所述缩放因子和所述偏移值将所述校验节点消息转换为经缩放和偏移的校验节点消息。
4.如权利要求1所述的装置,其中:
所述EC解码器实现最小和算法;
所述EC解码器包括校验节点单元,其适于生成最小和算法的第一最小和第二最小幅度值;
所述第一消息集合是所述第一最小和第二最小幅度值;以及
所述一个或更多个模块(例如,334)适于基于所述缩放因子和所述偏移值将所述第一最小和第二最小幅度值转换为经缩放和偏移的第一最小和第二最小幅度值。
5.如权利要求1所述的装置,其中:
所述控制器能够将所述缩放因子设定为1;以及
所述控制器能够将所述偏移值设定为0。
6.如权利要求1所述的装置,其中,所述一个或更多个模块包括执行缩放和偏移的缩放和偏移模块。
7.如权利要求1所述的装置,其中:
所述解码器是低密度奇偶校验(LDPC)解码器;以及
从所述上游处理器接收的所述值是具有硬判决比特和一个或更多个置信值比特的软输出值。
8.如权利要求1所述的装置,其中,所述控制器适于:(i)选择初始缩放因子和初始偏移值,以及(ii)随后修改所述初始缩放因子和所述初始偏移值中的至少一个。
9.如权利要求8所述的装置,其中,在所述控制器确定在预定的解码迭代次数内所述EC解码器未收敛在正确的码字之后,所述控制器修改所述初始缩放因子和所述初始偏移值中的至少一个。
10.如权利要求8所述的装置,其中,所述控制器适于修改所述初始缩放因子和所述初始偏移值。
11.如权利要求8所述的装置,其中,所述控制器适于通过使所述初始缩放因子渐增指定的缩放因子增量来修改所述初始缩放因子。
12.如权利要求8所述的装置,其中,所述控制器适于通过使所述初始偏移值渐增指定的偏移值增量来修改所述初始偏移值。
13.一种用于对纠错(EC)编码的码字解码以恢复正确码字的方法,所述方法包括:
(a)选择缩放因子和偏移值;
(b)从上游处理器接收初始值的初始集合,其中:
所述初始集合对应于所述EC编码的码字;以及
所述初始集合中的每个初始值对应于所述EC编码的码字的不同比特;
(c)基于所述初始值的初始集合生成第一消息集合;以及
(d)基于所述缩放因子和所述偏移值将所述第一消息集合转换为经缩放和偏移的消息。
14.如权利要求13所述的方法,其中:
步骤(c)包括生成变量节点消息作为所述第一消息集合;以及
步骤(d)包括基于所述缩放因子和所述偏移值将所述变量节点消息转换为经缩放和偏移的变量节点消息。
15.如权利要求13所述的方法,其中:
步骤(c)包括生成校验节点消息作为所述第一消息集合;以及
步骤(d)包括基于所述缩放因子和所述偏移值将所述校验节点消息转换为经缩放和偏移的校验节点消息。
16.如权利要求13所述的方法,其中:
步骤(c)包括生成最小和算法的第一最小和第二最小幅度值作为所述第一消息集合;以及
步骤(d)包括基于所述缩放因子和所述偏移值将所述第一最小和第二最小幅度值转换为经缩放和偏移的第一最小和第二最小幅度值。
17.如权利要求13所述的方法,其中:
步骤(a)包括选择初始缩放因子和初始偏移值;
步骤(d)包括基于所述初始缩放因子和所述初始偏移值将所述第一消息集合转换为经缩放和偏移的消息;以及
所述方法进一步包括:
(e)随后修改所述初始缩放因子和所述初始偏移值中的至少一个;
(f)生成第二消息集合;以及
(g)基于如步骤(e)中修改了的所述初始缩放因子和所述初始偏移值将所述第二消息集合转换为经缩放和偏移的消息。
18.如权利要求17所述的方法,其中,在确定在预定的解码迭代次数内所述方法未收敛在正确的码字之后,修改所述初始缩放因子和所述初始偏移值中所述至少一个。
19.如权利要求13所述的方法,其中:
所述EC编码的码字是LDPC编码的码字;以及
从所述上游处理器接收的所述值是具有硬判决比特和一个或更多个置信值比特的软输出值。
20.一种用于对纠错(EC)编码的码字解码以恢复正确码字的装置,所述方法包括:
(a)用于选择缩放因子和偏移值的装置;
(b)用于从上游处理器接收初始值的初始集合的装置,其中:
所述初始集合对应于所述EC编码的码字;以及
所述初始集合中的每个初始值对应于所述EC编码的码字的不同比特;
(c)用于基于所述初始值的初始集合生成第一消息集合的装置;以及
(d)用于基于所述缩放因子和所述偏移值将所述第一消息集合转换为经缩放和偏移的消息的装置。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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US8929708P | 2008-08-15 | 2008-08-15 | |
US61/089,297 | 2008-08-15 | ||
PCT/US2009/039918 WO2010019287A1 (en) | 2008-08-15 | 2009-04-08 | Error-correction decoder employing multiple check-node algorithms |
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Country Status (7)
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EP (3) | EP2223431A4 (zh) |
JP (4) | JP5276173B2 (zh) |
KR (3) | KR101418466B1 (zh) |
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CN115882873A (zh) * | 2023-02-23 | 2023-03-31 | 成都星联芯通科技有限公司 | 低密度奇偶校验码译码方法、装置、通信设备及存储介质 |
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