FR2905210B1 - Procede et dispositif de decodage par couches d'une succession de blocs encodes avec un code ldpc - Google Patents

Procede et dispositif de decodage par couches d'une succession de blocs encodes avec un code ldpc

Info

Publication number
FR2905210B1
FR2905210B1 FR0607490A FR0607490A FR2905210B1 FR 2905210 B1 FR2905210 B1 FR 2905210B1 FR 0607490 A FR0607490 A FR 0607490A FR 0607490 A FR0607490 A FR 0607490A FR 2905210 B1 FR2905210 B1 FR 2905210B1
Authority
FR
France
Prior art keywords
estate
ldpc code
blocks encoded
layered decoding
layered
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0607490A
Other languages
English (en)
Other versions
FR2905210A1 (fr
Inventor
Vincent Heinrich
Laurent Paumier
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
STMicroelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SA filed Critical STMicroelectronics SA
Priority to FR0607490A priority Critical patent/FR2905210B1/fr
Priority to US11/830,444 priority patent/US8037388B2/en
Publication of FR2905210A1 publication Critical patent/FR2905210A1/fr
Application granted granted Critical
Publication of FR2905210B1 publication Critical patent/FR2905210B1/fr
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
    • H03M13/1165—QC-LDPC codes as defined for the digital video broadcasting [DVB] specifications, e.g. DVB-Satellite [DVB-S2]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105—Decoding
    • H03M13/1131—Scheduling of bit node or check node processing
    • H03M13/1137—Partly parallel processing, i.e. sub-blocks or sub-groups of nodes being processed in parallel
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105—Decoding
    • H03M13/1131—Scheduling of bit node or check node processing
    • H03M13/114—Shuffled, staggered, layered or turbo decoding schedules
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6502—Reduction of hardware complexity or efficient processing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6566—Implementations concerning memory access contentions

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Probability & Statistics with Applications (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Multimedia (AREA)
  • Error Detection And Correction (AREA)
FR0607490A 2006-08-24 2006-08-24 Procede et dispositif de decodage par couches d'une succession de blocs encodes avec un code ldpc Expired - Fee Related FR2905210B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR0607490A FR2905210B1 (fr) 2006-08-24 2006-08-24 Procede et dispositif de decodage par couches d'une succession de blocs encodes avec un code ldpc
US11/830,444 US8037388B2 (en) 2006-08-24 2007-07-30 Method and device for layered decoding of a succession of blocks encoded with an LDPC code

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0607490A FR2905210B1 (fr) 2006-08-24 2006-08-24 Procede et dispositif de decodage par couches d'une succession de blocs encodes avec un code ldpc

Publications (2)

Publication Number Publication Date
FR2905210A1 FR2905210A1 (fr) 2008-02-29
FR2905210B1 true FR2905210B1 (fr) 2008-10-31

Family

ID=37714488

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0607490A Expired - Fee Related FR2905210B1 (fr) 2006-08-24 2006-08-24 Procede et dispositif de decodage par couches d'une succession de blocs encodes avec un code ldpc

Country Status (2)

Country Link
US (1) US8037388B2 (fr)
FR (1) FR2905210B1 (fr)

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US20100037121A1 (en) * 2008-08-05 2010-02-11 The Hong Kong University Of Science And Technology Low power layered decoding for low density parity check decoders
US8464129B2 (en) * 2008-08-15 2013-06-11 Lsi Corporation ROM list-decoding of near codewords
FR2944660B1 (fr) * 2009-04-16 2011-09-09 St Microelectronics Sa Decodeur ldpc
KR101321487B1 (ko) 2009-04-21 2013-10-23 에이저 시스템즈 엘엘시 기입 검증을 사용한 코드들의 에러-플로어 완화
US8464142B2 (en) 2010-04-23 2013-06-11 Lsi Corporation Error-correction decoder employing extrinsic message averaging
US8499226B2 (en) 2010-06-29 2013-07-30 Lsi Corporation Multi-mode layered decoding
US8458555B2 (en) 2010-06-30 2013-06-04 Lsi Corporation Breaking trapping sets using targeted bit adjustment
US8504900B2 (en) 2010-07-02 2013-08-06 Lsi Corporation On-line discovery and filtering of trapping sets
US8768990B2 (en) 2011-11-11 2014-07-01 Lsi Corporation Reconfigurable cyclic shifter arrangement
RU2012146685A (ru) 2012-11-01 2014-05-10 ЭлЭсАй Корпорейшн База данных наборов-ловушек для декодера на основе разреженного контроля четности
US9122625B1 (en) 2012-12-18 2015-09-01 Western Digital Technologies, Inc. Error correcting code encoder supporting multiple code rates and throughput speeds for data storage systems
US9619317B1 (en) 2012-12-18 2017-04-11 Western Digital Technologies, Inc. Decoder having early decoding termination detection
US8966339B1 (en) 2012-12-18 2015-02-24 Western Digital Technologies, Inc. Decoder supporting multiple code rates and code lengths for data storage systems
US9813080B1 (en) * 2013-03-05 2017-11-07 Microsemi Solutions (U.S.), Inc. Layer specific LDPC decoder
US10230396B1 (en) 2013-03-05 2019-03-12 Microsemi Solutions (Us), Inc. Method and apparatus for layer-specific LDPC decoding
US10448390B2 (en) * 2014-12-19 2019-10-15 Qualcomm Incorporated Transmission techniques for enabling an immediate response
US10332613B1 (en) 2015-05-18 2019-06-25 Microsemi Solutions (Us), Inc. Nonvolatile memory system with retention monitor
US9799405B1 (en) 2015-07-29 2017-10-24 Ip Gem Group, Llc Nonvolatile memory system with read circuit for performing reads using threshold voltage shift read instruction
US9886214B2 (en) 2015-12-11 2018-02-06 Ip Gem Group, Llc Nonvolatile memory system with erase suspend circuit and method for erase suspend management
US9892794B2 (en) 2016-01-04 2018-02-13 Ip Gem Group, Llc Method and apparatus with program suspend using test mode
US9899092B2 (en) 2016-01-27 2018-02-20 Ip Gem Group, Llc Nonvolatile memory system with program step manager and method for program step management
US10283215B2 (en) 2016-07-28 2019-05-07 Ip Gem Group, Llc Nonvolatile memory system with background reference positioning and local reference positioning
US10291263B2 (en) 2016-07-28 2019-05-14 Ip Gem Group, Llc Auto-learning log likelihood ratio
US10236915B2 (en) 2016-07-29 2019-03-19 Microsemi Solutions (U.S.), Inc. Variable T BCH encoding

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Publication number Priority date Publication date Assignee Title
US7159170B2 (en) * 2003-06-13 2007-01-02 Broadcom Corporation LDPC (low density parity check) coded modulation symbol decoding
JP2005093038A (ja) * 2003-09-19 2005-04-07 Fujitsu Ltd 記録再生装置および記録再生回路
US7484158B2 (en) * 2003-12-03 2009-01-27 Infineon Technologies Ag Method for decoding a low-density parity check (LDPC) codeword
US7174495B2 (en) * 2003-12-19 2007-02-06 Emmanuel Boutillon LDPC decoder, corresponding method, system and computer program
KR100594818B1 (ko) * 2004-04-13 2006-07-03 한국전자통신연구원 순차적 복호를 이용한 저밀도 패리티 검사 부호의 복호장치 및 그 방법
JP4050726B2 (ja) * 2004-06-23 2008-02-20 株式会社東芝 復号装置
US7260762B2 (en) * 2004-07-26 2007-08-21 Motorola, Inc. Decoder performance for block product codes
US7698623B2 (en) * 2004-08-13 2010-04-13 David Hedberg Systems and methods for decreasing latency in a digital transmission system
US20060085720A1 (en) * 2004-10-04 2006-04-20 Hau Thien Tran Message passing memory and barrel shifter arrangement in LDPC (Low Density Parity Check) decoder supporting multiple LDPC codes
US7760880B2 (en) * 2004-10-13 2010-07-20 Viasat, Inc. Decoder architecture system and method
US7577892B1 (en) * 2005-08-25 2009-08-18 Marvell International Ltd High speed iterative decoder
US7770090B1 (en) * 2005-09-14 2010-08-03 Trident Microsystems (Far East) Ltd. Efficient decoders for LDPC codes
US7707479B2 (en) * 2005-12-13 2010-04-27 Samsung Electronics Co., Ltd. Method of generating structured irregular low density parity checkcodes for wireless systems
US7669106B1 (en) * 2006-04-17 2010-02-23 Aquantia Corporation Optimization of low density parity check (LDPC) building blocks using multi-input Gilbert cells

Also Published As

Publication number Publication date
US8037388B2 (en) 2011-10-11
FR2905210A1 (fr) 2008-02-29
US20080049869A1 (en) 2008-02-28

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Effective date: 20130430