US8578256B2  Lowlatency decoder  Google Patents
Lowlatency decoder Download PDFInfo
 Publication number
 US8578256B2 US8578256B2 US12427786 US42778609A US8578256B2 US 8578256 B2 US8578256 B2 US 8578256B2 US 12427786 US12427786 US 12427786 US 42778609 A US42778609 A US 42778609A US 8578256 B2 US8578256 B2 US 8578256B2
 Authority
 US
 Grant status
 Grant
 Patent type
 Prior art keywords
 check
 values
 node
 set
 initial
 Prior art date
 Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
 Active, expires
Links
Images
Classifications

 H—ELECTRICITY
 H03—BASIC ELECTRONIC CIRCUITRY
 H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
 H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
 H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
 H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
 H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
 H03M13/1102—Codes on graphs and decoding on graphs, e.g. lowdensity parity check [LDPC] codes
 H03M13/1148—Structural properties of the code paritycheck or generator matrix
 H03M13/116—Quasicyclic LDPC [QCLDPC] codes, i.e. the paritycheck matrix being composed of permutation or circulant submatrices

 H—ELECTRICITY
 H03—BASIC ELECTRONIC CIRCUITRY
 H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
 H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
 H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
 H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
 H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
 H03M13/1102—Codes on graphs and decoding on graphs, e.g. lowdensity parity check [LDPC] codes
 H03M13/1105—Decoding
 H03M13/1111—Softdecision decoding, e.g. by means of message passing or belief propagation algorithms
 H03M13/1117—Softdecision decoding, e.g. by means of message passing or belief propagation algorithms using approximations for check node processing, e.g. an outgoing message is depending on the signs and the minimum over the magnitudes of all incoming messages according to the minsum rule
 H03M13/1122—Softdecision decoding, e.g. by means of message passing or belief propagation algorithms using approximations for check node processing, e.g. an outgoing message is depending on the signs and the minimum over the magnitudes of all incoming messages according to the minsum rule storing only the first and second minimum values per check node

 H—ELECTRICITY
 H03—BASIC ELECTRONIC CIRCUITRY
 H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
 H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
 H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
 H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
 H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
 H03M13/1102—Codes on graphs and decoding on graphs, e.g. lowdensity parity check [LDPC] codes
 H03M13/1105—Decoding
 H03M13/1131—Scheduling of bit node or check node processing
 H03M13/114—Shuffled, staggered, layered or turbo decoding schedules

 H—ELECTRICITY
 H04—ELECTRIC COMMUNICATION TECHNIQUE
 H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
 H04L1/00—Arrangements for detecting or preventing errors in the information received
 H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
 H04L1/0045—Arrangements at the receiver end
 H04L1/0047—Decoding adapted to other signal detection operation
 H04L1/005—Iterative decoding, including iteration between signal detection and decoding operation
 H04L1/0051—Stopping criteria

 H—ELECTRICITY
 H04—ELECTRIC COMMUNICATION TECHNIQUE
 H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
 H04L1/00—Arrangements for detecting or preventing errors in the information received
 H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
 H04L1/0056—Systems characterized by the type of code used
 H04L1/0057—Block codes
Abstract
Description
1. Field of the Invention
The present invention relates to signal processing, and, in particular, to errorcorrection encoding and decoding techniques such as lowdensity paritycheck (LDPC) encoding and decoding.
2. Description of the Related Art
In communicating a data signal from a transmitter to a receiver, noise may be introduced into the signal causing the signal to be distorted upon arrival at the receiver. As a result of this distortion, the receiver might not correctly recover the transmitted information. In such cases, the transmitted signal may need to be retransmitted so that the receiver may have another opportunity to recover the transmitted information. However, resending the transmitted signal increases the amount of time that it takes to provide the transmitted information to the user. To reduce the frequency of retransmissions, and therefore reduce the amount of time that it takes for the transmitted information to be delivered to the user, the transmitter may encode the transmitted signal using a channelcoding scheme. A channelcoding scheme adds redundant or additional data to the signal to be transmitted. The receiver then uses this redundant or additional data to detect and/or correct errors. If the channelcoding scheme is effective, then the transmitted data may be recovered correctly without the need to retransmit the data.
One particular channelcoding scheme that has received attention in recent years is lowdensity paritycheck (LDPC) coding. LDPC codes, which are typically defined using paritycheck matrices, provide excellent performance that comes relatively close to the Shannon limit. A discussion of LDPC codes and LDPC decoding is presented in Hocevar, “A Reduced Complexity Decoder Architecture via Layered Decoding of LDPC Codes,” Signal Processing Systems, IEEE Workshop on Signal Processing Systems Design and Implementation, pgs 107112, October 2004, the teachings all of which are incorporated herein by reference in their entirety.
In one embodiment, the present invention is a method for decoding an errorcorrection (EC) encoded codeword. The method receives values corresponding to bits of the ECencoded codeword. Checknode updates are performed based on the bits of the codeword to generate checknode messages. The checknode updates are initiated before all of the values corresponding to bits of the ECencoded codeword are generated. The values corresponding to the bits based on the checknode messages are updated to generate updated values, and the method determines whether the updated values correspond to a valid codeword.
In another embodiment, the present invention is an apparatus for performing the method described above. The apparatus comprises a decoder for decoding an ECencoded codeword. The decoder comprises (i) a checknode unit that performs the checknode updates, (ii) a combiner that generates the updated values, and (ii) a paritycheck calculator that determines whether the updated values correspond to a valid codeword.
Other aspects, features, and advantages of the present invention will become more fully apparent from the following detailed description, the appended claims, and the accompanying drawings in which like reference numerals identify similar or identical elements.
Reference herein to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments necessarily mutually exclusive of other embodiments. The same applies to the term “implementation.”
Softoutput memory 104 stores all 33,000 fivebit softoutput values, and provides the softoutput values to LDPC decoder 106 at a rate of 24 soft values per clock cycle. The softoutput values are provided in an order that is different from the order in which they are received by softoutput memory 104. The order in which they are output corresponds to the structure of the LDPC code, and consequently, the order in which they are processed by LDPC decoder 106. To provide the softoutput values in a different order, softoutput memory 104 is implemented with logic that enables it to determine which softoutput values to provide during each clock cycle.
LDPC decoder 106 decodes the softoutput values in the order that they are received from softoutput memory 104, and, if decoding is successful, LDPC decoder 106 outputs a harddecision bit for each of the 33,000 bits of the codeword at a rate of 24 harddecision bits per clock cycle. The harddecision bits are processed by downstream processing 108, which may perform, for example, digitaltoanalog conversion or other processing suitable for the particular application in which receiver 100 is implemented.
In receiver 200, all 33,000 softoutput values are provided from upstream processing 202 to LDPC decoder 204 in 1,375 clock cycles (i.e., 33,000 values/24 values per clock cycle). In receiver 100 of
The order in which the softoutput values are processed by an LDPC decoder generally depends on the structure of the LDPC code. Conventional LDPC codes do not allow for processing of softoutput values in the order in which they are output from the upstream processing. Rather, as described above in relation to
The arrangement of the first layer (H_{LAYER1}) may be varied from one embodiment of the present invention to the next to generate different LDPC codes. Various embodiments of the first layer (H_{LAYER1}), such as the embodiment of
The arrangement of each of the second through fourth layers (H_{LAYER2}H_{LAYER4}) of Hmatrix 300 may be obtained by implementing each (24×24) submatrix of the second through fourth layers (H_{LAYER2}H_{LAYER4}) as a zero matrix, an identity matrix, or a circulant, such that the hamming weight w_{r }of each layer row is 11 and the hamming weight w_{c }of each layer column is one. The arrangement of each of the second through fourth layers (H_{LAYER2}H_{LAYER4}) of Hmatrix 300 may differ from that of the first layer (H_{LAYER1}) and may be different from one implementation to the next to generate different LDPC codes. These layers may be made different, for example, by varying the locations of the zero matrices, identity matrices, and circulants. Additionally, one or more of the second through fourth layers (H_{LAYER2}H_{LAYER4}) may be arranged in the same manner as the first layer. Note that LDPC Hmatrices of the present invention may also be generated by permutating rows and columns of priorart Hmatrices. Typically, the errorcorrection capabilities of an LDPC matrix of the present invention that is obtained by permutating rows and columns of a priorart Hmatrix is the same as that of the priorart Hmatrix.
LDPC decoder 400 has multiplexer 402 which receives (i) the 33,000 fivebit softoutput values L_{n} ^{(0) }at a rate of 24 softoutput values L_{n} ^{(0) }per clock cycle via its lower input and (ii) 33,000 variablenode messages L(q_{nm}) at a rate of 24 variablenode messages L(q_{nm}) per clock cycle via its upper input. The variablenode (i.e., column) messages L(q_{nm}) are variablenode messages L(q_{nm}) generated for a previously considered codeword, previously considered iteration, or previously considered layer. During the first 1,375 clock cycles, multiplexer 402 selects the sets of 24 softoutput values L_{n} ^{(0) }that it receives to output to (i) delay buffer 406, which delays each set of 24 softoutput values L_{n} ^{(0) }by eleven clock cycles, and (ii) checknode units (CNUs) 404(1)(24). The sets of 24 softoutput values L_{n} ^{(0) }are selected by asserting (i.e., setting equal to 1) the control signal (LOAD) that is provided to the control port of multiplexer 402. Each set of 24 softoutput values L^{(0) }is output such that each of the 24 softoutput values L_{n} ^{(0) }is provided to a different CNU 404. During subsequent iterations, multiplexer 402 selects the 24 variablenode messages L(q_{nm}) that it receives to output to (i) CNUs 404(1)(24) and (ii) delay buffer 406. For the following discussion, it will be understood that any reference to variablenode messages L(q_{nm}), applies to softoutput values L_{n} ^{(0) }during the first 1,375 clock cycles.
LDPC decoder 400 performs the checknode (i.e., row) updates for Hmatrix 300 of
Each CNU 404 and R selector 408 pair (i) receives a number of variablenode messages L(q_{nm}) equal to the hamming weight w_{r }of a row of Hmatrix 300 (i.e., 11) at a rate of one variablenode message L(q_{nm}) per clock cycle and (ii) generates w_{r }checknode messages. Each checknode message may be generated using a suitable checknode algorithm, such as the minsum algorithm, characterized by Equations (1), (2), and (3) shown below:
where (i) R_{mn }represents the checknode message corresponding to m^{th }check node (i.e., row) and the n^{th }variable node (i.e., column) of Hmatrix 300, (ii) L(q_{nm}) represents the variablenode message corresponding to the n^{th }variable node and the m^{th }check node of Hmatrix 300, and (iii) the function sign indicates that the multiplication operation (i.e., Π) is performed on the signs of variablenode messages L(q_{nm}). Suppose that n′ is a variable node in the set N(m)/n of all variable nodes connected to the m^{th }check node except for the n^{th }variable node (i.e., n′ε N(m)/n). The CNU 404 and R selector 408 pair corresponding to the m^{th }check node (i.e., row), generates checknode message R_{mn }based on all variablenode messages L(q_{nm}) in the set N(m)/n. Thus, in the embodiment of
The minsum algorithm described in Equation (1) may be simplified using a valuereuse technique. For example, for each check node (i.e., row) of Hmatrix 300, each of the 11 checknode messages R_{mn }are generated using a set N(m)/n of ten variablenode messages L(q_{nm}) (one message is excluded as described above). For ten of these 11 checknode messages R_{mn}, the minimum magnitude of the variablenode messages L(q_{nm}) generated using Equation (1) will be the same. For one of these checknode messages R_{mn}, the minimum magnitude of the variablenode messages L(q_{nm}) will be the secondsmallest magnitude of the variablenode messages L(q_{nm}) because the minimum magnitude of the variablenode messages L(q_{nm}) will be excluded from the calculation as described above. Thus, it is not necessary to perform Equation (1) 11 times for each CNU 404 and R selector 408 pair. Rather, as discussed below in relation to
Comparator 504 receives a firstminimum magnitude value (MIN1) from fourbit register 508 at its lower input and compares MIN1 to magnitude value L(q_{nm})51 . If magnitude value L(q_{nm}) is less than MIN1, then the first comparison signal (CMP1) is asserted (i.e., set equal to 1). Otherwise, comparison signal CMP1 is deasserted. Similarly, comparator 506 receives a secondminimum magnitude value (MIN2) from fourbit register 512 at its lower input and compares MIN2 to magnitude value L(q_{nm}). If magnitude value L(q_{nm}) is less than MIN2, then the second comparison signal (CMP2) is asserted. Otherwise, comparison signal CMP2 is deasserted. At the beginning of each set of checknode updates, MIN1 and MIN2 may be set to suitably large values (i.e., binary 1111).
Fourbit registers 508, 512, and 526, which store MIN1, MIN2, and a counter value (MIN1_ID) corresponding to MIN1, respectively, each comprise four flipflops, one for each bit of the value that it stores. Each flipflop, which has a data port (D), an enable port (EN), a clocksignal input port (CLOCK), and an output port (Q), changes its stored value to capture data provided to its data port (D) when (1) its enable port (EN) is enabled and (2) the clock signal is at a rising edge. When either of these two conditions is not satisfied, the value stored by the flipflop is not changed, and the flipflop continues to output the same bit value from its output port (Q). For ease of discussion, fourbit registers 508, 512, and 526 are discussed in terms of having one fourbit data port (D), one enable port (EN), one clocksignal input port (CLOCK), and one fourbit output port (Q).
TABLE I  
CNU 500 MIN1 and MIN2 Logic Table  
CMP1  CMP2  Register 508  Register 512  Register 526 
1 (L(q_{nm}) < MIN1)  1 (L(q_{nm}) < MIN2)  L(q_{nm})  MIN1  Counter 524 
0 (L(q_{nm}) ≧ MIN1)  1 (L(q_{nm}) < MIN2)  MIN1  L(q_{nm})  N/C 
0 (L(q_{nm}) ≧ MIN1)  0 (L(q_{nm}) ≧ MIN2)  MIN1  MIN2  N/C 
1 (L(q_{nm}) < MIN1)  0 (L(q_{nm}) ≧ MIN2)  N/A  N/A  N/A 
To further understand the operation of CNU 500, consider the logic table of Table I. As shown in row 1, if comparison signals CMP1 and CMP2 are both asserted (i.e., L(q_{nm})<M1 and M2), then (i) the MIN1 value previously stored in register 508 is replaced with magnitude value L(q_{nm}), (ii) the MIN2 value previously stored in register 512 is replaced with the MIN1 value previously stored in register 508, and (iii) the MIN1_ID previously stored in register 526 is replaced with current counter value 524. Referring to
As shown in row 2 of Table I, if comparison signal CMP1 is deasserted and comparison signal CMP2 is asserted (i.e., M2>L(q_{nm})≧M1), then (i) the MIN1 value stored in fourbit register 508 is not changed, (ii) the MIN2 value stored in fourbit register 512 is replaced with magnitude value L(q_{nm}), and the MIN1_ID previously stored in register 526 is not changed (N/C). Referring to
As shown in row 3 of Table I, if comparison signals CMP1 and CMP2 are both deasserted (i.e., L(q_{nm})≧M1 and M2), then (i) registers 508, 512, and 526 are not enabled, and the previously stored MIN1, MIN2, and MIN1_ID values are not changed. Note that it is not possible that comparison signal CMP1 will be asserted and comparison signal CMP2 will be deasserted because this would indicate that magnitude value L(q_{nm}) is smaller than firstminimum magnitude value MIN1 but larger than secondminimum magnitude value MIN2.
In addition to determining MIN1 and MIN2, CNU 500 (i) provides the 11 sign bits (i.e., the most significant bits (MSBs) of the 11 signmagnitude variablenode messages L(q_{nm})) to sign memory 414 of
Referring back to
Every 11 clock cycles, 24×13 bits are written into min memory 416, which stores 13 bits for each of the 12,000 check nodes (i.e., rows) of Hmatrix 300 of
Sign memory 414, which stores 132,000 bits, receives 24 sign bits (sign(L(q_{nm})) during each clock cycle, one from each CNU 404, and outputs 24 sign bits (sign(L(q_{nm})) during each clock cycle that are 5,500 clock cycles old. Each of the 24 sign bits output are provided to a different R selector 422. Similar to min memory 416, the bits read out of sign memory 414 may correspond to (i) an iteration or (ii) a codeword that is different from the bits written into sign memory 414. Sign memory 414 may be implemented, for example, as dualport RAM comprising 5,500 addresses (i.e., 132,000 bits/24 bits per address), each address having a width of 24 bits. The sign bits may be written such that the bits corresponding to the 1^{st }through 24^{th }check nodes of Hmatrix 300 are always written to address 0, the bits corresponding to the 25^{th }through 48^{th }check nodes are always written to address 1, the bits corresponding to the 49^{th }through 72^{nd }check nodes are always written to address 2, and so on.
As an alternative, sign memory 414 may be implemented as singleport RAM having a width equal to four times (i.e., 4×24 bits) that of the dualport RAM described above, and which is clocked at half of the full clock speed of LDPC decoder 400. In such implementations, 4×24 bits may be read out of the singleport RAM during a first set of two full clock cycles (i.e., 24 bits per half clock cycle) and 4×24 bits may be written to the singleport RAM during a second set of two full clock cycles (i.e., 24 bits per half clock cycle). Thus, 4×24 bits are read out and 4×24 bits are written to the singleport RAM every four full clock cycles.
During each of the 11 clock cycles, SMT2 converter 606 receives a different sign product s_{mn }from OR gate 602. Each sign product s_{mn }is generated as shown in Equation (3) by applying both (i) the sign product (e.g., 522) generated by a CNU and (ii) a sign bit (the MSB of a variablenode message L(q_{nm})) received from a sign memory 414 or delay buffer 406 of
Referring back to
L(q _{n})=L(q _{nm})+R _{mn } (4)
The softoutput messages L(q_{n}), each of which corresponds to one bit of the encoded codeword, are provided to L(q_{n}) memory 418 at a rate of 24 messages per clock cycle, and are written to addresses of L(q_{n}) memory 418 (discussed below in relation to
Syndrome calculator 412 performs a parity check to determine whether LDPC decoder 400 has converged on a valid codeword. In general, if {circumflex over (x)}H^{T}=0, where H^{T }is the transpose of Hmatrix 300 of
During each clock cycle, L(q_{n}) memory 418 provides sets of 24 softoutput messages L(q_{n}) to barrel shifter 424. Barrel shifter 424 cyclically shifts the messages that it receives based on a shift signal that may be received from, for example, ROM 420. The cyclicshift signal corresponds to cyclicshift factors of the submatrices of Hmatrix 300 of
Adders 426(1)(24) receive (i) 24 cyclicallyshifted softoutput messages L(q_{n}) per clock cycle from barrel shifter 424 and (ii) 24 checknode messages R_{mn }per clock cycle from R selectors 422(1)(24). Each adder 426 subtracts a checknode message R_{mn }from a corresponding cyclicallyshifted softoutput message L(q_{n}) to generate an updated variablenode (i.e., column) message L(q_{nm}) as shown below in Equation (5):
L(q _{nm})=L(q _{n})−R _{mn } (5)
The updated variablenode messages L(q_{nm}) are subsequently provided to the upper input of multiplexer 402 at a rate of 24 messages per clock cycle for use in processing the next layer of Hmatrix 300 or the next iteration of LDPC decoder 400. Note that, as the updated variablenode messages L(q_{nm}) are output from adders 426(1)(24), multiplexer 402 selects the updated variablenode messages L(q_{nm}), such that LDPC decoder 400 may begin processing the next layer, without having to wait until all of the updated variablenode messages L(q_{nm}) are generated by adders 426(1)(24).
In general, during each clock cycle, syndrome calculator 700 receives 24 hard decisions {circumflex over (x)}_{n}, each corresponding to one paritycheck equation (i.e., row) in each of the four layers of Hmatrix 300 of
In general, first branch 706 performs the paritycheck updates for the first 24 rows of Hmatrix 300 during the first 11 clock cycles, the updates for rows 25 through 48 during the 12^{th }through 22^{nd }clock cycles, the updates for rows 49 through 72 during the 23^{rd }through 33^{rd }clock cycles, and so on, until all paritycheck equations of the first layer of Hmatrix 300 have been updated. During the first clock cycle, the first set of 24 hard decisions {circumflex over (x)}_{n }received corresponds to the first block column (i.e., the first 24 columns) of Hmatrix 300. Since the submatrix corresponding to the first block row and first block column of Hmatrix 300 (i.e., identity matrix I_{1,1}) is an identity matrix, the 1^{st }through 24^{th }hard decisions {circumflex over (x)}_{n }of the first set correspond to the 1^{st }through 24^{th }paritycheck equations (i.e., rows), respectively. Thus, the first set of hard decisions {circumflex over (x)}_{n }is used to update the first 24 paritycheck equations (i.e., rows). In so doing, the 24 hard decisions {circumflex over (x)}_{n }are applied to XOR gates 702(1)(24) along with 24 paritycheck bits stored in flipflops 704(1)(24), such that one hard decision {circumflex over (x)}_{n }and one paritycheck bit are applied to each XOR gate 702. The 24 paritycheck bits stored in flipflops 704(1)(24) may be initialized to 0. Each XOR gate 702 outputs an updated paritycheck bit to a different one of the 24 flipflops 704.
During the second clock cycle, a second set of 24 hard decisions {circumflex over (x)}_{n }is received that corresponds to the second block column (i.e., columns 25 through 48) of Hmatrix 300. Since the submatrix corresponding to the first block row and second block column of Hmatrix 300 (i.e., identity matrix I_{1,2}) is an identity matrix, the 1^{st }through 24^{th }hard decisions {circumflex over (x)}_{n }of the second set correspond to the 1^{st }through 24^{th }paritycheck equations (i.e., rows), respectively. Thus, these hard decisions {circumflex over (x)}_{n }are used to update the 24 paritycheck bits corresponding to the first 24 rows of Hmatrix 300 by applying the 24 hard decisions {circumflex over (x)}_{n }to XOR gates 702(1)(24) along with the 24 updated paritycheck bits stored in flipflops 704(1)(24). This process is repeated for the third through 11^{th }clock cycles.
Once all 11 updates have been performed for the first block row, controller 722 determines whether all 24 paritycheck bits stored in flipflops 704(1)(24) are equal to 0. In so doing, controller 722 may apply all 24 paritycheck bits to an OR gate to generate a singlebit value. If the singlebit value is 1, then one or more of the 24 paritycheck bits are equal to 1. In this case, the parity check is not satisfied for the first 24 paritycheck equations, and LDPC decoder 400 may need to perform decoding for the next layer or perform another iteration to correctly decode the codeword. If the singlebit value is 0, then all of the 24 paritycheck bits are equal to 0. In this case, the parity check is satisfied for the first 24 paritycheck equations, and LDPC decoder 400 continues to determine whether the remaining paritycheck equations of Hmatrix 300 are satisfied. First branch 706 then repeats this process to perform the updates for the paritycheck equations corresponding to identity matrices I_{2,12 }through I_{2,22 }during the 12^{th }through 22^{nd }clock cycles, followed by the updates for the paritycheck equations corresponding to identity matrices I_{3,23 }through I_{3,33 }during the 23^{rd }through 33^{rd }clock cycles, and so on. Note that, for each new set of 24 paritycheck equations processed, the flipflops 704(1)(24) are initialized to 0.
Typically, branches 714, 716, and 718 will perform the paritycheck (i.e., row) updates in a more random order than that of first branch 706 because the second through fourth layers (H_{LAYER2}H_{LAYER4}) of Hmatrix 300 might not be arranged in the same pattern as the first layer (H_{LAYER1}). For example, as described above, the first set of 24 hard decisions {circumflex over (x)}_{n }received during the first clock cycle correspond to the first block column (i.e., the first 24 columns) of Hmatrix 300. However, these 24 hard decisions {circumflex over (x)}_{n }might not, depending on the arrangement of the second layer (H_{LAYER2}), correspond to the first 24 paritycheck equations (i.e., rows) of the second layer (H_{LAYER2}). Rather, they might correspond to, for example, the third set of 24 paritycheck equations. During the second clock cycle, the second set of 24 hard decisions {circumflex over (x)}_{n}, which correspond to the second set of 24 columns, might, for example, correspond to the fifth set of 24 paritycheck equations (i.e., rows) of the second layer (H_{LAYER2}). During the third clock cycle, the third set of 24 hard decisions {circumflex over (x)}_{n}, which correspond to the second set of 24 columns, might correspond to the third set of 24 paritycheck equations (i.e., rows), the fifth set of 24 paritycheck equations, or another set of 24 paritycheck equations of the second layer (H_{LAYER2}). Thus, depending on the arrangement of the second layer (H_{LAYER2}), second branch 714 might not perform all 11 updates for each of the first 24 paritycheck equations together. Rather, second branch 714 might jump around from one set of 24 paritycheck equations to another set of 24 paritycheck equations every clock cycle.
Branches 714, 716, and 718 process the sets of 24 hard decisions {circumflex over (x)}_{n }that they receive in the same general manner using a barrel shifter (i.e., 708(1), 708(2), 708(3)), 24 XOR gates (i.e., 710(1)(24), 710(25)(48), and 710(49)(72)), and a dualport register file (i.e., 712(1), 712(2), 712(3)). For ease of discussion, the operation of branch 714 is described. This description may be extended to branches 716 and 718.
During each clock cycle, barrel shifter 708(1) cyclically shifts the set of 24 hard decisions n that it receives based on a cyclicshift signal received from, for example, ROM 720. The cyclicshift signal is based on the cyclicshift factors of the submatrices of the second layer (H_{LAYER2}) of Hmatrix 300. The 24 cyclicallyshifted hard decisions {circumflex over (x)}_{n }are applied to XOR gates 710(1)(24) along with 24 paritycheck bits stored in dualport register file 712(1) to generate 24 updated paritycheck bits that are subsequently stored in dualport register file 712(1).
Dualport register file 712(1), which stores 24×125 paritycheck bits, one for each paritycheck equation, has 125 addresses, one for each block row (i.e., set of 24 rows) of second layer (H_{LAYER2}) of Hmatrix 300. Each address stores 24 paritycheck bits, each corresponding to one paritycheck equation (i.e., row) of the second layer (H_{LAYER2}). All 24×125 paritycheck bits are stored because, as described above, branch 714 might perform the 11 updates for each of the paritycheck equations in a random order rather than performing the 11 updates consecutively. The sets of 24 paritycheck bits are read from and written to addresses of dualport register file 712(1) provided by controller 722 and may be initialized to 0 during the first clock cycle.
Once all 11 updates have been performed for each of the 24×125 paritycheck equations of branch 714, controller 722 determines whether the 24×125 paritycheck bits are equal to 0. In so doing, controller 722 may apply all 24×125 paritycheck bits to an OR gate to generate a singlebit value. If the singlebit value is 1, then one or more of the 24×125 paritycheck bits are equal to 1. In this case, the parity check is not satisfied for the second layer (H_{LAYER2}), and LDPC decoder 400 may need to perform decoding for the next layer or perform another iteration to correctly decode the codeword. If the singlebit value is 0, then all of the 24×125 paritycheck bits are equal to 0. In this case, the parity check is satisfied for the second layer (H_{LAYER2}). The same process is performed for layers three and four (H_{LAYER3}, H_{LAYER4}) of Hmatrix 300 in parallel with layers one and two (H_{LAYER1}, H_{LAYER2}), and, if syndrome calculator 700 determines that the paritycheck bits for all four layers are satisfied, then decoding is complete. Otherwise, decoding continues for another layer or iteration. Alternatively, the 24×125 paritycheck bits can be applied to a 24operand OR gate sequentially as follows: Whenever all 11 updates have been performed for a certain group of 24 parity checks, then apply these updated 24 parity checks to a 24operand OR gate and check the singlebit value of the ORgate.
RAM 804 and RAM 806 each have (i) a data input port (Data) that receives sets of 24 softoutput messages L(q_{n}) (i.e., 120 bits), (ii) a write enable port (WE) that receives a write enable control signal (Write_Enable) from, for example, a controller, (iii) an address input port (Addr) that receives tenbit addresses from, for example, ROM 420 of
During the 5^{th }through 6^{th }sets of 1,375 clock cycles, LDPC decoder 400 performs the second iteration by updating the messages corresponding to the first through second layers (H_{LAYER1}H_{LAYER2}), respectively. In this example, CW1 is successfully decoded at the end of the second layer (H_{LAYER2}). Thus, decoding is terminated before processing of the second iteration is complete. Note that, in practice, codewords may be successfully decoded during the processing of other layers or iterations or they might not be successfully decoded at all. During the seventh set of 1,375 clock cycles, the 33,000 soft values L_{n} ^{(0) }corresponding to a second codeword (CW2) are loaded into LDPC decoder 400 via multiplexer 402. At the same time, LDPC decoder 400 (i) performs the message updating for CW2 corresponding to the first layer (H_{LAYER1}) of Hmatrix 300 of
Since CW1 is unloaded at the same time that CW2 is loaded, the unloading of CW1 adds little to no delay to the decoding of CW2. However, note that up to 11 idle clock cycles might be needed between each set of 1,375 clock cycles to update the softoutput messages L(q_{n}) depending on the arrangement of the submatrices of Hmatrix 300. In generating the layers of Hmatrix 300, the submatrices may be arranged to minimize or even eliminate the number of idle clock cycles.
It will be further understood that various changes in the details, materials, and arrangements of the parts which have been described and illustrated in order to explain the nature of this invention may be made by those skilled in the art without departing from the scope of the invention as expressed in the following claims. For example, embodiments of the present invention may be envisioned in which barrel shifter 424 is positioned upstream of L(q_{n}) memory 418, rather than downstream of L(q_{n}) memory 418. Further, rather than using two sets of 24 R selectors (e.g., 408(1)(24) and 422(1)(24)), embodiment the present invention may use (i) one set of 24 R selectors (e.g., 408(1)(24)) and (ii) additional memory to store all of the checknode messages generated by the set of 24 R selectors for processing later in time by adders 426(1)(24). As another example, embodiments of the present invention may be envisioned that implement a suitable checknode algorithm other than the minsum checknode algorithm.
Although one embodiment has been described for each block of hardware of LDPC decoder 400 of
As described above, various embodiments of the first layer (H_{LAYER1}) of Hmatrix 300 may be envisioned that support processing of softoutput values without having to wait for all of the softoutput values to be generated. As an example, various embodiments may be envisioned in which groups of 11 identity matrices are not arranged along the diagonal as is shown in
As another example, the eleven identity matrices in each block row may be separated by, for example, zero matrices. For example, the eleven identity matrices in the first block row may be located in block columns 1, 3, . . . , 21, with zero matrices in block columns 2, 4, . . . , 22, and the eleven identity matrices in the second block row may be located in block columns 2, 4, . . . , 22, with zero matrices in block columns 1, 3, . . . , 21. Such embodiments may require a buffer, for example, at the inputs of multiplexer 402.
As yet another example, various embodiments may be envisioned in which submatrices of the first layer (H_{LAYER1}) are implemented as circulants rather than identity matrices. Such embodiments may require additional hardware, such as an additional barrel shifter upstream of multiplexer 402.
The present invention may be implemented for various Hmatrices that are the same size as or a different size from Hmatrix 300 of
While the present invention was described relative to its use with regular Hmatrices (i.e., Hmatrices wherein the hamming weights of all columns are the same and the hamming weight of all rows are the same), the present invention is not so limited. The present invention may also be implemented for Hmatrices that are irregular (i.e., Hmatrices wherein the hamming weights of all columns are not the same and the hamming weight of all rows are not the same).
Further, the present invention is not limited to use with quasicyclic Hmatrices. VNUs and LDPC decoders of the present invention may be used with Hmatrices that are either partially quasicyclic or fully noncyclic. Partially quasicyclic LDPC codes are LDPC codes that comprise (i) one or more cyclic submatrices that are either equal to an identity matrix or are obtained by cyclically shifting an identity matrix and (ii) one or more noncyclic submatrices that are not equal to an identity matrix and can not be obtained by cyclically shifting an identity matrix. LDPC codes that are fully noncyclic do not have any cyclic submatrices. In various embodiments that employ either partially quasicyclic or fully noncyclic Hmatrices, the VNUs and check node units (CNUs) may be interconnected using, for example, fixed connections or programmable crossbars in lieu of barrel shifters.
The present invention is also not limited to receiving and processing loglikelihood ratios. Various embodiments of the present invention may be envisioned in which other soft values, such as likelihood ratios, or hard bit decisions are processed.
Further, the present invention is not limited to use with the layered LDPC decoder configuration of
The present invention may be implemented as circuitbased processes, including possible implementation as a single integrated circuit (such as an ASIC or an FPGA), a multichip module, a single card, or a multicard circuit pack. As would be apparent to one skilled in the art, various functions of circuit elements may also be implemented as processing blocks in a software program. Such software may be employed in, for example, a digital signal processor, microcontroller, or generalpurpose computer.
The present invention can be embodied in the form of methods and apparatuses for practicing those methods. The present invention can also be embodied in the form of program code embodied in tangible media, such as magnetic recording media, optical recording media, solid state memory, floppy diskettes, CDROMs, hard drives, or any other machinereadable storage medium, wherein, when the program code is loaded into and executed by a machine, such as a computer, the machine becomes an apparatus for practicing the invention. The present invention can also be embodied in the form of program code, for example, whether stored in a storage medium, loaded into and/or executed by a machine, or transmitted over some transmission medium or carrier, such as over electrical wiring or cabling, through fiber optics, or via electromagnetic radiation, wherein, when the program code is loaded into and executed by a machine, such as a computer, the machine becomes an apparatus for practicing the invention. When implemented on a generalpurpose processor, the program code segments combine with the processor to provide a unique device that operates analogously to specific logic circuits. The present invention can also be embodied in the form of a bitstream or other sequence of signal values electrically or optically transmitted through a medium, stored magneticfield variations in a magnetic recording medium, etc., generated using a method and/or an apparatus of the present invention.
Unless explicitly stated otherwise, each numerical value and range should be interpreted as being approximate as if the word “about” or “approximately” preceded the value of the value or range.
The use of figure numbers and/or figure reference labels in the claims is intended to identify one or more possible embodiments of the claimed subject matter in order to facilitate the interpretation of the claims. Such use is not to be construed as necessarily limiting the scope of those claims to the embodiments shown in the corresponding figures.
It should be understood that the steps of the exemplary methods set forth herein are not necessarily required to be performed in the order described, and the order of the steps of such methods should be understood to be merely exemplary. Likewise, additional steps may be included in such methods, and certain steps may be omitted or combined, in methods consistent with various embodiments of the present invention.
Although the elements in the following method claims, if any, are recited in a particular sequence with corresponding labeling, unless the claim recitations otherwise imply a particular sequence for implementing some or all of those elements, those elements are not necessarily intended to be limited to being implemented in that particular sequence.
Claims (17)
Priority Applications (1)
Application Number  Priority Date  Filing Date  Title 

US12427786 US8578256B2 (en)  20090422  20090422  Lowlatency decoder 
Applications Claiming Priority (1)
Application Number  Priority Date  Filing Date  Title 

US12427786 US8578256B2 (en)  20090422  20090422  Lowlatency decoder 
Publications (2)
Publication Number  Publication Date 

US20100275088A1 true US20100275088A1 (en)  20101028 
US8578256B2 true US8578256B2 (en)  20131105 
Family
ID=42993200
Family Applications (1)
Application Number  Title  Priority Date  Filing Date 

US12427786 Active 20300330 US8578256B2 (en)  20090422  20090422  Lowlatency decoder 
Country Status (1)
Country  Link 

US (1)  US8578256B2 (en) 
Cited By (5)
Publication number  Priority date  Publication date  Assignee  Title 

US20140223259A1 (en) *  20130206  20140807  Lsi Corporation  Memory Architecture for Layered LowDensity ParityCheck Decoder 
US9485125B2 (en)  20140616  20161101  Raytheon Company  Dynamically reconfigurable channelizer 
US9590760B2 (en)  20140603  20170307  Raytheon Company  Analog RF memory system 
US9588213B2 (en)  20140218  20170307  Raytheon Company  Analog signal processing method for accurate single antenna direction finding 
US9645972B2 (en)  20140616  20170509  Raytheon Company  Butterfly channelizer 
Families Citing this family (19)
Publication number  Priority date  Publication date  Assignee  Title 

US8601352B1 (en) *  20090730  20131203  Apple Inc.  Efficient LDPC codes 
DE102010035210B4 (en) *  20100824  20120830  Deutsches Zentrum für Luft und Raumfahrt e.V.  A process for recovering lost data and to correct corrupted data 
JP5310701B2 (en) *  20101029  20131009  株式会社Ｊｖｃケンウッド  Decoding apparatus and decoding method 
JP2012124888A (en) *  20101115  20120628  Fujitsu Ltd  Decoder and decoding method 
JP5601182B2 (en) *  20101207  20141008  ソニー株式会社  Data processing apparatus, and a data processing method 
CN103166649B (en)  20111219  20160615  国际商业机器公司  A method for decoding cyclic codes, and a decoder means 
CN103297173B (en) *  20120224  20160803  国家广播电影电视总局广播科学研究院  The data transmission system of digital audio broadcasting reception method of dispensing apparatus 
US8977937B2 (en) *  20120316  20150310  Lsi Corporation  Systems and methods for compression driven variable rate decoding in a data processing system 
US8972826B2 (en)  20121024  20150303  Western Digital Technologies, Inc.  Adaptive error correction codes for data storage systems 
US9219504B2 (en) *  20121029  20151222  Avago Technologies General Ip (Singapore) Pte. Ltd.  LEH memory module architecture design in the multilevel LDPC coded iterative system 
US9021339B2 (en)  20121129  20150428  Western Digital Technologies, Inc.  Data reliability schemes for data storage systems 
US9059736B2 (en)  20121203  20150616  Western Digital Technologies, Inc.  Methods, solid state drive controllers and data storage devices having a runtime variable raid protection scheme 
US9116822B2 (en)  20121207  20150825  Micron Technology, Inc.  Stopping criteria for layered iterative error correction 
US9619317B1 (en) *  20121218  20170411  Western Digital Technologies, Inc.  Decoder having early decoding termination detection 
US8966339B1 (en)  20121218  20150224  Western Digital Technologies, Inc.  Decoder supporting multiple code rates and code lengths for data storage systems 
WO2014179502A1 (en) *  20130430  20141106  Western Digital Technologies, Inc.  Decoder having early decoding termination detection 
US9122625B1 (en)  20121218  20150901  Western Digital Technologies, Inc.  Error correcting code encoder supporting multiple code rates and throughput speeds for data storage systems 
US9214963B1 (en)  20121221  20151215  Western Digital Technologies, Inc.  Method and system for monitoring data channel to enable use of dynamically adjustable LDPC coding parameters in a data storage system 
US9350388B2 (en) *  20140307  20160524  Storart Technology Co. Ltd.  Data format with ECC information for onthefly decoding during data transfer and method for forming the data format 
Citations (30)
Publication number  Priority date  Publication date  Assignee  Title 

US20050018793A1 (en) *  20030724  20050127  Learned Rachel E.  Hybrid turbomud for multiple access systems 
US20050193320A1 (en)  20040209  20050901  President And Fellows Of Harvard College  Methods and apparatus for improving performance of information coding schemes 
US20050204255A1 (en)  20040312  20050915  NanHsiung Yeh  Cyclic redundancy check based message passing in Turbo Product Code decoding 
US20050283707A1 (en)  20040622  20051222  Eran Sharon  LDPC decoder for decoding a lowdensity parity check (LDPC) codewords 
US20060107181A1 (en)  20041013  20060518  Sameep Dave  Decoder architecture system and method 
US20060285852A1 (en)  20050621  20061221  Wenze Xi  Integrated maximum a posteriori (MAP) and turbo product coding for optical communications systems 
US20070011569A1 (en)  20050620  20070111  The Regents Of The University Of California  Variablerate lowdensity parity check codes with constant blocklength 
US20070011573A1 (en)  20050527  20070111  Ramin Farjadrad  Method and apparatus for extending decoding time in an iterative decoder using input codeword pipelining 
US20070011586A1 (en)  20040331  20070111  Belogolovy Andrey V  Multithreshold reliability decoding of lowdensity parity check codes 
US20070011568A1 (en) *  20020815  20070111  Texas Instruments Incorporated  HardwareEfficient Low Density Parity Check Code for Digital Communications 
US7181676B2 (en)  20040719  20070220  Texas Instruments Incorporated  Layered decoding approach for low density parity check (LDPC) codes 
US20070044006A1 (en)  20050805  20070222  Hitachi Global Technologies Netherlands, B.V.  Decoding techniques for correcting errors using soft information 
US20070071009A1 (en)  20050928  20070329  Thadi Nagaraj  System for early detection of decoding errors 
US20070124652A1 (en)  20051115  20070531  Ramot At Tel Aviv University Ltd.  Method and device for multi phase errorcorrection 
US20070147481A1 (en)  20051222  20070628  Telefonaktiebolaget Lm Ericsson (Publ)  Linear turbo equalization using despread values 
US20070162788A1 (en)  20031230  20070712  DignusJan Moelker  Method and device for calculating bit error rate of received signal 
US20070234184A1 (en)  20031222  20071004  Qualcomm Incorporated  Methods and apparatus for reducing error floors in message passing decoders 
US20070234178A1 (en)  20030226  20071004  Qualcomm Incorporated  Soft information scaling for interactive decoding 
US20080082868A1 (en)  20061002  20080403  Broadcom Corporation, A California Corporation  Overlapping submatrix based LDPC (low density parity check) decoder 
US20080104485A1 (en)  20050119  20080501  Mikhail Yurievich Lyakh  Data Communications Methods and Apparatus 
US20080109701A1 (en)  20061030  20080508  Motorola, Inc.  Turbo Interference Suppression in Communication Systems 
US20080126910A1 (en)  20060630  20080529  Microsoft Corporation  Low dimensional spectral concentration codes and direct list decoding 
US20080148129A1 (en)  20061214  20080619  Regents Of The University Of Minnesota  Error detection and correction using error pattern correcting codes 
US20080163032A1 (en)  20070102  20080703  International Business Machines Corporation  Systems and methods for error detection in a memory system 
US20080235561A1 (en)  20070323  20080925  Quantum Corporation  Methodology and apparatus for softinformation detection and LDPC decoding on an ISI channel 
US20080276156A1 (en)  20070501  20081106  Texas A&M University System  Low density parity check decoder for regular ldpc codes 
US20090100311A1 (en) *  20060429  20090416  Timi Technologies Co., Ltd.  Method of Constructing Low Density Parity Check Code, Method of Decoding the Same and Transmission System For the Same 
US20090273492A1 (en)  20080502  20091105  Lsi Corporation  Systems and Methods for Queue Based Data Detection and Decoding 
WO2010019168A1 (en)  20080815  20100218  Lsi Corporation  Ram listdecoding of near codewords 
US20100042806A1 (en)  20080815  20100218  Lsi Corporation  Determining index values for bits of a binary vector 
Patent Citations (33)
Publication number  Priority date  Publication date  Assignee  Title 

US20070011568A1 (en) *  20020815  20070111  Texas Instruments Incorporated  HardwareEfficient Low Density Parity Check Code for Digital Communications 
US20070234178A1 (en)  20030226  20071004  Qualcomm Incorporated  Soft information scaling for interactive decoding 
US20050018793A1 (en) *  20030724  20050127  Learned Rachel E.  Hybrid turbomud for multiple access systems 
US20070234184A1 (en)  20031222  20071004  Qualcomm Incorporated  Methods and apparatus for reducing error floors in message passing decoders 
US20070162788A1 (en)  20031230  20070712  DignusJan Moelker  Method and device for calculating bit error rate of received signal 
US20050193320A1 (en)  20040209  20050901  President And Fellows Of Harvard College  Methods and apparatus for improving performance of information coding schemes 
US20050204255A1 (en)  20040312  20050915  NanHsiung Yeh  Cyclic redundancy check based message passing in Turbo Product Code decoding 
US20070011586A1 (en)  20040331  20070111  Belogolovy Andrey V  Multithreshold reliability decoding of lowdensity parity check codes 
US20050283707A1 (en)  20040622  20051222  Eran Sharon  LDPC decoder for decoding a lowdensity parity check (LDPC) codewords 
US7181676B2 (en)  20040719  20070220  Texas Instruments Incorporated  Layered decoding approach for low density parity check (LDPC) codes 
US20060107181A1 (en)  20041013  20060518  Sameep Dave  Decoder architecture system and method 
US20080104485A1 (en)  20050119  20080501  Mikhail Yurievich Lyakh  Data Communications Methods and Apparatus 
US20070011573A1 (en)  20050527  20070111  Ramin Farjadrad  Method and apparatus for extending decoding time in an iterative decoder using input codeword pipelining 
US20070011569A1 (en)  20050620  20070111  The Regents Of The University Of California  Variablerate lowdensity parity check codes with constant blocklength 
US20060285852A1 (en)  20050621  20061221  Wenze Xi  Integrated maximum a posteriori (MAP) and turbo product coding for optical communications systems 
US20070044006A1 (en)  20050805  20070222  Hitachi Global Technologies Netherlands, B.V.  Decoding techniques for correcting errors using soft information 
US20070071009A1 (en)  20050928  20070329  Thadi Nagaraj  System for early detection of decoding errors 
US20070124652A1 (en)  20051115  20070531  Ramot At Tel Aviv University Ltd.  Method and device for multi phase errorcorrection 
US20070147481A1 (en)  20051222  20070628  Telefonaktiebolaget Lm Ericsson (Publ)  Linear turbo equalization using despread values 
US20090100311A1 (en) *  20060429  20090416  Timi Technologies Co., Ltd.  Method of Constructing Low Density Parity Check Code, Method of Decoding the Same and Transmission System For the Same 
US20080126910A1 (en)  20060630  20080529  Microsoft Corporation  Low dimensional spectral concentration codes and direct list decoding 
US20080082868A1 (en)  20061002  20080403  Broadcom Corporation, A California Corporation  Overlapping submatrix based LDPC (low density parity check) decoder 
US20080109701A1 (en)  20061030  20080508  Motorola, Inc.  Turbo Interference Suppression in Communication Systems 
US20080148129A1 (en)  20061214  20080619  Regents Of The University Of Minnesota  Error detection and correction using error pattern correcting codes 
US20080163032A1 (en)  20070102  20080703  International Business Machines Corporation  Systems and methods for error detection in a memory system 
US20080235561A1 (en)  20070323  20080925  Quantum Corporation  Methodology and apparatus for softinformation detection and LDPC decoding on an ISI channel 
US20080276156A1 (en)  20070501  20081106  Texas A&M University System  Low density parity check decoder for regular ldpc codes 
US20080301521A1 (en)  20070501  20081204  Texas A&M University System  Low density parity check decoder for irregular ldpc codes 
US20090273492A1 (en)  20080502  20091105  Lsi Corporation  Systems and Methods for Queue Based Data Detection and Decoding 
WO2010019168A1 (en)  20080815  20100218  Lsi Corporation  Ram listdecoding of near codewords 
US20100042890A1 (en)  20080815  20100218  Lsi Corporation  Errorfloor mitigation of ldpc codes using targeted bit adjustments 
US20100042806A1 (en)  20080815  20100218  Lsi Corporation  Determining index values for bits of a binary vector 
US20100241921A1 (en) *  20080815  20100923  Lsi Corporation  Errorcorrection decoder employing multiple checknode algorithms 
NonPatent Citations (71)
Title 

Amin Shokrollahi"LDPC Codes: An Introduction, In Coding, Cryptography and Combinatorics",Computer Science and Applied Logic, Birkhauser, Basel, 2004, pp. 85110, vol. 23. 
Amin Shokrollahi—"LDPC Codes: An Introduction, In Coding, Cryptography and Combinatorics",Computer Science and Applied Logic, Birkhauser, Basel, 2004, pp. 85110, vol. 23. 
Andrew J. Blanksby and Chris J. Howland"A 690mW 1Gb/s 1024b, Rate1/2 LowDensity ParityCheck Code Decoder", IEEE Journal of SolidState Circuits, Mar. 2002.pp. 404412,vol. 37, No. 3. 
Andrew J. Blanksby and Chris J. Howland—"A 690mW 1Gb/s 1024b, Rate1/2 LowDensity ParityCheck Code Decoder", IEEE Journal of SolidState Circuits, Mar. 2002.pp. 404412,vol. 37, No. 3. 
Badri N. Vellambi R, and Faramarz Fekri, "An Improved Decoding Algorithm for LowDensity ParityCheck Codes over the Binary Erasure Channel", IEEE GLOBECOM 2005 proceedings, pp. 11821186. 
Cavus et al., "A Performance Improvement and Error Floor Avoidance Technique for Belief Propagation Decoding of LDPC Codes," IEEE 16th International Symposium, Personal, Indoor & Mobile Radio Communications (PIMRC), Berlin, Germany Sep. 1114, 2005, pp. 23862390. 
Cavus, Enver et al., "An IS Simulation Technique for Very Low BER Performance Evaluation of LDPC Codes," IEEE International Conference on Communications, Jun. 1, 2006, pp. 10951100. 
Cole, Chad A. and Hall, Eric K., "Analysis and Design of Moderate Length Regular LDPC Codes with Low Error Floors," Proc, 40th Conf. Information Sciences and Systems, Princeton, NJ, 2006, 6 pgs. 
D.J.C. Mackay and R.M. Neal"Near Shannon limit performance of low density parity check codes", Electronics Letters Mar. 13, 1997, pp. 458459, vol. 33 No. 6. 
D.J.C. Mackay and R.M. Neal—"Near Shannon limit performance of low density parity check codes", Electronics Letters Mar. 13, 1997, pp. 458459, vol. 33 No. 6. 
Dale E. Hocevar"A Reduced Complexity Decoder Architecture Via Layered Decoding of LDPC Codes", IEEE Workshop on Signal Processing Systems, 2004, pp. 107112. 
Dale E. Hocevar—"A Reduced Complexity Decoder Architecture Via Layered Decoding of LDPC Codes", IEEE Workshop on Signal Processing Systems, 2004, pp. 107112. 
David J.C. MacKay"Information Theory, Inference, and Learning Algorithms", Cambridge University Press Sep. 2003, pp. 640. 
David J.C. MacKay—"Information Theory, Inference, and Learning Algorithms", Cambridge University Press Sep. 2003, pp. 640. 
E. Papagiannis, C. Tjhai, M. Ahmed, M. Ambroze, M. Tomlinson"Improved Iterative Decoding for Perpendicular Magnetic Recording", The ISCTA 2005 Conference on Feb. 4, 2005,pp. 14. 
E. Papagiannis, C. Tjhai, M. Ahmed, M. Ambroze, M. Tomlinson—"Improved Iterative Decoding for Perpendicular Magnetic Recording", The ISCTA 2005 Conference on Feb. 4, 2005,pp. 14. 
Gunnam, Kiran K., Choi, Gwan S., and Yeary, Mark B., "Technical Note on Iterative LDPC Solutions for Turbo Equalization," Texas A&M Technical Note, Department of ECE, Texas A&M University, College Station, TX 77843, Jul. 2006 (available online at http://dropzone.tamu.edu), pp. 15. 
Gunnam, Kiran K., et al. "Decoding of Quasicyclic LDPC Codes Using an OntheFly Computation," Signals, Systems and Computers, 2006, ACSSC '06. Fortieth Asilomar Conference on Oct.Nov. 2006;pp. 11921197. 
Hao Zhong,Tong Zhang"BlockLDPC: A Practical LDPC Coding System Design Approach", IEEE transactions on circuits and systemsI: Regular Papers, Apr. 2005, pp. 766775, vol. 52. 
Hao Zhong,Tong Zhang—"Block—LDPC: A Practical LDPC Coding System Design Approach", IEEE transactions on circuits and systems—I: Regular Papers, Apr. 2005, pp. 766775, vol. 52. 
Jinghu Chen, Ajay Dholakia, Evangelos Eleftheriou, Marc P. C. Fossorier, XiaoYu Hu, "ReducedComplexity Decoding of LDPC Codes", IEEE Transactions on Communications, Aug. 2005, pp. 12881299,vol. 53, No. 8. 
K. Gunnam "Area and Energy Efficient VLSI Architectures for LowDensity ParityCheck Decoders Using an OnTheFly Computation" dissertation at Texas A&M University, Dec. 2006. 
K. Gunnam et al., "ValueReuse Properties of MinSum for GF (q)" (dated Jul. 2008) Dept. of ECE, Texas A&M University Technical Note, published about Aug. 2010. 
K. Gunnam et al., "ValueReuse Properties of MinSum for GF(q)" (dated Oct. 2006) Dept. of ECE, Texas A&M University Technical Note, published about Aug. 2010. 
Kiran Gunnam, Gwan Choi, Mark Yeary"An LDPC decoding schedule for memory acces reduction", IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP) 2004, pp. 173176, vol. I5. 
Kiran Gunnam, Gwan Choi, Mark Yeary—"An LDPC decoding schedule for memory acces reduction", IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP) 2004, pp. 173176, vol. I5. 
Kiran Gunnam, Gwan Choi, Weihuang Wang, Mark Yeary"MultiRate Layered Decoder Architecture for Block LDPC Codes of the IEEE 802, 11n Wireless Standard", IEEE International Symposium on Circuits and Systems (ISCAS) 2007, pp. 16451648. 
Kiran Gunnam, Gwan Choi, Weihuang Wang, Mark Yeary—"MultiRate Layered Decoder Architecture for Block LDPC Codes of the IEEE 802, 11n Wireless Standard", IEEE International Symposium on Circuits and Systems (ISCAS) 2007, pp. 16451648. 
Kiran Gunnam, Weihuang Wang, Gwan Choi, Mark Yeary"VLSI Architectures for Turbo Decoding Message Passing Using MinSum for RateCompatible Array LDPC Codes", 2nd International Symposium on Wireless Pervasive Computing (ISWPC), 2007, pp. 561566. 
Kiran Gunnam, Weihuang Wang, Gwan Choi, Mark Yeary—"VLSI Architectures for Turbo Decoding Message Passing Using MinSum for RateCompatible Array LDPC Codes", 2nd International Symposium on Wireless Pervasive Computing (ISWPC), 2007, pp. 561566. 
Kiran K. Gunnam, Gwan S. Choi, and Mark B. Yeary"A Parallel VLSI Architecture for Layered Decoding for Array LDPC Codes", 20th International Conference on VLSI Design, 2007,6th International Conference on Embedded Systems, Jan. 2007 pp. 738743. 
Kiran K. Gunnam, Gwan S. Choi, and Mark B. Yeary—"A Parallel VLSI Architecture for Layered Decoding for Array LDPC Codes", 20th International Conference on VLSI Design, 2007,6th International Conference on Embedded Systems, Jan. 2007 pp. 738743. 
Kiran K. Gunnam, Gwan S. Choi, Mark B. Yeary and Mohammed Atiquzzaman"VLSI Architectures for Layered Decoding for Irregular LDPC Codes of WiMax", IEEE International Conference on Communications (ICC), 2007, pp. 45424547. 
Kiran K. Gunnam, Gwan S. Choi, Mark B. Yeary and Mohammed Atiquzzaman—"VLSI Architectures for Layered Decoding for Irregular LDPC Codes of WiMax", IEEE International Conference on Communications (ICC), 2007, pp. 45424547. 
Kiran K. Gunnam, Gwan S. Choi, Mark B. Yeary, Shaohua Yang and Yuanxing Lee"Next Generation Iterative LDPC Solutions for Magnetic Recording Storage", 42nd Asilomar Conference on Signals, Systems and Computers, 2008, pp. 11481152. 
Kiran K. Gunnam, Gwan S. Choi, Mark B. Yeary, Shaohua Yang and Yuanxing Lee—"Next Generation Iterative LDPC Solutions for Magnetic Recording Storage", 42nd Asilomar Conference on Signals, Systems and Computers, 2008, pp. 11481152. 
Kiran K. Gunnam, Gwan S. Choi, Weihuang Wang, and Mark B. Yeary"A Parallel VLSI Architecture for Layered Decoding",Proceedings of the 20th International Conference on VLSI Design, 6th International Conference: Embedded Systems, 2007, pp. 738743. 
Kiran K. Gunnam, Gwan S. Choi, Weihuang Wang, and Mark B. Yeary—"A Parallel VLSI Architecture for Layered Decoding",Proceedings of the 20th International Conference on VLSI Design, 6th International Conference: Embedded Systems, 2007, pp. 738743. 
Kiran K. Gunnam, Gwan S. Choi, Weihuang Wang, Euncheol Kim, and Mark B. Yeary"Decoding of Quasicyclic LDPC Codes Using an OntheFly Computation", Fortieth Asilomar Conference on Signals, Systems and Computers (ACSSC), 2006, pp. 11921199. 
Kiran K. Gunnam, Gwan S. Choi, Weihuang Wang, Euncheol Kim, and Mark B. Yeary—"Decoding of Quasicyclic LDPC Codes Using an OntheFly Computation", Fortieth Asilomar Conference on Signals, Systems and Computers (ACSSC), 2006, pp. 11921199. 
Mohammad M. Mansour and Naresh R. Shanbhag"Low Power VLSI decoder architectures for LDPC codes" International Symposium on Low Power Electronics and Design Proceedings of the 2002 , ICIMS Research Center, 2002, pp. 284289. 
Mohammad M. Mansour and Naresh R. Shanbhag—"Low Power VLSI decoder architectures for LDPC codes" International Symposium on Low Power Electronics and Design Proceedings of the 2002 , ICIMS Research Center, 2002, pp. 284289. 
Mohammad M. Mansour, and Naresh R. Shanbhag"A 640Mb/s 2048Bit Programmable LDPC Decoder Chip", IEEE Journal of SolidState Circuits, Mar. 2006, pp. 684698,vol. 41, No. 3. 
Mohammad M. Mansour, and Naresh R. Shanbhag—"A 640Mb/s 2048Bit Programmable LDPC Decoder Chip", IEEE Journal of SolidState Circuits, Mar. 2006, pp. 684698,vol. 41, No. 3. 
PCT International Search Report dated Feb. 12, 2009 from International Application No. PCT/US 08/86523. 
PCT International Search Report dated Feb. 9, 2009 from International Application No. PCT/US 08/86537. 
PCT International Search Report dated May 15, 2009 from International Application No. PCT/US 09/39279. 
PCT International Search Report dated May 15, 2009 from International Application No. PCT/US 09/39918. 
PCT International Search Report dated May 28, 2009 from International Application No. PCT/US 09/41215. 
R. Michael Tanner, Deepak Sridhara, Arvind Sridharan, Thomas E. Fuja, and Daniel J. Costello, Jr"LDPC Block and Convolutional Codes Based on Circulant Matrices", IEEE Transactions on Information Theory, Dec. 2004, pp. 29662984, vol. 50, No. 12. 
R. Michael Tanner, Deepak Sridhara, Arvind Sridharan, Thomas E. Fuja, and Daniel J. Costello, Jr—"LDPC Block and Convolutional Codes Based on Circulant Matrices", IEEE Transactions on Information Theory, Dec. 2004, pp. 29662984, vol. 50, No. 12. 
R.Michael Tanner"A Recursive Approach to Low Complexity Codes",IEEE transaction on Information Theory, Sep. 1981, pp. 533547,vol. IT27, No. 5. 
R.Michael Tanner—"A Recursive Approach to Low Complexity Codes",IEEE transaction on Information Theory, Sep. 1981, pp. 533547,vol. IT27, No. 5. 
Richardson, Tom, "Error Floors of LDPC Codes," Allerton Conf. on Communication, Control and Computing, (Monticello, Illinois), Oct. 2003, pp. 14261435. 
Robert G. Gallager"Low Density ParityCheck Codes",Cambridge Mass Jul. 1963,pp. 90. 
Robert G. Gallager—"Low Density Parity—Check Codes",Cambridge Mass Jul. 1963,pp. 90. 
Stefan Landner, Olgica Milenkovic"Algorithmic and Combinatorial Analysis of Trapping Sets in Structured LDPC Codes", International Conference on Wireless Networks, Communications and Mobile Computing, 2005, pp. 630635, vol. 1. 
Stefan Landner, Olgica Milenkovic—"Algorithmic and Combinatorial Analysis of Trapping Sets in Structured LDPC Codes", International Conference on Wireless Networks, Communications and Mobile Computing, 2005, pp. 630635, vol. 1. 
T. Richardson and R. Urbanke"Modern Coding Theory", Cambridge University Press, Preliminary versionOct. 18, 2007, pp. 590. 
T. Richardson and R. Urbanke—"Modern Coding Theory", Cambridge University Press, Preliminary version—Oct. 18, 2007, pp. 590. 
Thomas J. Richardson and Rudiger L. Urbanke"Efficient Encoding of LowDensity ParityCheck Codes", IEEE Transactions on Information Theory, Feb. 2001,pp. 638656,vol. 47, No. 2. 
Thomas J. Richardson and Rudiger L. Urbanke—"Efficient Encoding of LowDensity ParityCheck Codes", IEEE Transactions on Information Theory, Feb. 2001,pp. 638656,vol. 47, No. 2. 
Tom Richardson"Error Floors of LDPC Codes", IEEE Transactions on Information Theory, Feb. 2001, pp. 14261435,vol. 47, No. 2. 
Tom Richardson—"Error Floors of LDPC Codes", IEEE Transactions on Information Theory, Feb. 2001, pp. 14261435,vol. 47, No. 2. 
Vila Casado, Andres I. "Variablerate Lowdenisty Paritycheck Codes with Constant Blocklength," UCLA Technologies Available for Licensing Copyright © 2009 The Regents of the University of California. http://www.research.ucla.edu/tech/ucla05074.htm (2 pages). 
Vila Casado, Andres I., Weng, WenYen and Wesel, Richard D. "Multiple Rate LowDensity ParityCheck Codes with Constant Blocklength," IEEE 2004, pp. 20102014. 
Vila Casado, Andres I., Weng, WenYen, Valle, Stefano and Wesel, Richard D. "MultipleRate LowDensity ParityCheck Codes with Constant Blocklength," IEEE Transactions on Communications, vol. 57, No. 1, Jan. 2009; pp. 7583. 
Yang Han and William E. Ryan"LDPC Decoder Strategies for Achieving Low Error Floors", Proceedings of Information Theory and Applications Workshop, San Diego, CA, Jan. 2008, pp. 110. 
Yang Han and William E. Ryan—"LDPC Decoder Strategies for Achieving Low Error Floors", Proceedings of Information Theory and Applications Workshop, San Diego, CA, Jan. 2008, pp. 110. 
Yang Han, William E. Ryan"LowFloor Decoders for LDPC Codes", IEEE Transactions on Communications, vol. 57, No. 6, Jun. 2009, pp. 16631673. 
Yang Han, William E. Ryan—"LowFloor Decoders for LDPC Codes", IEEE Transactions on Communications, vol. 57, No. 6, Jun. 2009, pp. 16631673. 
Cited By (6)
Publication number  Priority date  Publication date  Assignee  Title 

US20140223259A1 (en) *  20130206  20140807  Lsi Corporation  Memory Architecture for Layered LowDensity ParityCheck Decoder 
US9037952B2 (en) *  20130206  20150519  Avago Technologies General Ip (Singapore) Pte. Ltd.  Memory architecture for layered lowdensity paritycheck decoder 
US9588213B2 (en)  20140218  20170307  Raytheon Company  Analog signal processing method for accurate single antenna direction finding 
US9590760B2 (en)  20140603  20170307  Raytheon Company  Analog RF memory system 
US9485125B2 (en)  20140616  20161101  Raytheon Company  Dynamically reconfigurable channelizer 
US9645972B2 (en)  20140616  20170509  Raytheon Company  Butterfly channelizer 
Also Published As
Publication number  Publication date  Type 

US20100275088A1 (en)  20101028  application 
Similar Documents
Publication  Publication Date  Title 

US7174495B2 (en)  LDPC decoder, corresponding method, system and computer program  
US8006161B2 (en)  Apparatus and method for receiving signal in a communication system using a low density parity check code  
US7133853B2 (en)  Methods and apparatus for decoding LDPC codes  
US20050229087A1 (en)  Decoding apparatus for lowdensity paritycheck codes using sequential decoding, and method thereof  
US7996746B2 (en)  Structured lowdensity paritycheck (LDPC) code  
Gunnam et al.  VLSI architectures for layered decoding for irregular LDPC codes of WiMax  
US20100042890A1 (en)  Errorfloor mitigation of ldpc codes using targeted bit adjustments  
US7127659B2 (en)  Memory efficient LDPC decoding methods and apparatus  
US8069390B2 (en)  Universal error control coding scheme for digital communication and data storage systems  
US7246304B2 (en)  Decoding architecture for low density parity check codes  
EP1990921A2 (en)  Operational parameter adaptable LDPC (low density parity check) decoder  
US8359522B2 (en)  Low density parity check decoder for regular LDPC codes  
US7219288B2 (en)  Running minimum message passing LDPC decoding  
US20050149840A1 (en)  Apparatus for encoding and decoding of lowdensity paritycheck codes, and method thereof  
US7730377B2 (en)  Layered decoding of low density parity check (LDPC) codes  
US20070245217A1 (en)  Lowdensity parity check decoding  
US20100023838A1 (en)  Quasicyclic LDPC (Low Density Parity Check) code construction  
US7299397B2 (en)  Decoding apparatus, decoding method, and program to decode low density parity check codes  
US20110320902A1 (en)  Conditional skiplayer decoding  
US8127209B1 (en)  QCLDPC decoder with listsyndrome decoding  
Gunnam et al.  A parallel VLSI architecture for layered decoding for array LDPC codes  
Zhang et al.  Reducedcomplexity decoder architecture for nonbinary LDPC codes  
US8504887B1 (en)  Low power LDPC decoding under defects/erasures/puncturing  
Gunnam et al.  Multirate layered decoder architecture for block LDPC codes of the IEEE 802.11 n wireless standard  
US20080263425A1 (en)  Turbo LDPC Decoding 
Legal Events
Date  Code  Title  Description 

AS  Assignment 
Owner name: AGERE SYSTEMS INC., PENNSYLVANIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:GRAEF, NILS;REEL/FRAME:022577/0463 Effective date: 20090417 

AS  Assignment 
Owner name: AGERE SYSTEMS LLC, PENNSYLVANIA Free format text: CERTIFICATE OF FORMATION/CERTIFICATE OF CONVERSION;ASSIGNOR:AGERE SYSTEMS INC.;REEL/FRAME:031326/0800 Effective date: 20120723 

AS  Assignment 
Owner name: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AG Free format text: PATENT SECURITY AGREEMENT;ASSIGNORS:LSI CORPORATION;AGERE SYSTEMS LLC;REEL/FRAME:032856/0031 Effective date: 20140506 

AS  Assignment 
Owner name: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:AGERE SYSTEMS LLC;REEL/FRAME:035365/0634 Effective date: 20140804 

AS  Assignment 
Owner name: AGERE SYSTEMS LLC, PENNSYLVANIA Free format text: TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 0328560031);ASSIGNOR:DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT;REEL/FRAME:037684/0039 Effective date: 20160201 Owner name: LSI CORPORATION, CALIFORNIA Free format text: TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 0328560031);ASSIGNOR:DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT;REEL/FRAME:037684/0039 Effective date: 20160201 

AS  Assignment 
Owner name: BANK OF AMERICA, N.A., AS COLLATERAL AGENT, NORTH Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.;REEL/FRAME:037808/0001 Effective date: 20160201 

AS  Assignment 
Owner name: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD Free format text: TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS;ASSIGNOR:BANK OF AMERICA, N.A., AS COLLATERAL AGENT;REEL/FRAME:041710/0001 Effective date: 20170119 

FPAY  Fee payment 
Year of fee payment: 4 