JP2012124888A - Decoder and decoding method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an LDPC decoder that has a memory with reduced capacity for storing probability messages.SOLUTION: A decoder includes: a bit node processing unit which performs bit node processing in decoding processing of a cyclic-type LDPC code for each one-column block of a check matrix, and based on a probability message α in a one-column block, updates all probability messages β in the one-column block; and a check node processing unit which performs sequentially and in stages calculation of check node processing of one row in calculation of check node processing of each row of the check matrix based on one probability message β updated whenever one probability message β in the one row is updated, and sequentially outputs a probability message α after update in the one row after all probability messages β in the one row have been updated.

Description

  The present disclosure relates generally to a decoding device and a decoding method, and more particularly to a decoding device and a decoding method for decoding an LDPC code.

  In a transmission / reception method using an LDPC (Low Density Parity Check) code, a low-density check matrix H in which the number of 1s is much smaller than the number of 0s is used to perform error correction. The transmission signal Tx is transmitted so that H × Tx = 0 on the transmission side. Therefore, when the transmitted signal is correctly received on the receiving side, the received signal Rx satisfies the condition of H × Rx = 0. This calculation of H × Rx is called a parity check.

  On the receiving side, using an LDPC decoder that performs LDPC decoding, error correction is performed so that the decoded codeword Rx becomes H × Rx = 0. As a result, a received signal after error correction is obtained. In the LDPC decoding process, the probability information calculated from the probabilistic reliability information of the received signal is updated to obtain a received signal with a parity check result of zero. As the LDPC decoding algorithm, a Normalized Min-sum algorithm having a good correction capability is generally used.

FIG. 1 is a diagram illustrating a relationship between a parity check matrix and a probability message used in the Normalized Min-sum algorithm. The parity check matrix H shown in FIG. 1 is a 2-row block × 3-column block cyclic parity check matrix having a 3 × 3 unit matrix or a cyclic matrix thereof as a block (partial matrix). In the Normalized Min-sum algorithm, a probability message α and a probability message β are defined for each of all elements having a value of 1 among the elements of the check matrix H. In the example shown in FIG. 1, the subscripts mn of the probability messages α and β are such that m indicates a row of the check matrix and n indicates a column block of the check matrix. That is, for example, α _mn indicates the probability message α of the block in the n-th column in the m-th row.

  By repeating two processes called check node processing and bit node processing using these probability messages, the probability information calculated from the probabilistic reliability information of the received signal is updated, and the parity check result becomes zero. Such a received signal is obtained. Specifically, the check node process updates the probability message α using the probability message β. In the bit node processing, the probability message β is updated using the prior probability λ and the probability message α which are LLR (Log-Likelihood Ratio) derived from the received signal. At the same time, a decoded code word c is generated by bit node processing. After updating the probability message, it is determined by parity check whether the product of the check matrix H and the decoded codeword c (strictly, the product of H and the transposed matrix of c) becomes zero. If the result of the parity check is 0, the check is completed and c is output as the decoding result. If the result of the parity check is not 0, the update of the probability message α and the probability message β and the subsequent parity check are performed again.

FIG. 2 is a diagram schematically illustrating check node processing and bit node processing. In the check node process, all αs in one line are updated using all βs in one line. In the example of the 6 × 9 parity check matrix illustrated in FIG. 2, the check node processing for the first row R1 uses α _1,1 , β _1,2 , β _1,3 included in the first row R1 to obtain α _1,1 , α _1,2 and α _1,3 are updated. Thereafter, similarly, check node processing for the second to sixth rows is executed to update all α in the check matrix. After all α are updated, the bit node processing is executed next.

In the bit node processing, β is updated using all α in one column. In the example of the 6 × 9 parity check matrix illustrated in FIG. 2, β _1,1 using the LLR and α _1,1 and α _5,1 included in the first column C1 by the bit node processing for the first column C1. , Β _5,1 are updated. Thereafter, in the same manner, the bit node processing for the second column to the ninth column is executed, and all β in the parity check matrix are updated. When all βs are updated, the decoding result is subjected to parity check, and if the parity check result is not 0, check node processing is executed again.

  As described above, when the check node process and the bit node process are alternately executed, a memory for temporarily storing the probability message α or β updated by the check node process or the bit node process is required. The memory capacity needs to be “the number of 1s in the check matrix” × “the bit width of each message”, which increases the circuit scale. Furthermore, there is a problem that the number of cycles required for one iterative process becomes large due to the write and read processes to the memory.

  In general, in order to improve the processing speed, check node processing and bit node processing are not performed in units of row blocks and column blocks, but check node processing and bit node processing are performed in units of row blocks and column units as described above. Execute the process. For example, in the case of the parity check matrix shown in FIG. 1, check node processing is executed in parallel for every three rows, and bit node processing is executed in parallel for every three columns. However, even when parallel processing is performed in this way, if check node processing and bit node processing are executed alternately, a memory for temporarily storing the probability message updated by each processing is required. End up. Even if the degree of parallelism is further increased, a memory is similarly required as long as check node processing and bit node processing are executed alternately.

  Patent Document 1 proposes a method of performing check node processing and bit node processing at the same time by performing bit node processing from a difference between a check node message before update and a check node message after update. In this method, the circuit scale of the message RAM can be reduced as compared with the conventional method, but the RAM for the check node message and the message RAM for the SUM value before update are necessary.

JP 2008-154298 A JP 2007-89064 A JP 2007-110265 A JP 2007-20068 A

  In view of the above, an LDPC decoding device with a reduced memory for storing probability messages is desired.

  The decoding apparatus executes the bit node process in the decoding process of the cyclic LDPC code for each column block of the parity check matrix, and obtains all the probability messages β in the column block based on the probability message α in the column block. In the calculation of the check node processing for each row of the check matrix and the bit node processing unit to be updated, the check node processing calculation for one row is updated every time one probability message β in the one row is updated. Check node that sequentially performs stepwise based on the one probability message β and outputs the updated probability message α in the one row after all the probability messages β in the one row are updated And a processing unit.

  In the decoding method, the bit node process in the decoding process of the cyclic LDPC code is executed for each column block of the parity check matrix, and all the probability messages β in the column block are obtained based on the probability message α in the column block. In the calculation of the check node processing of each row of the check matrix, the calculation of the check node processing of one row is updated with one probability updated every time one probability message β in the one row is updated. The method includes performing each step sequentially based on the message β, and sequentially outputting the updated probability messages α in the one row after all the probability messages β in the one row are updated. And

  According to at least one embodiment of the present disclosure, the calculation of check node processing for each row is performed sequentially based on the updated probability message β every time one probability message β in the row is updated. It can be done in stages. Accordingly, the memory for storing the probability message β can be reduced or deleted. Since the calculation of the probability message α in the check node processing is based on the selection of the minimum value of the probability message β, if the minimum value of the probability message β is held, the probability message α can be sequentially calculated based on that. Accordingly, the memory for storing the probability message α can be reduced or deleted.

It is a figure which shows the relationship between a test matrix and the probability message used with the Normalized Min-sum algorithm. It is a figure which shows a check node process and a bit node process typically. It is a figure which shows an example of a structure of a communication system. It is a figure which shows an example of a structure of a LDPC decoding part. It is a figure which shows the structure of a cyclic | annular check matrix. It is a figure which shows the input-output relationship of a bit node process part and a check node process part. FIG. 7 is a diagram illustrating operations of a bit node processing unit and a check node processing unit illustrated in FIG. 6. 5 is a flowchart showing a flow of decoding processing of the LDPC decoding unit in FIG. 4. It is a figure which shows typically a mode that a bit node process is repeated for every column block. It is a figure which shows an example of a structure of one check node processing circuit of a check node processing part. It is a figure which shows an example of a structure of one bit node processing circuit of a bit node processing part. It is a figure which shows an example of the check matrix according to the application to the actual communication system using a LDPC code. It is a figure which shows an example of a structure of the LDPC decoding part corresponding to the check matrix of FIG. It is a figure which shows an example of operation | movement of the LDPC decoding part shown in FIG. It is a figure which shows another example of a structure of one check node processing circuit of a check node process part. FIG. 16 is a diagram illustrating a modification of the configuration of the LDPC decoding unit. It is a figure which shows the input-output relationship of a bit node process part and a check node process part. It is a figure which shows operation | movement of the bit node process part and check node process part which are shown in FIG.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 3 is a diagram illustrating an example of a configuration of a communication system. The communication system illustrated in FIG. 3 includes a transmission device 10 and a reception device 20. The transmission device 10 encodes and modulates transmission data to generate a transmission signal, and outputs the transmission signal. The transmission signal is received by the receiving device 20 via the wired or wireless communication path 15. The receiving device 20 demodulates and decodes the received data to generate decoded data.

  The transmission apparatus 10 includes an LDPC encoding unit 11 and a modulation unit 12. The LDPC encoding unit 11 generates encoded data including information bits and redundant bits by performing LDPC encoding on the transmission data. When the code word in the encoded data is Tx and the LDPC check matrix is H, the code word Tx is generated so that H × Tx = 0. The modulation unit 12 executes mapping processing, modulation processing, and D / A conversion processing. In the mapping process, carrier modulation is performed by assigning encoded data supplied from the LDPC encoding unit 11 to symbol points (signal points) such as 64QAM (Quadrature Amplitude Modulation). In the modulation process, a modulated signal is generated by performing OFDM (Orthogonal Frequency Division Multiplexing) modulation or the like on the carrier-modulated data by the mapping process. In the D / A conversion process, the modulation signal is converted from digital to analog to generate a transmission signal.

  The receiving device 20 includes a demodulator 21 and an LDPC decoder 22. The demodulator 21 performs A / D conversion processing, demodulation processing, and demapping processing. The A / D conversion unit converts the reception signal received from the transmission device 10 via the communication path 15 from analog to digital, and generates a digital reception signal. In the demodulation process, a demodulation process corresponding to the modulation used on the transmission side is applied to the digital reception signal to generate a demodulated reception signal. In the demapping process, among the symbol points in the modulation scheme used on the transmission side, a symbol point close to the reception signal point is detected, the probability that the value of the reception signal is 0 or 1 is softly determined, and the soft determination result is obtained. Calculate and output LLR. The LDPC decoding unit 22 performs an LDPC decoding process based on the calculated LLR. At this time, error correction is performed so that the decoded code word Rx becomes H × Rx = 0. As a result, a received signal after error correction is obtained.

  FIG. 4 is a diagram illustrating an example of the configuration of the LDPC decoding unit 22. The LDPC decoding unit 22 includes a control unit 31, an LLR RAM 32, a bit node processing unit 33, a check node processing unit 34, and a parity check unit 35. The LLR RAM 32 is a memory for storing the calculated LLR. The check node processing unit 34 updates the probability message α using the probability message β. The bit node processing unit 33 updates the probability message β using the prior probability λ and the probability message α, which are LLRs stored in the LLR RAM 32, and generates decoded decoded data c. The parity check unit 35 determines whether or not the product of the check matrix H and the decoded decoded data c (strictly, the product of the transposed matrix of H and c) becomes 0 by the parity check after the probability message is updated. judge. The control unit 31 controls the overall operation of the LDPC decoding unit 22. If the result of the parity check is 0, the control unit 31 outputs c as a decoding result. If the result of the parity check is not 0, the control unit 31 performs the update of the probability message α and the probability message β and the subsequent parity check again, so that the bit node processing unit 33, the check node processing unit 34, and The parity check unit 35 is controlled.

  In check node processing, specifically,

の計算式により、確率メッセージαを更新する。ここでＡ（ｍ）は、検査行列の行ｍにおいて要素値が“１”である列の集合である。Ａ（ｍ）＼ｎは、Ａ（ｍ）から列ｎを除いた集合を表わす。即ち、α_ｍｎを計算するときにはβ_ｍｎを使わず、残りの集合Ａ（ｍ）＼ｎのβを用いることになる。上記のチェックノード計算式は、符号計算部分（関数ｓｇｎの部分）と絶対値計算部分（関数ｍｉｎの部分）とからなる。

The probability message α is updated by the following formula. Here, A (m) is a set of columns whose element value is “1” in row m of the parity check matrix. A (m) \ n represents a set obtained by removing column n from A (m). That is, when calculating α _mn , β _mn is not used, and β of the remaining set A (m) \ n is used. The above check node calculation formula includes a code calculation part (function sgn part) and an absolute value calculation part (function min part).

  In bit node processing, specifically,

により、βが更新される。ここでＢ（ｎ）は検査行列の列ｎにおいて要素値が“１”である行の集合である。Ｂ（ｎ）＼ｍはＢ（ｎ）から行ｍを除いた集合を表わす。また事後確率計算処理は、

Accordingly, β is updated. Here, B (n) is a set of rows whose element value is “1” in column n of the parity check matrix. B (n) \ m represents a set obtained by removing row m from B (n). The posterior probability calculation process is

となる。これは事前確率λ_ｎ（受信信号から計算したＬＬＲ）に対して、αを加算することにより、事前確率よりも信頼度を高めた事後確率Ｌ_ｎを求めることを意味している。事後確率Ｌ_ｎは、一連の観測受信信号を受信したという条件及びパリティ検査の拘束条件の下で、送信信号が０又は１である確率を示す値である。この事後確率Ｌ_ｎが０以上か或いは０より小さいかを判定することにより、復号データｃのｎ番目のビットの値ｃ_ｎが求められる。具体的には、Ｌ_ｎが０以上であればｃ_ｎ＝０となり、Ｌ_ｎが０より小さければｃ_ｎ＝１となる。

It becomes. This means that by adding α to the prior probability λ _n (LLR calculated from the received signal), the posterior probability L _n with higher reliability than the prior probability is obtained. The posterior probability L _n is a value indicating the probability that the transmission signal is 0 or 1 under the condition that a series of observation reception signals are received and the parity check constraint condition. By determining whether the posterior probability L _n is _equal to or greater than 0 or smaller than 0, the value cn of the _nth bit of the decoded data c is obtained. Specifically, if L _n is 0 or more, c _n = 0, and if L _n is smaller than 0, c _n = 1.

  FIG. 5 is a diagram illustrating a configuration of a cyclic parity check matrix. The parity check matrix H is an N × n unit matrix or its cyclic matrix as a block (partial matrix), and is a J row block × K column block cyclic parity check matrix. Assume that the LDPC decoding unit 22 shown in FIG. 4 decodes a cyclic LDPC code using a cyclic check matrix as shown in FIG. In this case, as illustrated in FIG. 4, the bit node processing unit 33 includes n bit node processing circuits having the same structure. The check node processing unit 34 includes n × J (that is, a number equal to the number of rows of the check matrix H) check node processing circuits having the same structure.

  Specifically, the bit node processing unit 33 performs the bit node processing as shown in the above-described equation (2) for each column block of the check matrix, and based on the probability message α in one column block, the 1 Update all probability messages β in the column block. The one-column block includes n columns of the check matrix as shown in FIG. As shown in FIG. 4, the bit node processing unit 33 has an n-parallel configuration, and may execute bit node processing in parallel for all the columns in one column block.

FIG. 6 is a diagram illustrating an input / output relationship between the bit node processing unit 33 and the check node processing unit 34. In FIG. 6, the same components as those of FIG. 4 are referred to by the same numerals, and a description thereof will be omitted. FIG. 6 shows an example in which the cyclic parity check matrix shown in FIG. 1 where n is 3, J is 2, and K is 3 is used. In this case, the bit node processing unit 33 firstly stores the probability messages α _1,1 , α _2,1 , α _3,1 , α _4,1 , α _5,1 , α _{6,1 in} the first column block CB1. Update all probability messages β _1,1 , β _2,1 , β _3,1 , β _4,1 , β _5,1 , β _6,1 . FIG. 6A shows input / output of the bit node processing unit 33 and the check node processing unit 34 at this time. As shown in FIG. 6A, α _1,1 , α _2,1 , α ₃ from the first to sixth check node processing circuits 34-1 to 34-6 included in the check node processing unit 34, respectively. _{, 1} , α _4,1 , α _5,1 , α _6,1 are output in parallel. Among these, α _1,1 and α _{5,1 in} the first column of the check matrix H shown in FIG. 1 are supplied to the first bit node processing circuit 33-1 of the bit node processing unit 33. Α _2,1 and α _{6,1 in} the second column are supplied to the second bit node processing circuit 33-2 of the bit node processing unit 33. The third column α _3,1 , α _4,1 is supplied to the third bit node processing circuit 33-3 of the bit node processing unit 33. As a result, as shown in FIG. 6B, the first to third bit node processing circuits 33-1 to 33-3 of the bit node processing unit 33 receive β _1,1 and β _5,1 , β _2,1 and β _6,1 , β _3,1 and β _4,1 are output. These probability messages β are supplied to the corresponding check node processing circuit of the check node processing unit 34. Here, the output of the bit node processing unit 33 is directly connected to the input of the check node processing unit 34 without going through a memory.

In the same manner, based on the probability messages α _1,2 , α _2,2 , α _3,2 , α _4,2 , α _5,2 , α _6,2 in the second column block CB ₂ , Update all probability messages β _1,2 , β _2,2 , β _3,2 , β _4,2 , β _5,2 , β _6,2 . Finally, based on the probability messages α _1,3 , α _2,3 , α _3,3 , α _4,3 , α _5,3 , α _6,3 in the third column block CB3, The probability messages β _1,3 , β _2,3 , β _3,3 , β _4,3 , β _5,3 , β _6,3 are updated.

  FIG. 7 is a diagram illustrating operations of the bit node processing unit 33 and the check node processing unit 34 illustrated in FIG. 6. In FIG. 7, (a) through (c) show the inputs and internal operations of the first through third bit node processing circuits 33-1 through 33-3, respectively. (D) to (i) show the inputs and internal operations of the first to sixth check node processing circuits 34-1 to 34-6, respectively. For example, in the operation cycle T1, the probability message α corresponding to the first to third bit node processing circuits is input. This state is the state shown in FIG. Further, for example, in the operation cycle T2, the probability message β corresponding to the first to sixth check node processing circuits is input. This state is the state shown in FIG. The probability message α is input to the bit node processing circuit in three steps corresponding to the three column blocks. After one operation cycle, the calculation of the bit node processing is executed inside the bit node processing circuit as shown as Bnode in FIG. Further, the updated probability message β is output from the bit node processing circuit with a delay of one operation cycle.

The check node processing unit 34 calculates the check node processing for each row of the parity check matrix as shown in the above equation (1) every time one probability message β in the row is updated. This is performed step by step based on the probability message β. As can be seen from the above equation (1), the check node calculation formula is composed of a sign calculation part (function sgn part) and an absolute value calculation part (function min part). The content of the code calculation part is the sum of the values of the codes of all the probability messages β in one line excluding β _mn (a value obtained by adding up all) when α _mn is calculated. The total square value is equal to the integrated value of the infinite product value and beta _mn of code of the code of all probabilities message beta in a row which also contains beta _mn. The total value of the codes of all the probability messages β in one row can be realized by stepwise calculation if the sequentially updated probability messages β are integrated one by one with respect to the previous integration result. The content of the absolute value calculation part is the minimum value of all the probability messages β in one line except β _mn when α _mn is calculated. This value is either the first minimum value (the smallest value) or the second minimum value (the second smallest value) of all probability messages β in one row including β _mn , and β _mn is the first value. When it is the minimum value, it is the second minimum value, and when β _mn is not the first minimum value, it is the first minimum value. The minimum value and the second minimum value of all the probability messages β in one line are compared with the minimum value and the second minimum value obtained up to the previous time by sequentially comparing the probability messages β that are sequentially updated. It can ask for. In this way, the calculation of the check node processing of each row as shown in the above formula (1) is performed based on the updated probability message β every time one probability message β in the row is updated. Can be carried out step by step. Therefore, there is no need for a memory for storing the probability message β. Since the calculation of the probability message α in the check node processing is based on the selection of the minimum value of the probability message β, if the minimum value of the probability message β is held, the probability message α can be sequentially calculated based on that. Therefore, there is no need for a memory for storing the probability message α.

As shown in FIG. 4, the check node processing unit 34 has an n × J parallel configuration, and the check node processing unit 34 may execute check node processing in parallel for all rows of the check matrix. In the example illustrated in FIG. 7, in the operation cycle T2, the first to sixth check node processing circuits update the probability messages β _1,1 , β _2,1 , β ₃ updated for the first column block CB1. _{, 1} , β _4,1 , β _5,1 , β _6,1 are received. One check cycle later than this, check node processing calculation is executed inside the check node processing circuit, as indicated by Cnode in FIG. The calculation of the check node process is sequentially executed step by step based on the updated probability messages β of the first column block to the third column block sequentially supplied in the operation cycle T2 and the subsequent operation cycles. .

In the above check node processing, when the probability message β is updated and supplied for all the column blocks, the update processing of the probability message α is substantially completed. The check node processing circuits 34-1 to 34-6 corresponding to each row of the check node processing unit 34 update the probability message α after updating all the probability messages β in the corresponding row. Output sequentially. For example, in the case of the check node processing circuit 34-1, the updated probability messages α _1,1 , α _1,2 , α _1,3 are sequentially output.

  FIG. 8 is a flowchart showing the flow of the decoding process of the LDPC decoding unit 22 of FIG. The flow of this decoding process may be controlled by the control unit 31 in FIG.

  In step S1, a variable N indicating a column block is set to an initial value 1. In step S 2, all probability messages α of the Nth column block are output from the check node processing unit 34. In step S3, the bit node processing unit 33 executes bit node processing of the Nth column block, and updates all probability messages β of the Nth column block. At this time, a part of the check node processing is executed by the check node processing unit 34 based on the updated probability message β. In step S4, it is determined whether or not the variable N is equal to the total column block number K. If they are not equal, N is incremented by 1 in step S5, and the processes in and after step S2 are repeated.

  FIG. 9 is a diagram schematically showing how the bit node processing is repeated for each column block. First, bit node processing is executed for the first column block CB1. Thereafter, as indicated by an arrow, the bit node processing is repeated for each column block from the second column block CB2 to the Kth column block CBK.

  Returning to FIG. 8, if it is determined in step S4 that the variable N is equal to the total column block number K, the process proceeds to step S6. In step S6, the update of all probability messages α is completed in the check node process. In step S7, it is determined whether or not a decoding completion condition in which the product of the check matrix and the decoded data is 0 is satisfied. If the decryption completion condition is not satisfied, the process returns to step S1 and the subsequent processes are repeated. When the decoding completion condition is satisfied, the LDPC decoding process for the data to be decoded is completed.

  FIG. 10 is a diagram illustrating an example of the configuration of one check node processing circuit of the check node processing unit 34. The check node processing unit 34 includes n × J check node processing circuits shown in FIG. The check node processing circuit illustrated in FIG. 10 includes an absolute value calculation unit 41, an XOR unit 42, a comparison determination unit 43, flip-flops 44 to 51, and an output control unit 52. When one updated probability message β is supplied, the absolute value calculation unit 41 calculates and outputs the absolute value of the received probability message β. The most significant bit (sign bit) of the updated one probability message β is supplied to the XOR unit 42 and the flip-flop 44.

  The comparison determination unit 43 compares the absolute value of the updated one probability message β with the stored values of the flip-flops 46 and 47 (first register). The flip-flop 46 stores the first minimum value, and the flip-flop 47 stores the second minimum value. The comparison determination unit 43 stores the smallest value among the three compared values in the flip-flop 46 and stores the second smallest value in the flip-flop 47. In this way, each time one updated probability message β is supplied, the first minimum value or the second minimum value is updated as appropriate. After all the updated probability messages β of the target row are supplied, the first minimum value of the probability messages β of the target row is stored in the flip-flop 46, and the second minimum value is stored in the flip-flop 47. Will be.

As described above, the content of the absolute value calculation part of the check node calculation formula is the minimum value of all probability messages β in one line excluding β _mn when α _mn is calculated. This value is either the first minimum value or the second minimum value of all probability messages β in one line including β _mn , and is the second minimum value when β _mn is the first minimum value. _Yes , if β _mn is not the first minimum value, it is the first minimum value. Therefore, information indicating what number β is the first minimum value in the target row is recorded, and the first minimum value or the second minimum value supplied from the flip-flops 46 and 47 by the output control unit 52 is recorded. If the value is appropriately selected based on the information, the absolute value calculation part can be calculated.

  The XOR unit 42 performs an exclusive OR of the sign of one updated probability message β and the stored value of the flip-flop 45 (second register). The exclusive OR referred to here is an accumulation operation of sign bits, where 0 is positive and 1 is negative. If the product of positive and positive or the product of negative and negative, the output is positive, and positive and negative. The output is negative if the product of or the product of negative and positive. After all the updated probability messages β of the target row are supplied, the sign value of all the probability messages β of the target row is stored in the flip-flop 45. The stored value of the flip-flop 45 is supplied to the output control unit 52 via the flip-flop 49.

  The flip-flop 44 includes a plurality of flip-flops, and the codes of all the updated probability messages β in the target row are individually stored in the respective flip-flops. Since the sign is 1 bit, the number of necessary flip-flops 44 is not so large. The stored value of the flip-flop 44 is supplied to the output control unit 52 via the flip-flop 48.

As described above, the content of the code calculation part of the check node calculation formula is that when α _mn is calculated, the total value of the codes of all probability messages β in one line excluding β _mn (the value obtained by adding up all) It is. The total square value is equal to the integrated value of the infinite product value and beta _mn of code of the code of all probabilities message beta in a row which also contains beta _mn. Therefore, the output control unit 52 obtains the total value of the signs of all β supplied from the flip-flop 45 and the integrated value of the sign of the _target β _mn supplied from the flip-flop 44, thereby Arithmetic can be performed.

  In this way, after all the updated probability messages β in the target row are supplied, the output control unit 52 sequentially outputs the updated α to perform bit node processing, for example, as shown in FIG. Can be provided. When outputting the updated α, the check node processing circuit shown in FIG. 10 provided in parallel with n × J outputs α for all n × J rows in one column block of the parity check matrix. As a result, n × J parallel bit node processes can be realized.

  FIG. 11 is a diagram illustrating an example of the configuration of one bit node processing circuit of the bit node processing unit 33. The bit node processing unit 33 is provided with n bit node processing circuits shown in FIG. 11 in parallel. The bit node processing circuit shown in FIG. 11 includes a bit node calculation unit 61 and a hard decision unit 62. FIG. 11 shows an example in which there are three α and β in each row. However, the present invention is not limited to this example, and any number of α and β may be used in each row. Good.

  Based on the LLR calculated from the received signal and all α in the column, the bit node calculation unit 61 calculates the above-described equation (2) and updates all β in the column. (3) is calculated to generate decoded data. In FIG. 11, this decoded data is shown as SUM. The hard decision unit 62 generates hard decision data based on the decoded data SUM having a soft decision value. Specifically, if SUM is 0 or more, the hard decision value is 0, and if SUM is smaller than 0, the hard decision value is 1.

  FIG. 12 is a diagram illustrating an example of a parity check matrix adapted to application to an actual communication system using an LDPC code. The parity check matrix H shown in FIG. 12 is a cyclic parity check matrix of 3 row blocks × 58 column blocks having an 83 × 83 unit matrix or a cyclic matrix thereof as a block (partial matrix).

  FIG. 13 is a diagram illustrating an example of a configuration of an LDPC decoding unit corresponding to the parity check matrix of FIG. In FIG. 13, the same components as those of FIG. 4 are referred to by the same numerals, and a description thereof will be omitted. In FIG. 13, the control unit 31 and the parity check unit 35 shown in FIG. 4 are not shown.

  The LDPC decoding unit 22 shown in FIG. 13 decodes a cyclic LDPC code using a cyclic check matrix as shown in FIG. In this case, as shown in FIG. 13, the bit node processing unit 33 includes 83 bit node processing circuits having the same structure. The check node processing unit 34 includes 249 (= 83 × 3) check node processing circuits having the same structure.

FIG. 14 is a diagram illustrating an example of the operation of the LDPC decoding unit illustrated in FIG. 14A shows an α output from the check node processing unit 34 (α input to the bit node processing unit 33). (B) shows β output from the bit node processing unit 33 based on α input (β input to the check node processing unit 34). (C) shows stepwise execution of check node processing in the check node processing unit 34. As shown in (a), α _{1 to} α ₅₈ for 58 column blocks are sequentially output from the check node processing unit 34. Using these α _{1 to} α ₅₈ as inputs, the bit node processing unit 33 sequentially updates β, and sequentially outputs β _{1 to} β ₅₈ as shown in FIG. The stepwise processes C1 to C58 of the check node process shown in (c) compare the latest β of sequentially supplied β _{1 to} β ₅₈ with the minimum value up to the previous β, The minimum value is updated. As a result, the first and second minimum values are determined when the check node processing C58 finishes comparing the last β ₅₈ with the minimum value up to the previous β. This completes one iteration. When the hard-decision decoded data does not satisfy the parity check decoding completion condition by the check matrix, as shown in (a), α _{1 to} α ₅₈ for 58 column blocks are sequentially output from the check node processing unit 34 again. Then, bit node processing and check node processing are executed.

  FIG. 15 is a diagram illustrating another example of the configuration of one check node processing circuit of the check node processing unit. In FIG. 15, the same components as those of FIG. 10 are referred to by the same numerals, and a description thereof will be omitted. In the check node processing circuit shown in FIG. 15, the comparison determination unit 43 and the output control unit 52 of the check node processing circuit of FIG. 10 are replaced with a comparison determination unit 43A and an output control unit 52A, respectively. Further, the flip-flops 47 and 51 for the second minimum value are deleted. In the check node processing circuit shown in FIG. 15, the code calculation part of the check node process has the same configuration as that of the check node processing circuit shown in FIG. 10, but the configuration of the absolute value calculation part is simplified.

As described above, the absolute value calculation part of the check node processing of the Normalized Min-sum algorithm obtains the minimum value of all probability messages β in one line excluding β _mn when calculating α _mn . At this time, in order to cope with the case where β _mn is the minimum value, the check node processing circuit shown in FIG. 10 obtains the second minimum value. However, based on the recognition that the first minimum value and the second minimum value are not so different, even if β _mn is the minimum value and the second minimum value should be selected originally, It is conceivable to select and use the first minimum value as the approximate value. When only the first minimum value is used in this way, only the first minimum value comparison / determination unit and flip-flop are required as shown in FIG. 15. Compared to the configuration shown in FIG. The circuit scale can be reduced.

  In the configuration shown in FIG. 15, the comparison determination unit 43 </ b> A compares the updated absolute value of one probability message β with the stored value of the flip-flop 46. The flip-flop 46 stores the first minimum value. The comparison determination unit 43A stores the smaller of the two compared values in the flip-flop 46. In this way, each time one updated probability message β is supplied, the first minimum value is updated as appropriate. After all the updated probability messages β of the target row are supplied, the first minimum value of the probability messages β of the target row is stored in the flip-flop 46. The output control unit 52A may use the first minimum value supplied from the flip-flop 46 via the flip-flop 50 as the operation value of the absolute value calculation part of the check node process.

  Below, the modification of the structure of a LDPC decoding part is demonstrated. In the LDPC decoding unit 22 shown in FIG. 4, the bit node processing unit 33 includes n bit node processing circuits, and the check node processing unit 34 checks n × J (that is, a number equal to the number of rows of the check matrix H). Includes node processing circuitry. In this configuration, for example, in the case of the LDPC decoding unit 22 shown in FIG. 13, 249 (= 83 × 3) check node processing circuits having the same structure are provided, and the circuit of the check node processing unit 34 is provided. The scale will increase. Depending on the application field, it may be preferable to reduce the circuit scale of the processing circuit even if some memory for storing the probability message is required. For example, when an LDPC decoding unit or other circuit unit of a receiving device is realized using an FPGA (Field Programmable Gate Array), the number of gates that can be used to realize logical processing may be limited. Therefore, a modified example in which the circuit scale of the check node processing unit 34 is reduced is desired.

  FIG. 16 is a diagram illustrating a modification of the configuration of the LDPC decoding unit. In FIG. 16, the same components as those of FIG. 4 are referred to by the same numerals, and a description thereof will be omitted. 16 includes a control unit 31, an LLR RAM 32, a bit node processing unit 33, a check node processing unit 34, a parity check unit 35, buffers 71 and 72, and selectors (SEL) 73 and 74. . In the LDPC decoding unit 22A shown in FIG. 16, buffers 71 and 72 and selectors 73 and 74 are added to the LDPC decoding unit 22 shown in FIG. 4, and the number of parallel processes of the check node processing unit 34 is n × J. To n × J / p. Here, p is an integer of 2 or more which is a divisor of n × J.

  It is assumed that the LDPC decoding unit 22A illustrated in FIG. 16 decodes a cyclic LDPC code using a cyclic check matrix as illustrated in FIG. In this case, as shown in FIG. 16, the bit node processing unit 33 includes n bit node processing circuits having the same structure. The check node processing unit 34 includes n × J / p (that is, a number equal to 1 / p of the number of rows of the check matrix H) check node processing circuits having the same structure. As will be described below, the check node processing unit 34 performs parallel check node processing on a plurality of M (= n × J / p) rows of the cyclic check matrix. Further, the check node processing unit 34 sequentially executes this parallel check node processing on sequentially different M rows, thereby performing check node processing on all rows (n × J rows) of the cyclic check matrix. Execute.

  FIG. 17 is a diagram illustrating an input / output relationship between the bit node processing unit 33 and the check node processing unit 34. In FIG. 17, the same components as those of FIG. 16 are referred to by the same numerals, and a description thereof will be omitted. FIG. 17 shows an example in which the cyclic parity check matrix shown in FIG. 1 where n is 3, J is 2, and K is 3 is used. The check node processing unit 34 includes n × J / 2 check node processing circuits 34-1 to 34-3 having the same structure.

First, the bit node processing unit 33 is based on the probability messages α _1,1 , α _2,1 , α _3,1 , α _4,1 , α _5,1 , α _6,1 in the first column block CB1. The probability messages β _1,1 , β _2,1 , β _3,1 , β _4,1 , β _5,1 , β _6,1 are updated. FIG. 17A shows input / output of the bit node processing unit 33 and the check node processing unit 34 at this time. As shown in FIG. 17A, α _1,1 , α _2,1 , α from the first to third check node processing circuits 34-1 to 34-3 included in the check node processing unit 34, respectively. _{3 and 1} are output in parallel, and then α _5,1 , α _6,1 and α _4,1 are output in parallel. When α _1,1 , α _2,1 , α _3,1 are output from the check node processing unit 34, they are temporarily stored in the buffer 72 via the selector 74, and then α _5,1 , α _{6 , 1} , α _{4 , 1} are supplied to the bit node processing unit 33 at the same timing. When α _5,1 , α _6,1 , α _4,1 are output from the check node processing unit 34, they are immediately supplied to the bit node processing unit 33 via the selector 74 without passing through the buffer 72. Specifically, α _1,1 and α _{5,1 in} the first column of the parity check matrix H shown in FIG. 1 are supplied to the first bit node processing circuit 33-1 of the bit node processing unit 33. Α _2,1 and α _{6,1 in} the second column are supplied to the second bit node processing circuit 33-2 of the bit node processing unit 33. The third column α _3,1 , α _4,1 is supplied to the third bit node processing circuit 33-3 of the bit node processing unit 33.

As a result, as shown in FIG. 17B, the first to third bit node processing circuits 33-1 to 33-3 of the bit node processing unit 33 have β _1,1 and β _5,1 , β _2,1 and β _6,1 , β _3,1 and β _4,1 are output. These probability messages β are supplied to the corresponding check node processing circuit of the check node processing unit 34. Here, among the outputs of the bit node processing unit 33, each of β _1,1 , β _2,1 , and β _3,1 is immediately passed through the selector 73 without passing through the buffer 71. Are input to the check node processing circuits 34-1 to 34-3. Among the outputs of the bit node processing unit 33, β _5,1 , β _6,1 , and β _4,1 are each stored in the buffer 71, and then the first is passed through the selector 73 at an appropriate timing. To the third check node processing circuits 34-1 to 34-3.

In the same manner, based on the probability messages α _1,2 , α _2,2 , α _3,2 , α _4,2 , α _5,2 , α _6,2 in the second column block CB ₂ , Update all probability messages β _1,2 , β _2,2 , β _3,2 , β _4,2 , β _5,2 , β _6,2 . Finally, based on the probability messages α _1,3 , α _2,3 , α _3,3 , α _4,3 , α _5,3 , α _6,3 in the third column block CB3, The probability messages β _1,3 , β _2,3 , β _3,3 , β _4,3 , β _5,3 , β _6,3 are updated.

  FIG. 18 is a diagram illustrating operations of the bit node processing unit 33 and the check node processing unit 34 illustrated in FIG. In FIG. 18, (a) to (c) show the inputs and internal operations of the first to third bit node processing circuits 33-1 to 33-3, respectively. (E) through (g) show the inputs and internal operations of the first through third check node processing circuits 34-1 through 34-3, respectively. Further, (d) shows the buffer operation of the buffer 71 which is a bit node buffer, and (h) shows the buffer operation of the buffer 72 which is a check node buffer.

For example, in the operation cycle T1, the probability message α corresponding to the first to third bit node processing circuits is input. This state is the state shown in FIG. Further, for example, in the operation cycle T2, probability messages β (β _1,1 , β _2,1 , and β _3,1 ) corresponding to the first to third check node processing circuits are input. Further, for example, in the operation cycle T3, probability messages β (β _5,1 , β _6,1 , and β _4,1 ) corresponding to the first to third check node processing circuits are input. Note that β _5,1 , β _6,1 , and β _4,1 are stored in the bit node buffer shown in (d) for three cycles, and then supplied to the first to third check node processing circuits. . This state is the state shown in FIG. The probability message α is input to the bit node processing circuit in three steps corresponding to the three column blocks. After one operation cycle, the calculation of the bit node processing is executed inside the bit node processing circuit as shown as Bnode in FIG. By this bit node processing, the updated probability messages β (β _1,1 , β _5,1 , β _2,1 , β _6,1 , β _3,1 , β _4,1 ) are simultaneously transmitted from the bit node processing circuit. Is output. Here, a part of β (β _5,1 , β _6,1 , and β _4,1 ) is buffered by the bit node buffer shown in (d) and then output to the check node processing unit.

  The check node processing unit 34 calculates the check node processing for each row of the parity check matrix as shown in the above equation (1) every time one probability message β in the row is updated. This is performed step by step based on the probability message β. The method of stepwise calculation is as described above. Therefore, in the case of the example shown in FIG. 18, the first to third rows of the cyclic check matrix do not require a memory for storing the probability message β for the check node processing. However, for the fourth to sixth rows of the cyclic check matrix, a bit node buffer (buffer 71 shown in FIG. 16) is provided to store a probability message during the check node processing of the first to third rows. Used. By using the buffer function of the bit node buffer, the first to third row check node processing and the fourth to sixth row are performed using the first to third check node processing circuits 34-1 to 34-3. Check node processing can be executed in a time-sharing manner. That is, by executing parallel check node processing for a plurality of three rows of a cyclic check matrix and sequentially executing this parallel check node processing for three different rows, the cyclic check matrix Check node processing can be executed for all rows (6 rows). At this time, the bit node buffer functions to store a probability message β to be input to the parallel check node processing waiting to be executed when the parallel check node processing is sequentially executed.

  Since the calculation of the probability message α in the check node processing is based on the selection of the minimum value of the probability message β, if the minimum value of the probability message β is held, the probability message α can be sequentially calculated based on that. However, in the case of the example shown in FIG. 18, the check node processing in the fourth to sixth rows is executed after the check node processing in the first to third rows of the cyclic check matrix. Therefore, the check node buffer (buffer 74 shown in FIG. 16) is used to store the probability message α calculated by the check node processing in the first to third rows. That is, the check node buffer functions to store a probability message α waiting for input in the bit node processing unit that is output from the parallel check node processing that is sequentially executed. For the fourth to sixth rows of the cyclic check matrix, a memory for storing the probability message α is not necessary.

As shown in FIG. 16, the check node processing unit 34 has an n × J / p parallel configuration, and the check node processing unit 34 may execute check node processing with a degree of parallelism according to the value of p of the check matrix. In the example illustrated in FIG. 18, in the operation cycle T2, the first to third check node processing circuits are updated with the probability messages β _1,1 , β _2,1 , β ₃ updated for the first column block CB1. _{, 1} is received. One check cycle later than this, check node processing is calculated inside the check node processing circuit, as indicated by Cnode in FIG. The calculation of the check node process is sequentially executed step by step based on the updated probability messages β of the first column block to the third column block sequentially supplied in the operation cycle T2 and the subsequent operation cycles. . Furthermore, in the operation cycle T3, the first to third check node processing circuits receive the probability messages β _5,1 , β _6,1 , β _4,1 updated for the first column block CB1. One check cycle later than this, check node processing is calculated inside the check node processing circuit, as indicated by Cnode in FIG. The calculation of the check node processing is sequentially executed step by step based on the updated probability messages β of the first to third column blocks sequentially supplied in the operation cycle T3 and the subsequent operation cycles. .

In the above check node processing, when the probability message β is updated and supplied for all the column blocks, the update processing of the probability message α is substantially completed. The check node processing circuits 34-1 to 34-3 corresponding to the three rows of the cyclic check matrix update all the probability messages β in the corresponding rows, and then update the probability messages α in the rows. Are output sequentially. For example, the check node processing circuit 34-1 first outputs the updated probability messages α _1,1 , α _1,2 , α _1,3 sequentially to the first row of the cyclic check matrix. Further, the check node processing circuit 34-1 sequentially outputs updated probability messages α _5,1 , α _5,2 , α _5,3 to the fifth row of the cyclic check matrix.

  Note that one bit node processing circuit of the bit node processing unit 33 of the LDPC decoding unit 22A of FIG. 16 may have the circuit configuration shown in FIG. Also, one check node processing circuit of the check node processing unit 34 of the LDPC decoding unit 22A of FIG. 16 may have the circuit configuration shown in FIG. 10 or FIG. In the LDPC decoding unit 22A shown in FIG. 16, by using the buffers 71 and 72, the parallel number of check node processing circuits can be reduced to n × J / p, and the circuit scale of the logical operation part can be reduced. .

The present invention includes the following contents.
(Appendix 1)
A bit node that performs a bit node process in the decoding process of the cyclic LDPC code for each column block of the parity check matrix and updates all the probability messages β in the column block based on the probability message α in the column block A processing unit;
In the calculation of check node processing for each row of the check matrix, the calculation of check node processing for one row is changed to one probability message β that is updated every time one probability message β in the one row is updated. And a check node processing unit that sequentially outputs the updated probability messages α in the one row after all the probability messages β in the one row are updated. A decoding device.
(Appendix 2)
The bit node processing unit performs bit node processing in parallel on all columns in one column block, and the check node processing unit performs check node processing on all rows in parallel. The decoding device according to supplementary note 1, which is characterized.
(Appendix 3)
The decoding apparatus according to claim 1 or 2, wherein an output of the bit node processing unit is directly connected to an input of the check node processing unit without going through a memory.
(Appendix 4)
The check node processing unit
A first register;
A second register;
A comparator that compares the absolute value of the updated one probability message β with the stored value of the first register;
The decoding apparatus according to any one of appendices 1 to 3, further comprising an XOR circuit that performs an exclusive OR of the sign of the updated one probability message β and the stored value of the second register.
(Appendix 5)
The bit node processing unit updates the probability message β and generates the decoded data after the hard decision based on the log likelihood ratio input and the probability message α. The decoding device described.
(Appendix 6)
The bit node processing unit performs bit node processing on all columns in one column block in parallel, and the check node processing unit performs parallel check node processing on a plurality of M rows of the check matrix. The check node processing is executed for all the rows of the parity check matrix by sequentially executing the parallel check node processing for different M rows sequentially. Decoding device.
(Appendix 7)
A first buffer for storing a probability message β to be input to the parallel check node process waiting to be executed when the parallel check node process is sequentially executed;
The decoding according to claim 6, further comprising: a second buffer that is output from the parallel check node processing executed sequentially and stores a probability message α waiting for input in the bit node processing unit. apparatus.
(Appendix 8)
Performing bit node processing in the decoding process of the cyclic LDPC code for each column block of the parity check matrix, and updating all the probability messages β in the one-column block based on the probability message α in the one-column block;
In the calculation of check node processing for each row of the check matrix, the calculation of check node processing for one row is changed to one probability message β that is updated every time one probability message β in the one row is updated. And decoding each step of sequentially outputting the updated probability messages α in the one row after all the probability messages β in the one row are updated. Method.
(Appendix 9)
9. The decoding method according to appendix 8, wherein the bit node processing is executed in parallel for all columns in one column block, and the check node processing is executed in parallel for all rows.
(Appendix 10)
The decoding method according to appendix 8 or 9, wherein the bit node processing updates the probability message β and generates decoded data after the hard decision based on the log likelihood ratio input and the probability message α.
(Appendix 11)
A demodulator that converts an analog reception signal into a digital reception signal, demodulates the digital reception signal to generate a demodulated reception signal, calculates and outputs an LLR from the demodulated reception signal;
A decoding unit that performs LDPC decoding based on the LLR, and the decoding unit includes:
A bit node that performs a bit node process in the decoding process of the cyclic LDPC code for each column block of the parity check matrix and updates all the probability messages β in the column block based on the probability message α in the column block A processing unit;
In the calculation of check node processing for each row of the check matrix, the calculation of check node processing for one row is changed to one probability message β that is updated every time one probability message β in the one row is updated. And a check node processing unit that sequentially outputs the updated probability messages α in the one row after all the probability messages β in the one row are updated. A receiving device.

  As mentioned above, although this invention was demonstrated based on the Example, this invention is not limited to the said Example, A various deformation | transformation is possible within the range as described in a claim.

DESCRIPTION OF SYMBOLS 10 Transmission apparatus 15 Communication path 20 Reception apparatus 31 Control part 32 LLR RAM
33 bit node processing unit 34 check node processing unit 35 parity check unit

Claims (7)

A bit node that performs a bit node process in the decoding process of the cyclic LDPC code for each column block of the parity check matrix and updates all the probability messages β in the column block based on the probability message α in the column block A processing unit;
In the calculation of check node processing for each row of the check matrix, the calculation of check node processing for one row is changed to one probability message β that is updated every time one probability message β in the one row is updated. And a check node processing unit that sequentially outputs the updated probability messages α in the one row after all the probability messages β in the one row are updated. A decoding device.   The bit node processing unit performs bit node processing in parallel on all columns in one column block, and the check node processing unit performs check node processing on all rows in parallel. The decoding device according to claim 1, wherein:   3. The decoding apparatus according to claim 1, wherein an output of the bit node processing unit is directly connected to an input of the check node processing unit without going through a memory. The check node processing unit
A first register;
A second register;
A comparator that compares the absolute value of the updated one probability message β with the stored value of the first register;
4. The decoding device according to claim 1, further comprising: an XOR circuit that obtains an exclusive OR of the sign of the updated one probability message β and the stored value of the second register. 5. .   The bit node processing unit performs bit node processing on all columns in one column block in parallel, and the check node processing unit performs parallel check node processing on a plurality of M rows of the check matrix. The check node processing is executed for all rows of the parity check matrix by executing and executing the parallel check node processing sequentially on different M rows sequentially. Decoding device. A first buffer for storing a probability message β to be input to the parallel check node process waiting to be executed when the parallel check node process is sequentially executed;
6. The second buffer according to claim 5, further comprising: a second buffer that is output from the parallel check node processing executed sequentially and stores a probability message α waiting for input in the bit node processing unit. Decoding device. Performing bit node processing in the decoding process of the cyclic LDPC code for each column block of the parity check matrix, and updating all the probability messages β in the one-column block based on the probability message α in the one-column block;
In the calculation of check node processing for each row of the check matrix, the calculation of check node processing for one row is changed to one probability message β that is updated every time one probability message β in the one row is updated. And decoding each step of sequentially outputting the updated probability messages α in the one row after all the probability messages β in the one row are updated. Method.

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