TWI442712B - 使用多檢查節點演算法之錯誤更正解碼器 - Google Patents
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Description
本發明係關於信號處理,特別是錯誤更正編碼和解碼技術,如低密度奇偶校驗(LDPC)編碼和解碼。
本申請案主張2008年8月15日申請之代理檔案號碼08-0241之美國臨時申請案第61/089,297號之申請日期之權利,其該等教示以引用的方式全部併入本文中。
本申請案之主題係關於2008年5月1日申請之美國專利申請案第12/113,729號、2008年5月1日申請之美國專利申請案第12/113,755號、2008年11月26日申請之美國專利申請案第12/323,626號、2009年3月10日申請之美國專利申請案第12/401,116號、2008年12月12日申請之PCT專利申請案第PCT/US08/86523號及2008年12月12日申請之PCT專利申請案第PCT/US08/86537號,其該等教示以引用的方式全部併入本文中。
在解碼一碼字中,一低密度奇偶校驗(LDPC)解碼器可能遇到一或多個陷阱集,該等陷阱集阻礙該解碼器正確地解碼該碼字。陷阱集(其等表示在一LDPC碼的一Tanner圖中的子圖。)通常對該LDPC碼的錯誤基數特性有很強影響,因為一陷阱集可能強迫該解碼器收斂於一不正確結果。為了改良錯誤基數特性,一LDPC解碼器可利用不同技術以打破主導陷阱集(即通常對錯誤基數特性有最大影響的陷阱集)。這些主導陷阱集基於該解碼器的作業條件而變化多端,如解碼器字母、解碼器演算法、解碼器檢查節點單元更新、通道條件和信號條件。
在一實施例中,本發明是一種解碼一錯誤更正(EC)編碼碼字以恢復一正確碼字的方法。該方法選擇一縮放因數和一偏移值,以及從一上游處理器接收一原始組原始值。該原始組原始值對應於該EC編碼碼字,以及在該原始組中的每個原始值對應於該EC編碼碼字的一不同位元。基於該原始組原始值產生一第一組訊息,以及基於該縮放因數和該偏移值將該第一組訊息轉換為縮放和偏移的訊息。
在另一實施例中,本發明是一種實施上述方法的裝置。該裝置包括一用於解碼該EC編碼碼字以恢復一正確碼字的錯誤更正(EC)解碼器。該解碼器產生該第一組訊息並且包括(i)一或多個模組,其基於一縮放因數和一偏移值而調適以將該第一組訊息轉換為縮放和偏移的訊息及(ii)一控制器,其經調適以選擇該縮放因數和該偏移值。
本發明的其他態樣、特徵和優點從以下實施方式、該等所附請求項及其所附圖式將變得更加顯而易見,其中相同參考數字表示類似或相同元件。
此處參考「一(one)實施例」或「一(a)實施例」意為結合該實施例所述的一特定特徵、結構或特性可被包含在本發明的至少一實施例中。在本說明書中各處中該短語「在一實施例中」的出現並不一定全部參考同一實施例,單獨或替代性實施例並不一定相互排除其他實施例。這同樣適用於該術語「實施」。
經由改變由一LDPC解碼器所使用的該檢查節點演算法可改良該LDPC解碼器的錯誤基數特性。通常,由於使用一特定檢查節點演算法產生的陷阱集與由於使用其他檢查節點演算法產生的陷阱集是不同的。因此,例如,經由將該檢查節點演算法從一偏移最小和演算法改變到一縮放最小和演算法可獲得不同陷阱集。還可經由改變由一偏移最小和演算法使用的該偏移值或經由改變由一縮放最小和演算法使用的該縮放因數獲得不同陷阱集。
圖1顯示一奇偶校驗矩陣100之一實施,該奇偶校驗矩陣可被用於實施一規則、準循環(QC)LDPC碼。奇偶校驗矩陣100(通常稱為一H矩陣)包括40個循環行列式Bj,k
,該等循環行列式被配置成r=4列循環行列式(即分組列),和c=100行循環行列式(即分組行)中,其中j=1,...,r以及其中k=1,...,c。一循環行列式是一子矩陣,該子矩陣是一單位矩陣或經由循環移位一單位矩陣而獲得,以及一準循環LDPC碼是一LDPC碼,其中該等子矩陣全部是循環行列式。在H矩陣100中,每個循環行列式Bj,k
是一p×p子矩陣,該p×p子矩陣可經由循環移位一單個p×p單位矩陣而獲得。為了該討論的目的,假設p=72使得H矩陣100有p×r=72×4=288個總列和p×c=72×10=720個總行。因為每個循環行列式Bj,k
是一單位矩陣的置換,所以在一循環行列式中每行的漢明(hamming)權重(即,具有一值1的元素個數)和在一循環行列式中每列的漢明權重都是等於1。因此,H矩陣100的每列的總漢明權重wr
等於1×c=1×10=10,且H矩陣100的每行的總漢明權重wc
等於1×r=1×4=4。H矩陣100之該288個列之每個對應一第m檢查節點,其中m的範圍為0,...,287,且該720行之每個對應一第n可變節點(也稱為一位元節點),其中n的範圍為0,...,719。此外,每個檢查節點被連接到wr
=10個可變節點,如一列中的1s所示,以及每個可變節點被連接到wc
=4個檢查節點,如一行中的1s所示。因為H矩陣100的所有列具有相同的漢明權重wr
,且H矩陣100的所有行具有相同的漢明權重wc
,所以H矩陣100可被描述為一規則LDPC碼。
圖2顯示根據本發明之一實施例之一LDPC解碼器200的簡化方塊圖,該LDPC解碼器可被用於解碼使用一H矩陣(如圖1的H矩陣100)編碼的碼字。對於接收到的每個碼字,LDPC解碼器200(i)從一上游處理器接收720個軟值(例如,對數似然比(LLR))Ln (0)
,該處理器(例如)可實施射頻處理、類比至數位轉換、均等化、通道檢測(如Viterbi檢測)或適合產生軟輸出值的其他處理,以及(ii)將這些軟值Ln (0)
儲存在軟值記憶體202中。由該上游處理器實施的該處理可取決於實施LDPC解碼器200的特定應用。每個軟值Ln (0)
對應該碼字之一位元,以及使用一訊息傳遞演算法來迭代解碼每個碼字。對於該討論,假設每個軟值Ln (0)
有五個位元,其包含一硬決定位元和一四位元信心值。
一般而言,LDPC解碼器200使用一分組串列訊息傳遞方案解碼該720個軟值Ln (0)
(即訊息)。使用(i)288個檢查節點單元(CNU)210,其中每個CNU 210為H矩陣100的一列(即該第m個檢查節點)實施檢查節點更新,和(ii)72個五位元可變節點單元(VNU)204,其中每個VNU 204為H矩陣100的十個行(即該第n個可變節點)實施該可變節點更新,更新該等訊息。CNU 210(0),...,210(287)為H矩陣100之該288個列實施該等檢查節點(即列)更新,一次一個分組行,使得為該第一分組行(即循環行列式B1,1
、B2,1
、B3,1
和B4,1
)實施該等檢查節點更新,接著是該第二分組行(即循環行列式B1,2
、B2,2
、B3,2
和B4,2
)的該等檢查節點更新,接著是該第三分組行(即循環行列式B1,3
、B2,3
、B3,3
和B4,2
)的該等檢查節點更新等。VNU 204(0),...,204(71)接著為H矩陣100的該72個行實施該等可變節點(即行)更新,一次一個分組行,使得為該第一分組行(即循環行列式B1,1
、B2,1
、B3,1
和B4,1
)實施該等可變節點更新,接著是該第二分組行(即循環行列式B1,2
、B2,2
、B3,2
和B4,2
)的該等可變節點更新,接著是該第三分組行(即循環行列式B1,3
、B2,3
、B3,3
和B4,3
)的該等可變節點更新等。在實施全部檢查節點更新和可變節點更新之後,完成LDPC解碼器200的迭代(即,局部迭代)。
最初,該720個五位元軟值Ln (0)
被以每個時鐘週期72個軟值Ln (0)
的速率提供給四個多工器206(0),...,206(3),使得每個多工器206接收在該組中的所有72個軟值Ln (0)
。每個多工器206還從VNU 204(0),...,204(71)接收72個五位元可變節點訊息(此處稱為Q訊息),如以下進一步詳細討論它們之產生。在LDPC解碼器200的該第一迭代期間,多工器206(0),...,206(3)選擇該組72個五位元軟值Ln (0)
,它們接收該等軟值以分別輸出到72路循環移位器208(0),...,208(3)。沒有被選擇的該等原始Q訊息可能是為一先前考慮的碼字產生的Q訊息。在LDPC解碼器200的隨後迭代期間,多工器206(0),...,206(3)選擇該組72個五位元Q訊息,它們從VNU 204(0),...,204(71)接收該等訊息以分別輸出到72路循環移位器208(0),...,208(3)。對於以下討論,應明白,對Q訊息的任何參考在LDPC解碼器200的該第一迭代期間適用於軟值Ln (0)
。
循環移位器208(0),...,208(3)循環移位該組72個五位元Q訊息,它們基於例如從控制器214接收到的一循環移位信號而接收該等Q訊息。該循環移位信號對應於圖1的H矩陣100的該等循環行列式的循環移位因數。例如,在LDPC 200的一迭代的第一時鐘週期期間,循環移位器208(0),...,208(3)可分別基於圖1的H矩陣100的循環行列式B1,1、B2,1、B3,1和B4,1的該等移位因數而移位它們各自組的72個五位元Q訊息。在LDPC 200的一迭代的第二時鐘週期期間,循環移位器208(0),...,208(3)分別基於循環行列式B1,2、B2,2、B3,2和B4,2的該等移位因數而移位它們各自組的72個五位元Q訊息。循環移位器208(0),...,208(3)接著提供它們各自的72個循環移位五位元Q訊息給CNU 210(0),...,210(287),使得每個CNU 210接收該等Q訊息的一不同訊息。
每個CNU 210(i)以每個時鐘週期一個Q訊息的速率接收許多個等於H矩陣100的一列的該漢明權重wr
(例如10)的五位元Q訊息以及(ii)產生wr
個五位元分組節點訊息(此處稱為R訊息)。每個CNU 210被選擇性地配置成使用(i)一偏移最小和檢查節點演算法,(ii)一縮放最小和檢查節點演算法或(iii)一應用偏移和縮放兩者的最小和檢查節點演算法產生R訊息。每個R訊息可表示為如下方程式(1)、(2)和(3)所示:
其中(i)表示與用於LDPC解碼器200的第i次迭代的圖1的H矩陣100的第m個檢查節點(即列)和第n可變節點(即行)相對應的該R訊息,(ii)表示與用於第(i-1)次迭代的H矩陣100的第n可變節點和第m個檢查節點相對應的該R訊息,(iii)α表示一縮放因數,其範圍為0到1,(iv)β表示一偏移值,其範圍為0到15,以及(v)該函數sign表示在該個訊息的符號上實施乘法運算(即Π)。假設n'是在除了該第n個可變節點以外的連接到該第m個檢查節點的所有可變節點的該組N(m)/n中的一可變節點(即,)。對應於該第m個檢查節點(即列)的該CNU 210基於在先前第(i-1)次迭代期間從該組N(m)/n接收到的所有Q訊息產生訊息。因此,在圖2的該實施例中,基於N(m)/n=9個Q訊息(即wr
-1=10-1)產生每個R訊息。注意,對於該第一次迭代,從軟值記憶體202接收到的軟值Ln (0)
代替位於先前迭代的該等Q訊息被用在方程(2)和(3)中(即)。
由每個CNU 210使用的該特定演算法例如可由控制器214選擇。例如,為了實施一沒有縮放的偏移最小和檢查節點演算法,控制器214可選擇一α為1的縮放因數使得CNU 210不實施縮放,和一異於0的偏移值β。為了實施一沒有偏移的縮放最小和檢查節點演算法,控制器214可選擇一β為0的偏移值使得CNU 210不實施偏移,和一異於1的縮放因數α。為了實施一實施縮放和偏移兩者的最小和檢查節點演算法,控制器214可選擇一異於0的偏移值β和一異於1的縮放因數α。最初,控制器214選擇一預想偏移和縮放因數。控制器214接著可改變該偏移和縮放因數,例如從LDPC解碼器200的一迭代(即一局部迭代)到下個迭代、從該LDPC碼的一層到下一層、從一碼字到下個碼字以及從一整體迭代(以下進一步描述)到下個整體迭代。
圖3顯示根據本發明的一實施例的一CNU 300的簡化方塊圖,該檢查節點單元可被用於實施圖2的LDPC解碼器的每個CNU 210。一般地,CNU 300產生十個五位元R訊息,其中使用一組N(m)/n=9個Q訊息(如上所述排除一訊息)產生每個五位元R訊息。對於這些十個五位元R訊息的9個訊息,使用方程式(2)產生的該等Q訊息的最小大小是相同的。對於這些R訊息的一個訊息,該等Q訊息的最小大小將是該等Q訊息的第二最小大小,因為將從該計算排除該等Q訊息的最小大小,如上所述。除了實施方程式(2)十次,該十個五位元R訊息每個一次,CNU 300實施一值再利用技術,其中CNU 300(i)使用M1_M2查找器302決定具有最小和第二最小大小的該等Q訊息以及(ii)基於該最小和第二最小大小產生該十個五位元R訊息。
在該第一十個時鐘週期的每個期間,M1_M2查找器302接收一係2的補數格式的五位元Q訊息。可使用縮放和偏移邏輯模組310縮放及/或偏移該等五位元Q訊息。縮放及/或偏移可被施加在CNU 300中的各種位置。例如,可由縮放和偏移邏輯模組334或346施加縮放及/或偏移,以替代由縮放和偏移邏輯模組310實施的縮放及/或偏移。作為替代,可由縮放和偏移邏輯模組310、334和346之兩個或更多模組施加縮放及/或偏移。該等縮放因數(例如α1、α2、α3))及/或偏移值(例如β1、β2、β3)例如可由圖2的控制器214提供。當使用縮放和偏移邏輯模組310、334和346之兩個或更多模組時,該等縮放因數和偏移值從一縮放和偏移邏輯模組到下個模組可能是不同的。作為另一替代,縮放可被施加在一不同於偏移的位置。當由在不同位置中的不同模組實施縮放和偏移時,該等不同模組可被視為基於一縮放因數和一偏移值將訊息轉換為縮放和偏移訊息。例如,如果模組310實施縮放以及模組346實施偏移,則該等模組310和346可被視為將該等Q訊息轉換為縮放和偏移R訊息。
M1_M2查找器302使用2的補數對符號大小(2TSM)轉換器312將每個可能縮放及/或偏移Q訊息從2的補數格式轉換為一五位元符號大小值。該符號大小值的該符號位元326被提供給符號處理邏輯器328,該符號處理邏輯器(i)產生所有十個Q訊息的該等符號位元326的一積以及(ii)將該等符號位元326之每個乘以該積以為10個R訊息之每個產生一不同符號位元332。該五位元符號大小值Q[4:0]的該四位元大小|Q|[3:0]與分別儲存在部分狀態記憶體304的部分狀態暫存器330(0)和330(1)中的該四位元最小大小值M1和該四位元第二最小大小值M2一起被提供給多工器(MUX)320。此外,該四位元大小值|Q|[3:0]被提供給觸發器(FF)314,該觸發器將CNU 300的定時與LDPC解碼器200的該時鐘信號同步。
最小運算器316(0)比較該大小值|Q|與儲存在暫存器330(0)中的最小大小值M1。如果該大小值|Q|小於最小大小值M1,則該最小運算器316(0)確認控制信號318(0)(即設定318(0)等於1)。否則,該最小運算器316(0)撤銷確認控制信號318(0)(即設定318(0)等於0)。同樣,最小運算器316(1)比較該大小值|Q|與儲存在暫存器330(1)中的第二最小大小值M2。如果該大小值|Q|小於M2,那麼確認控制信號318(1)。否則,撤銷確認控制信號318(1)。注意,為了本發明的目的,最小大小值M1和第二最小大小值M2被認為是訊息。為了進一步理解MUX 320的該作業,考慮用於大小值|Q|的表I的邏輯表。
表I顯示,如果控制信號318(0)和318(1)都被撤銷確認(即|Q|大於等於M1和M2),那麼大小值|Q|被丟棄,以及先前儲存的最小和第二最小大小值M1和M2分別被儲存在M1暫存器330(0)和M2暫存器330(1)中。如果控制信號318(0)被撤銷確認且控制信號318(1)被確認(即|Q|大於等於M1且小於M2),那麼(i)最小大小值M1被儲存在M1暫存器330(0)中,(ii)大小值|Q|被儲存在M2暫存器330(1)中以及(iii)先前儲存的第二最小大小值M2被丟棄。如果控制信號318(0)和318(1)都被確認(即|Q|小於M1和M2),那麼(i)大小值|Q|被儲存在M1暫存器330(0)中,(ii)先前儲存的最小大小值M1被儲存在M2暫存器330(1)中以及(iii)第二最小大小值M2被丟棄。除了儲存大小值|Q|在M1暫存器330(0)中,M1_index暫存器330(2)被致能,對應於該新最小值M1的計數器值324(由計數器322產生)被儲存在M1_index暫存器330(2)中,以及先前儲存在M1_index暫存器330(2)中的該計數器值被丟棄。注意,控制信號318(0)將被確認並且控制信號318(1)將被撤銷確認是不可能的,因為這可能表示該大小值|Q|小於最小大小值M1但大於第二最小大小值M2。此外,在該第一時鐘週期之前,該最小和第二最小大小值M1和M2被初始化到適當大的值(例如,二進位1111)以及M1_index被初始化到0。
在考慮所有十個Q訊息之後,該最小大小值M1和第二最小大小值M2可由縮放和偏移邏輯模組334縮放及/或偏移。符號大小對2的補數(SMT2)轉換器338經由附加一正符號位元到四位元值M1'將可能縮放和偏移四位元最小大小值M1'轉換為一五位元正補數值並且將該五位元結果(+M1')儲存在最後狀態處理器306的暫存器336(0)中。SMT2轉換器338還經由附加一負符號位元到四位元值M1'將可能縮放及/或偏移四位元偏移最小大小值M1'轉換為一五位元負補數值並且將該五位元結果(-M1')儲存在暫存器336(1)中。此外,如果來自符號處理邏輯器328的符號位元332是一正符號位元(0),那麼SMT2轉換器338將可能縮放及/或偏移四位元第二最小大小值M2'轉換為一五位元正補數值(+M2')用於儲存在暫存器336(2)中。如果來自符號處理邏輯器328的符號位元332是一負符號位元(1),那麼SMT2轉換器338將可能縮放及/或偏移四位元第二最小大小值M2'轉換為一五位元負補數值(-M2')用於儲存在暫存器336(2)中。最後狀態處理器306的暫存器336(3)儲存來自M1_index暫存器330(2)的該計數器值M1_INDEX。
在下個十個時鐘週期之每個時鐘週期期間,R選擇器308的MUX 344基於(1)該正值(+M1')、(2)該負值(-M1')、(3)該正或負值(±M2')、(4)一來自比較運算器340的比較位元342及(5)儲存在符號處理邏輯器328中的相應符號位元326輸出一五位元R訊息。經由比較當前計數器值324與儲存在暫存器336(3)中的該M1_index值而產生每個比較位元342。當該兩個值相等時,比較位元342被確認,以及當該兩個值不相等時,比較位元342被撤銷確認。每個符號位元332可使用方程(3)被產生為,或作為替代,在使用一FIFO實施符號處理邏輯器328的情況下,經由將一儲存符號位元326(由於它是從該FIFO輸出)乘以儲存在符號處理邏輯器326中的所有符號位元326的該積。為了進一步理解如何從MUX 344輸出R訊息,考慮表II的邏輯表。
表II顯示,如果比較位元342和符號位元332都被撤銷確認,那麼儲存在暫存器336(0)中的該正值(+M1')將被輸出為該五位元R訊息。如果比較位元342被撤銷確認並且符號位元332被確認,那麼儲存在暫存器336(1)中的該負值(-M1')將被輸出為該五位元R訊息。如果比較位元342被確認並且符號位元332被撤銷確認,那麼該正值(+M2')將被儲存在暫存器336(2)中並且將被輸出為該五位元R訊息。如果比較位元342和符號位元332都被確認,那麼該負值(-M2')將被儲存在暫存器336(3)中並且將被輸出為該五位元R訊息。該等R訊息接著可由縮放和偏移邏輯器346縮放及/或偏移。
回到參考圖2,循環移位器212(0),...,212(3)從它們各自CNU 210接收幾組72個五位元R訊息並且根據圖1的H矩陣100的該等循環行列式B jk
的該等循環移位循環地移位該幾組72個五位元R訊息。基本上,循環移位器212(0),...,212(3)將循環移位器208(0),...,208(3)的循環移位反向。例如,如果循環移位器208(0),...,208(3)實施循環上移,那麼循環移位器212(0),...,212(3)可能實施循環下移。
循環移位器212(0),...,212(3)提供4×72個循環移位五位元R訊息給VNU 204(0),...,204(71),使得每個VNU 204接收該等R訊息的四個訊息,每個循環移位器212一個。每個VNU 204更新該四個五位元Q訊息的每個,它如方程式(4)中所示產生:
其中m'是在除了該第m個檢查節點以外的連接到該第n個檢查節點的所有檢查節點的該組M(n)/m中的一檢查節點(即,m'M(n)m)。該第n個可變節點基於(i)在先前第(i-1)次迭代期間從該組M(n)/m接收到的所有Q訊息和(ii)一從軟值記憶體202接收到的原始軟值Ln (0)
產生訊息,該軟值記憶體對應該第n個可變節點。每個VNU 204(其可使用加法器電路實施)輸出它產生的該四個更新五位元Q訊息,使得該四個訊息的一不同訊息被提供給一相應的不同MUX 206。
除了輸出四個更新五位元Q訊息,每個VNU 204輸出(i)一七位元外部LLR值,(ii)一硬決定輸出位元及(iii)一八位元P值。每個七位元外部LLR值可被表示為如方程式(5)中所示:
其中m是在連接到該第n個可變節點的所有檢查節點的該組M(n)中的一檢查節點(即,)。八位元P值可使用方程式(6)產生,如下:
每個硬決定位元可基於以下方程式(7)和(8)產生:
經由從方程式(5)增加該外部值到從軟值記憶體202接收到的該原始軟值Ln (0)
為每個可變節點決定Pn
,該軟值記憶體對應該第n個可變節點。如果Pn
大於或等於0,那麼該硬決定位元等於0,如方程式(7)中所示。如果Pn
小於0,那麼該硬決定位元等於1,如方程式(8)中所示。
接著例如由控制器214使用該硬決定值實施一奇偶校驗以決定LDPC解碼器200是否已經收斂於一有效碼字。特別是,在十個時鐘週期期間從VNU 204(0),...,204(71)輸出的720個硬決定位元形成的一720-元素的向量被乘以圖1的H矩陣100的該轉置矩陣HT
以產生一288-位元向量,其中該288-位元向量的每個位元對應於H矩陣100的該288個檢查節點(即列)其中之一。如果最終形成的該288-位元向量的每個元素等於0(即),那麼LDPC解碼器200已經收斂於一有效碼字。另一方面,如果最終形成的該288-位元向量的一或多個元素等於1(即),那麼LDPC解碼器200還沒有收斂於一有效碼字。具有一值1的該288-位元向量的每個元素被視為一不滿意的檢查節點。如果並且當LDPC解碼器200收斂於一有效碼字時,例如可由控制器214實施一循環冗餘檢查(CRC)。如果該CRC是成功的,那麼LDPC解碼器200已經收斂於一有效正確碼字。如果該CRC是不成功的,那麼LDPC解碼器200已經收斂於一有效但不正確的碼字。
如果LDPC解碼器200沒有收斂於一有效碼字或收斂於一有效但不正確的碼字,那麼需要進一步行動以正確恢復該正確碼字。例如,可實施LDPC解碼器200的隨後局部迭代以收斂於一有效正確碼字。作為另一實例,可實施一整體迭代,據此(i)該等外部LLR值被回饋到該上游處理器,(ii)該檢測器產生一組新的720個五位元軟值Ln (0)
及(iii)LDPC解碼器200嘗試從該組新的720個五位元軟值Ln (0)
恢復該正確碼字。如果LDPC解碼器200在預定次數的局部及/或整體迭代內沒有收斂於一有效正確碼字,那麼該接收器及/或LDPC解碼器可能採取進一步行動以恢復一有效碼字,如實施專用於打破陷阱集的其他方法。在一些情況下,LDPC解碼器200可能不能恢復該正確碼字。作為另一實例,LDPC解碼器200駐留在其中的該接收器可能請求該資料的重新發送。
對於隨後每次嘗試解碼該碼字(例如,隨後每次局部迭代、隨後整體迭代或重新發送),控制器214可選擇一或多個不同縮放因數α、一或多個不同偏移值β或同時一或多個不同縮放因數α和一或多個不同偏移值β。可使用任何合適方法選擇該等縮放因數α和偏移值β。例如,該等縮放因數α和偏移值β可基於在該奇偶校驗期間識別的不滿意的檢查節點數選擇。當不滿意的檢查節點數相當少時,相當接近1的縮放因數α和相當接近0的偏移值β可被選擇以在該等檢查節點訊息中引起相當小的改變。當不滿意的檢查節點數是相當大時,更小的縮放因數α及/或更大的偏移值β可被選擇以在該等檢查節點訊息中引起相當大的改變。由於一縮放因數α從1遞減以及由於一偏移值β從0遞增,所以增加了改等檢查節點訊息的改變。
作為另一實例,在預定次數的迭代之後可遞增該等縮放因數α和偏移值β。例如可經由遞增0.2調整該等縮放因數α以及例如可經由遞增1調整該等偏移值β。
經由改變該等縮放因數α及/或偏移值β,本發明的LDPC解碼器可能能夠改良只實施固定或沒有縮放或固定或沒有偏移因數的LDPC解碼器的錯誤基數特性。當本發明的一LDPC解碼器面臨一陷阱集時,該解碼器可改變一或多個縮放因數α及/或一或多個偏移值β以嘗試打破該陷阱集,使得該LDPC解碼器有另一機會正確解碼該碼字。
雖然本發明已經被描述關於圖2的該具體非層次LDPC解碼器組態200,但是本發明並不限於此。本發明的各種實施例也可被設想用於使用訊息傳遞的其他LDPC解碼器結構。例如,本發明可被實施用於其他非層次或層次化解碼器結構以及使用訊息傳遞方案而不是一分組串列訊息傳遞方案的解碼器。作為另一實例,可不使用循環移位器實施本發明的LDPC解碼器。在這些實施例中,可經由直接連接或使用實施非循環移位的轉換開關在CNU與VNU之間傳遞該等訊息。
根據各種實施例,可使用檢查節點演算法而不是該最小和演算法實施本發明。在此等實施例中,縮放及/或偏移可能以類似於縮放和偏移邏輯模組346和310的一種方式分別被施加到檢查節點訊息及/或可變節點訊息。進一步,在產生該等檢查節點訊息之前可經由該檢查節點演算法施加縮放及/或偏移,類似於縮放和偏移邏輯模組334。
雖然本發明被描述關於圖1的該具體H矩陣100,但是本發明並不限於此。本發明可被實施用於各種H矩陣,該等矩陣是與圖1的矩陣100同樣大小或不同大小。例如,本發明可被實施用於H矩陣,其中行、分組行(block column)、列、分組列(block row)、層(包含只具有一層的實施)、每個時鐘週期處理的訊息的數目、該子矩陣的大小、該等層的大小及/或該行及/或列漢明權重不同於H矩陣100的數目和大小。此等H矩陣例如可能是循環、準循環、非循環、規則或不規則H矩陣。此外,此等H矩陣可包括除了包含零矩陣的循環行列式以外的子矩陣。注意,VNU、桶式(barrel)移位器及/或CNU的數目可根據該H矩陣的該等特性而有所不同。
應進一步明白,在不偏離在以下請求項中所表達的本發明的範圍下,可由熟習此項技術者在已經描述且說明以便解釋本發明的實質的該等部分的該等細節、材料和配置中做各種改變。例如,該縮放和偏移邏輯模組可被實施在除了圖3中所示的該三個位置以外(例如,除了310、334、346)的位置中,如在多工器320的該大小|Q|輸入或在SMT2轉換器338與最後狀態暫存器336(0),...,336(2)之間。縮放和偏移邏輯模組310還可位於一VNU(或產生可變節點訊息的加法器)的該輸出處,而不是作為CNU 300的一部分,以及縮放和偏移邏輯模組346還可位於一VNU(或產生可變節點訊息的加法器)的該輸入處,而不是作為CNU 300的一部分。作為另一實例,除了使用2的補數格式接收Q訊息和輸出R訊息,CNU 300可以另一格式接收並輸出訊息,如符號大小格式。此外,例如可由該等VNU實施2的補數對符號大小轉換。作為另一實例,本發明的LDPC解碼器可處理除了五位元大小以外的訊息。
雖然在LDPC碼的上下文中已經描述了本發明實施例,但是本發明並不限於此。本發明的實施例可被實施用於可由一圖界定的任何碼,如tornado碼和結構IRA碼,因為圖界定的碼受到陷阱集的影響。
雖然在電路處理的方面已經描述本發明的該等示例性實施例,包含可能實施作為一單一積體電路、一多晶片模組、一單一卡或一多卡電路套裝(pack),但是本發明並不限於此。如熟習此項技術者所明白者,電路元件的各種功能也可被實施作為一軟體程式中的處理模組。此軟體可被用在(例如)一數位信號處理器、微控制器或通用電腦中。
本發明也並不限於接收和處理對數似然比。可設想本發明的各種實施例,其中處理其他軟值(如似然比)或硬位元決定。
在本發明和該等請求項中所使用的該術語「遞增」應理解為包含當一值被遞增時的情況及當該值被遞減時的情況。例如,由一具體縮放因數遞增遞增該縮放因數包含當由該具體縮放因數遞增而遞增該縮放因數時的情況和當由該具體縮放因數遞增而遞減該縮放因數時的情況。
如在本發明和該等請求項中所使用者,儘管在該第一與第二值之間產生中間值,但是一第二值可被視為「基於」一第一值而產生。例如,儘管在該等軟值Ln (0)
的接收與該等檢查節點訊息的產生之間產生檢查節點訊息,但是可變節點訊息可被視為「基於」由該解碼器接收到得軟值Ln (0)
產生。作為另一實例,儘管為了一第二局部迭代,在該等軟值Ln (0)
的接收與該等檢查節點訊息的產生之間產生可變節點訊息和其他檢查節點訊息,但是在該LDPC解碼器的該第二局部迭代期間產生的檢查節點訊息可被視為是「基於」在該第一迭代期間接收到的軟值Ln (0)
。
本發明可以以方法及實踐這些方法之裝置的形式體現。本發明亦可以以有形媒體體現之程式碼的形式體現,如磁記錄媒體、光記錄媒體、固態記憶體、軟碟、CD-ROM、硬碟或其他機器可讀儲存媒體,其中當該程式碼被載入到一機器(如電腦)並且由該機器執行時,該機器變成一實踐本發明的裝置。本發明亦可以以(例如)儲存在一儲存媒體中、載入到一機器中及/或由一機器執行或經由某個傳輸媒體或載體(如電力線或電纜)、經由光纖或經由電磁輻射發送之程式碼的形式體現,其中當該程式碼被載入到一機器(如電腦)並且由該機器執行時,該機器變成一實踐本發明的裝置。當實施於一通用處理器上時,該等程式碼段結合該處理器以提供一與特定邏輯電路之作業類似的獨特裝置。本發明亦可以以一位元流或經由在使用本發明之一種方法及/或一種裝置產生之一磁記錄媒體等中儲存磁場變化的媒體電氣地或光學地傳輸的其他信號值序列體現。
除非另有明確規定,每個數值和範圍應解釋為接近於在該值或範圍的該值前的該字「大約」或「接近於」。
在該等請求項中之圖式數字及/或圖式參考標籤的使用意為識別該請求主題的一或多個可能實施例以便易於解釋該等請求項。這種使用不應視為一定將這些請求項的範圍限制於在相應圖中所示的該等實施例。
應明白,此處所闡述的該等示例性方法的該等步驟並不一定需要以所述順序實施,以及這些方法的該等步驟的該順序應理解為僅僅是示例性的。同樣,在這些方法中可包含額外步驟,以在與本發明的各種實施例一致的方法中可省略或結合某些步驟。
雖然以具有相應標記的一特定順序列舉在以下方法請求項中的該等元件(如果有的話),除非該等請求列舉另有暗示一特定順序用於實施這些元件的某些或全部,這些元件並不一定意為限於以該特定順序實施。
100...奇偶校驗矩陣
200...低密度奇偶校驗解碼器
202...軟值記憶體
204...可變節點單元
206...多工器
208...循環移位器
210...檢查節點單元
212...循環移位器
214...控制器
300...檢查節點單元
302...M1_M2查找器
304...部分狀態記憶體
306...最後狀態處理器
308...R選擇器
310...縮放和偏移邏輯模組
312...2的補數對符號大小轉換器
314...觸發器
316...最小運算器
318...控制信號
320...多工器
322...計數器
324...計數器值
328...符號處理邏輯器
330...部分狀態暫存器
332...符號位元
334...縮放和偏移邏輯模組
336...暫存器
340...比較運算器
342...比較位元
344...多工器
346...縮放和偏移邏輯模組
圖1顯示一奇偶校驗H矩陣的一實施,該奇偶校驗H矩陣可被用於實施一規則的、準循環(QC)低密度奇偶校驗(LDPC)碼;
圖2顯示根據本發明的一實施例的一LDPC解碼器的簡化方塊圖,該LDPC解碼器可被用於解碼使用一H矩陣(如圖1的該H矩陣)編碼的一信號;以及
圖3顯示一檢查節點單元(CNU)的一實施的簡化方塊圖,該檢查節點單元可被用於實施圖2的該LDPC解碼器的每個CNU。
300...檢查節點單元
302...M1_M2查找器
304...部分狀態記憶體
306...最後狀態處理器
308...R選擇器
310...縮放和偏移邏輯模組
312...2的補數對符號大小轉換器
314...觸發器
316...最小運算器
318...控制信號
320...多工器
322...計數器
324...計數器值
328...符號處理邏輯器
330...部分狀態暫存器
332...符號位元
334...縮放和偏移邏輯模組
336...暫存器
340...比較運算器
342...比較位元
344...多工器
346...縮放和偏移邏輯模組
Claims (18)
- 一種包含一用於解碼一錯誤更正編碼碼字以恢復一正確碼字之錯誤更正解碼器之裝置,其中:該解碼器經組態以基於由一上游處理器產生之一原始組原始值產生一第一組訊息,其中:該原始組對應該錯誤更正編碼碼字;以及該原始組中之每個原始值對應於該錯誤更正編碼碼字之一不同位元;以及該解碼器包括:一或多個模組,其經組態以基於一縮放因數和一偏移值將該第一組訊息轉換為縮放和偏移訊息;和一控制器,其經組態以選擇該縮放因數和該偏移值,其中該控制器經組態以(i)選擇一原始縮放因數和一原始偏移值,以及(ii)隨後修飾該原始縮放因數和該原始偏移值之至少其中之一。
- 如請求項1之裝置,其中:該錯誤更正解碼器包括一經組態以產生可變節點訊息之可變節點單元;該第一組訊息是該等可變節點訊息;以及該一或多個模組經組態以基於該縮放因數和該偏移值將該等可變節點訊息轉換為縮放和偏移可變節點訊息。
- 如請求項1之裝置,其中:該錯誤更正解碼器包括一經組態以產生檢查節點訊息之檢查節點單元; 該第一組訊息是該等檢查節點訊息;以及該一或多個模組經組態以基於該縮放因數和該偏移值將該等檢查節點訊息轉換為縮放和偏移檢查節點訊息。
- 如請求項1之裝置,其中:該錯誤更正解碼器實施一最小和演算法;該錯誤更正解碼器包括一經組態以產生該最小和演算法之第一最小和第二最小大小值之檢查節點單元;該第一組訊息是該第一最小和第二最小大小值;以及該一或多個模組經組態以基於該縮放因數和該偏移值將該第一最小和第二最小大小值轉換為縮放和偏移之第一最小和第二最小大小值。
- 如請求項1之裝置,其中:該控制器能夠將該縮放因數設定為1;以及該控制器能夠將該偏移值設定為0。
- 如請求項1之裝置,其中該一或多個模組包括一既實施縮放又實施偏移之縮放和偏移模組。
- 如請求項1之裝置,其中:該解碼器是一低密度奇偶校驗解碼器;以及從該上游處理器接收之該等值是具有一硬決定(hard-decision)位元和一或多個信心值(confidence-value)位元的軟輸出值。
- 如請求項1之裝置,其中在該控制器決定在一預定次數之解碼迭代內該錯誤更正解碼器沒有收斂於該正確碼字之後,該控制器修飾該原始縮放因數和該原始偏移值之 至少其中之一。
- 如請求項1之裝置,其中該控制器經組態以修飾該原始縮放因數和該原始偏移值兩者。
- 如請求項1之裝置,其中該控制器經組態以經由一具體縮放因數遞增而遞增該原始縮放因數來修飾該原始縮放因數。
- 如請求項1之裝置,其中該控制器經組態以經由一具體偏移值遞增而遞增該原始偏移值來修飾該原始偏移值。
- 一種用於解碼一錯誤更正編碼碼字以恢復一正確碼字之方法,該方法包括:(a)選擇一原始縮放因數和一原始偏移值;(b)從一上游處理器接收一原始組原始值,其中:該原始組對應於該錯誤更正編碼碼字;以及該原始組中之每個原始值對應於該錯誤更正編碼碼字之一不同位元;(c)基於該原始組原始值產生一第一組訊息;(d)基於該原始縮放因數和該原始偏移值,將該第一組訊息轉換為縮放和偏移訊息;(e)隨後修飾該原始縮放因數和該原始偏移值之至少其中之一;(f)產生一第二組訊息;以及(g)基於在步驟(e)中修飾之該原始縮放因數和該原始偏移值,將該第二組訊息轉換為縮放和偏移訊息。
- 如請求項12之方法,其中: 步驟(c)包括產生可變節點訊息作為該第一組訊息;以及步驟(d)包括基於該原始縮放因數和該原始偏移值,將該等可變節點訊息轉換為縮放和偏移可變節點訊息。
- 如請求項12之方法,其中:步驟(c)包括產生檢查節點訊息作為該第一組訊息;以及步驟(d)包括基於該原始縮放因數和該原始偏移值,將該等檢查節點訊息轉換為縮放和偏移檢查節點訊息。
- 如請求項12之方法,其中:步驟(c)包括產生一最小和演算法之第一最小和第二最小大小值作為該第一組訊息;以及步驟(d)包括基於該原始縮放因數和該原始偏移值,將該第一最小和第二最小大小值轉換為縮放和偏移之第一最小和第二最小大小值。
- 如請求項12之方法,其中在決定在一預定次數之解碼迭代內該方法沒有收斂於該正確碼字之後,修飾該原始縮放因數和該原始偏移值之至少其中之一。
- 如請求項12之方法,其中:該錯誤更正編碼碼字是一低密度奇偶校驗編碼碼字;以及從該上游處理器接收之該等值是具有一硬決定位元和一或多個信心值位元的軟輸出值。
- 一種用於解碼一錯誤更正編碼碼字以恢復一正確碼字之裝置,該裝置包括:(a)用於選擇一原始縮放因數和一原始偏移值之構 件;(b)用於從一上游處理器接收一原始組原始值之構件,其中:該原始組對應於該錯誤更正編碼碼字;以及該原始組中之每個原始值對應於該錯誤更正編碼碼字之一不同位元;(c)用於基於該原始組原始值產生一第一組訊息之構件;(d)用於基於該原始縮放因數和該原始偏移值將該第一組訊息轉換為縮放和偏移訊息之構件;(e)用於隨後修飾該原始縮放因數和該原始偏移值之至少其中之一之構件;(f)用於產生一第二組訊息之構件;以及(g)用於基於在步驟(e)中修飾之該原始縮放因數和該原始偏移值,將該第二組訊息轉換為縮放和偏移訊息之構件。
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