GB2455274A - Decoding LDPC-coded data - Google Patents

Abstract

A decoder decodes an incoming data signal in accordance with an error correction code. The decoder is operable to perform a plurality of decoding operations to decode the incoming data, each decoding operation using a different representation of a parity check matrix for the error correction code corresponding to a respective different non-binary Tanner graph (5a-5c). The multiple representations of the parity check matrix are possible if the code is formed over an Abelian group. The operations may be performed in sequential order (if the first operation does not produce a suitable convergence) or in parallel (fig.2, not shown). Application to LDPC codes (using e.g. a belief propagation algorithm) but also to, e.g.. turbo and BCH codes.

Description

DECODING APPARATUS AND METHOD

This invention relates to forward error correction coding and decoding schemes for communication systems. The invention has particular, but not exclusive, relevance to decoding codewords formed using non- binary low density parity check (LDPC) codes.

For LDPC codes, in general during encoding a generator matrix G converts a message vector into a code vector by means of matrix multiplication. During decoding a parity check matrix H is used which has the property that matrix multiplication of the code vector by the panty check matrix H results in a null vector. For LDPC codes, the parity check matrix is sparse (i.e. it is largely populated by zeros).

LDPC coding designed over field GF(q) has been shown to approach the Shannon limit for performance when q=2 and the code lengths are very long. It has also been shown that for more moderate code lengths, efficient error decoding can be achieved by increasing q above 2. However, this results in increased decoder complexity.

It is known to use a Belief Propagation (BP) decoder to decode LDPC codes. For LDPC codes with q > 2, if the code is formed over an Abelian group then it is possible to create different binary representations (sometimes called binary images) of the parity check matrix. There is no unique binary representation because any linear transformation of the rows or any permutation of the columns corresponds to the same code.

The decoding using a Belief Propagation algorithm associated with an LDPC code may be represented by a bipartite factor graph (commonly referred to as a Tanner graph) having symbol nodes and check nodes which are interconnected in accordance with the parity check matrix. In effect, messages are iteratively sent from the symbol nodes to the check nodes indicating the believed values at the symbol nodes and a measure of the strength of that belief, and messages are sent from the check nodes to the symbol nodes providing feedback information which is used to re-evaluate the values of the symbol nodes, until the values of the symbol nodes converge.

However, a short cycle in the Tanner graph can prevent the values of the symbol nodes from converging, thereby giving an inconclusive result.

According to an aspect of the present invention, a decoder is provided which is operable to decode in accordance with a plurality of different representations of a parity check matrix, each representation corresponding to a different non-binary Tanner graph. Each representation of the parity check matrix has a different convergence behaviour. In an extreme case, one representation may be able to achieve convergence of an input set of samples where another representation could not. More typically, the speed of convergence will vary between representations.

Different representations of the parity check matrix corresponding to different non-binary Tanner graphs can arise in various different ways. For example, binary transformations of a binary image of the parity check matrix can lead to different non-binary Tanner graphs with the same clustering.

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Alternatively, the same binary image with different clusterings can lead to different non-binary tanner graphs.

The clustering can be irregular in the same code, with clusters of different sizes, that is rectangular p x p2 clusters (with p' > P2).

The decoding operations using respective different representations of the parity check matrix could be performed in series or in parallel, or a combination of series and parallel decoding operations, with an appropriate merging strategy being used to arrive at a final decision.

The invention is applicable to a wide variety of error corrections codes including LDPC codes, turbo codes and block codes such as BCH codes or Reed-Solomon (RS) Codes.

Various exemplary embodiments of the invention will now be described with reference to the attached figures in which: Figure 1 schematically represents a decoding operation in accordance with a first embodiment of the invention; and Figure 2 schematically represents a decoding operation in accordance with a second embodiment of the invention.

The first and second embodiments of the invention utilise LDPC codes which are defined over Abelian groups and a non-binary group decoder, as discussed in "FFT-based BP Decoding of General LDPC Codes over Abelian Groups" by Goupil et al in IEEE Trans. on Commun., vol. 55(4), pp. 644-649, April 2007 (the contents of which is hereby incorporated by reference). In this case, the code has a binary parity check matrix representation, which is not unique since any linear transformation of the rows or any permutation of the columns corresponds to the same code. In particular, in order to avoid changing the code space, only permutations of the columns are allowed whereas any linear transformations (permutations and/or sums) of the rows are allowed.

As discussed in the Goupil et al article, a clustering of a binary matrix representation is then considered to build a non-binary Tanner graph representation of the code. Every adjacent non-overlapping square matrix of size p x p is transformed during the clustering process into a closed function, which is used in the group BP decoder.

A representation of the decoding in accordance with a first embodiment of the invention is shown in Figure 1. As shown, a received data signal is stored in a buffer memory I which is connected with a decoding controller 3. The decoding controller 3 initially initiates a first group BP decoder 5a using a first binary image of the parity check matrix. The first group BP decoder 5a retrieves a copy of the received data signal from the buffer memory 1 and attempts to decode the received data signal. If the solution calculated by the first group BP decoder 5a has converged within a predefined number of iterations of the belief propagation algorithm (in this embodiment one hundred), then that solution is conveyed as a hard decision to the decoding controller 3, which then outputs the solution.

If the solution calculated by the first group BP decoder 5a fails to converge after the predefined number of iterations, a failure message is sent to

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the decoding controller 3. On receiving the failure message, the decoding controller 3 initiates a second group BP decoder 5b using a second binary image of the parity check matrix, the second binary image being different from the first binary image. The second group BP decoder 5b retrieves a copy of the received data signal from the buffer memory I and attempts to decode the received data signal. If the solution calculated by the second group BP decoder 5b has converged within the predefined number of iterations of the belief propagation algorithm, that solution is indicated as a hard decision to the decoding controller 3, which then outputs the solution.

If the solution calculated by the second group BP decoder 5a fails to converge after the predefmed number of iterations, a failure message is sent to the decoding controller 3. On receiving the failure message, the decoding controller 3 initiates a third group BP decoder Sc using a third binary image of the parity check matrix, the third binary image being different from the first and second binary images. The third group BP decoder 5c retrieves a copy of the received data signal from the buffer memory I and attempts to decode the received data signal. If the solution calculated by the third group BP decoder Sc has converged within the predefined number of iterations of the belief propagation algorithm, that solution is indicated as a hard decision to the decoding controller 3, which then outputs the solution.

Accordingly, in effect the first embodiment uses a plurality of group BP decoders 5 in series. For each decoder a decision is made as to whether a codeword has been found. The subsequent decoders in the series are only used if this is not the case.

A second embodiment will now be described with reference to Figure 2 in which, in effect, a plurality of group BP decoders are used in parallel, each group BP decoder using a different binary image of the parity check matrix.

As shown in Figure 2, the received data signal is simultaneously processed by a first group BP decoder 1 la using a first binary image of the parity check matrix, a second group BP decoder 1 lb using a second binary image of the parity check matrix, and a third group BP decoder I Ic using a third binary image of the parity check matrix. The first, second and third binary images are all different.

If a group BP decoder 11 arrives at a convergent solution within a predefined number of iterations of the belief propagation algorithm (in this embodiment one hundred iterations), then that convergent solution is output as a hard decision to a parallel merger 13. If, after the predefined number of iterations, a group BP decoder has not reached a convergent solution, then a error message is sent to the parallel merger 13.

The parallel merger 13 processes the solutions received from the group BP decoders 11, and outputs the most likely solution as the decoder output.

Modifications and Further Embodiments In the first and second embodiments, each group BP decoder outputs its solution as a hard decision', which means that no information is provided as to the level of certainty that each symbol in the solution is correct.

Alternatively, each group BP decoder could output its solution as a soft decision' in which each symbol is associated with a probability value indicative of the confidence the decoder has that the symbol is correct. These probabilities could be used by the decoding controller 3 of the first embodiment or the parallel merger 13 of the second embodiment to improve the reliability of the decoding.

For example, in the first embodiment if the group BP decoders output soft decisions then even if both the first and second group BP decoders do not arrive at convergent solutions, there may be sufficient information in the two soft decisions for the decoding controller 3 to infer the correct solution without requiring processing by the third group BP decoder. Alternatively, in the second embodiment if the group BP decoders output soft decisions then the parallel merger 13 can use all this information when deciding the most likely codeword.

In principle, the information contained in a soft decision output by one group BP decoder could be input to a second group BP decoder to improve decoding performance.

While the use of three group BP decoders, each using different binary images of the parity check matrix, are used in the first and second embodiments, it will be appreciated that any number of group BP decoders in excess of one could be used.

It will be appreciated that instead of performing a simple series of decoding operations (as in the first embodiment) or performing all decoding operations in parallel (as in the second embodiment), a combination of parallel and series decoding operations could be performed.

In each embodiment, the group BP decoders need not be separate hardware modules, but could be implemented as different software routines implemented on the same processor, which could also be used to perform software routines as the decoding controller (for the first embodiment) and the parallel merger (for the second embodiment).

The first and second embodiments discuss decoding in accordance with the LDPC error correction algorithm. However, the present invention could also be employed with other error correction algorithms, even ones which are not normally decoded in an iterative fashion. For example, the invention could be applied to various Turbo codes (duo-binary Turbo codes) or block codes (for example non-sparse BCH codes).

The present invention provides decoder diversity. This covers the process of using two or more parity check matrices which result in different non-binary Tanner graph representations after clustering. The difference can be in the cluster size and/or in the edge locations and/or in the linear functions built from the cluster contents. By using decoder diversity to produce several group decodings of the same code, the difference in convergence behaviour

S

may be utilised to improve decoder performance. The difference in decoder performance could be in terms of different convergent fixed points and/or different convergence speed.

Of course, using several binary images for decoding a input data signal requires more computational effort than a unique decoding step. The complexity increase of performing serial decoding operations may, however, be quite small since a second decoding operation is only performed if the first decoding operation fails to converge. The design of a good group decoder diversity based decoder relies on the following choices: a) The choice of the number Nd of binary images. A good choice would be to ensure that the decodings of the different images provide sufficient "diversity" in that the convergence points differ the most for a constant average performance. In this scheme, it is desirable that the average performance of different decoders is approximately the same.

b) The choice of merging strategy that is linked to the performance/complexity trade-off.

The embodiment described with reference to the drawings comprises computer apparatus and involves processes performed in the computer apparatus. The invention also extends to computer programs, particularly computer programs on or in a carrier, adapted for putting the invention into practice. The program may be in the form of source code, object code, a code intermediate to source code and object code such as in partially compiled form, or in any other form suitable for using in the implementation of the processes according to the invention.

The carrier may be any entity or device capable of carrying the program. For example, the carrier may comprise a storage medium, such as a ROM, for example a CD-ROM or a semiconductor ROM, or a magnetic recording medium, for example a floppy disc or a hard disc, or an optical recording medium. Further, the carrier may be a transmissible carrier such as an electronic or optical signal which may be conveyed via electrical or optical cable or by radio or other means.

The carrier may be an integrated circuit in which the program is embedded, the integrated circuit being adapted for performing, or for use in the performance of, the relevant processes.

Although in the described embodiment the invention is implemented by software, it will be appreciated that alternatively the invention could be implemented by hardware devices or a combination of hardware devices and software. DECODING APPARATUS AND METHOD

This invention relates to forward error correction coding and decoding schemes for communication systems. The invention has particular, but not exclusive, relevance to decoding codewords formed using non- binary low density parity check (LDPC) codes.

For LDPC codes, in general during encoding a generator matrix G converts a message vector into a code vector by means of matrix multiplication. During decoding a parity check matrix H is used which has the property that matrix multiplication of the code vector by the panty check matrix H results in a null vector. For LDPC codes, the parity check matrix is sparse (i.e. it is largely populated by zeros).

LDPC coding designed over field GF(q) has been shown to approach the Shannon limit for performance when q=2 and the code lengths are very long. It has also been shown that for more moderate code lengths, efficient error decoding can be achieved by increasing q above 2. However, this results in increased decoder complexity.

It is known to use a Belief Propagation (BP) decoder to decode LDPC codes. For LDPC codes with q > 2, if the code is formed over an Abelian group then it is possible to create different binary representations (sometimes called binary images) of the parity check matrix. There is no unique binary representation because any linear transformation of the rows or any permutation of the columns corresponds to the same code.

The decoding using a Belief Propagation algorithm associated with an LDPC code may be represented by a bipartite factor graph (commonly referred to as a Tanner graph) having symbol nodes and check nodes which are interconnected in accordance with the parity check matrix. In effect, messages are iteratively sent from the symbol nodes to the check nodes indicating the believed values at the symbol nodes and a measure of the strength of that belief, and messages are sent from the check nodes to the symbol nodes providing feedback information which is used to re-evaluate the values of the symbol nodes, until the values of the symbol nodes converge.

However, a short cycle in the Tanner graph can prevent the values of the symbol nodes from converging, thereby giving an inconclusive result.

According to an aspect of the present invention, a decoder is provided which is operable to decode in accordance with a plurality of different representations of a parity check matrix, each representation corresponding to a different non-binary Tanner graph. Each representation of the parity check matrix has a different convergence behaviour. In an extreme case, one representation may be able to achieve convergence of an input set of samples where another representation could not. More typically, the speed of convergence will vary between representations.

Different representations of the parity check matrix corresponding to different non-binary Tanner graphs can arise in various different ways. For example, binary transformations of a binary image of the parity check matrix can lead to different non-binary Tanner graphs with the same clustering.

S

Alternatively, the same binary image with different clusterings can lead to different non-binary tanner graphs.

The clustering can be irregular in the same code, with clusters of different sizes, that is rectangular p x p2 clusters (with p' > P2).

The decoding operations using respective different representations of the parity check matrix could be performed in series or in parallel, or a combination of series and parallel decoding operations, with an appropriate merging strategy being used to arrive at a final decision.

The invention is applicable to a wide variety of error corrections codes including LDPC codes, turbo codes and block codes such as BCH codes or Reed-Solomon (RS) Codes.

Various exemplary embodiments of the invention will now be described with reference to the attached figures in which: Figure 1 schematically represents a decoding operation in accordance with a first embodiment of the invention; and Figure 2 schematically represents a decoding operation in accordance with a second embodiment of the invention.

The first and second embodiments of the invention utilise LDPC codes which are defined over Abelian groups and a non-binary group decoder, as discussed in "FFT-based BP Decoding of General LDPC Codes over Abelian Groups" by Goupil et al in IEEE Trans. on Commun., vol. 55(4), pp. 644-649, April 2007 (the contents of which is hereby incorporated by reference). In this case, the code has a binary parity check matrix representation, which is not unique since any linear transformation of the rows or any permutation of the columns corresponds to the same code. In particular, in order to avoid changing the code space, only permutations of the columns are allowed whereas any linear transformations (permutations and/or sums) of the rows are allowed.

As discussed in the Goupil et al article, a clustering of a binary matrix representation is then considered to build a non-binary Tanner graph representation of the code. Every adjacent non-overlapping square matrix of size p x p is transformed during the clustering process into a closed function, which is used in the group BP decoder.

A representation of the decoding in accordance with a first embodiment of the invention is shown in Figure 1. As shown, a received data signal is stored in a buffer memory I which is connected with a decoding controller 3. The decoding controller 3 initially initiates a first group BP decoder 5a using a first binary image of the parity check matrix. The first group BP decoder 5a retrieves a copy of the received data signal from the buffer memory 1 and attempts to decode the received data signal. If the solution calculated by the first group BP decoder 5a has converged within a predefined number of iterations of the belief propagation algorithm (in this embodiment one hundred), then that solution is conveyed as a hard decision to the decoding controller 3, which then outputs the solution.

If the solution calculated by the first group BP decoder 5a fails to converge after the predefined number of iterations, a failure message is sent to

S

the decoding controller 3. On receiving the failure message, the decoding controller 3 initiates a second group BP decoder 5b using a second binary image of the parity check matrix, the second binary image being different from the first binary image. The second group BP decoder 5b retrieves a copy of the received data signal from the buffer memory I and attempts to decode the received data signal. If the solution calculated by the second group BP decoder 5b has converged within the predefined number of iterations of the belief propagation algorithm, that solution is indicated as a hard decision to the decoding controller 3, which then outputs the solution.

If the solution calculated by the second group BP decoder 5a fails to converge after the predefmed number of iterations, a failure message is sent to the decoding controller 3. On receiving the failure message, the decoding controller 3 initiates a third group BP decoder Sc using a third binary image of the parity check matrix, the third binary image being different from the first and second binary images. The third group BP decoder 5c retrieves a copy of the received data signal from the buffer memory I and attempts to decode the received data signal. If the solution calculated by the third group BP decoder Sc has converged within the predefined number of iterations of the belief propagation algorithm, that solution is indicated as a hard decision to the decoding controller 3, which then outputs the solution.

Accordingly, in effect the first embodiment uses a plurality of group BP decoders 5 in series. For each decoder a decision is made as to whether a codeword has been found. The subsequent decoders in the series are only used if this is not the case.

A second embodiment will now be described with reference to Figure 2 in which, in effect, a plurality of group BP decoders are used in parallel, each group BP decoder using a different binary image of the parity check matrix.

As shown in Figure 2, the received data signal is simultaneously processed by a first group BP decoder 1 la using a first binary image of the parity check matrix, a second group BP decoder 1 lb using a second binary image of the parity check matrix, and a third group BP decoder I Ic using a third binary image of the parity check matrix. The first, second and third binary images are all different.

If a group BP decoder 11 arrives at a convergent solution within a predefined number of iterations of the belief propagation algorithm (in this embodiment one hundred iterations), then that convergent solution is output as a hard decision to a parallel merger 13. If, after the predefined number of iterations, a group BP decoder has not reached a convergent solution, then a error message is sent to the parallel merger 13.

The parallel merger 13 processes the solutions received from the group BP decoders 11, and outputs the most likely solution as the decoder output.

Modifications and Further Embodiments In the first and second embodiments, each group BP decoder outputs its solution as a hard decision', which means that no information is provided as to the level of certainty that each symbol in the solution is correct.

Alternatively, each group BP decoder could output its solution as a soft decision' in which each symbol is associated with a probability value indicative of the confidence the decoder has that the symbol is correct. These probabilities could be used by the decoding controller 3 of the first embodiment or the parallel merger 13 of the second embodiment to improve the reliability of the decoding.

For example, in the first embodiment if the group BP decoders output soft decisions then even if both the first and second group BP decoders do not arrive at convergent solutions, there may be sufficient information in the two soft decisions for the decoding controller 3 to infer the correct solution without requiring processing by the third group BP decoder. Alternatively, in the second embodiment if the group BP decoders output soft decisions then the parallel merger 13 can use all this information when deciding the most likely codeword.

In principle, the information contained in a soft decision output by one group BP decoder could be input to a second group BP decoder to improve decoding performance.

While the use of three group BP decoders, each using different binary images of the parity check matrix, are used in the first and second embodiments, it will be appreciated that any number of group BP decoders in excess of one could be used.

It will be appreciated that instead of performing a simple series of decoding operations (as in the first embodiment) or performing all decoding operations in parallel (as in the second embodiment), a combination of parallel and series decoding operations could be performed.

In each embodiment, the group BP decoders need not be separate hardware modules, but could be implemented as different software routines implemented on the same processor, which could also be used to perform software routines as the decoding controller (for the first embodiment) and the parallel merger (for the second embodiment).

The first and second embodiments discuss decoding in accordance with the LDPC error correction algorithm. However, the present invention could also be employed with other error correction algorithms, even ones which are not normally decoded in an iterative fashion. For example, the invention could be applied to various Turbo codes (duo-binary Turbo codes) or block codes (for example non-sparse BCH codes).

The present invention provides decoder diversity. This covers the process of using two or more parity check matrices which result in different non-binary Tanner graph representations after clustering. The difference can be in the cluster size and/or in the edge locations and/or in the linear functions built from the cluster contents. By using decoder diversity to produce several group decodings of the same code, the difference in convergence behaviour

S

may be utilised to improve decoder performance. The difference in decoder performance could be in terms of different convergent fixed points and/or different convergence speed.

Of course, using several binary images for decoding a input data signal requires more computational effort than a unique decoding step. The complexity increase of performing serial decoding operations may, however, be quite small since a second decoding operation is only performed if the first decoding operation fails to converge. The design of a good group decoder diversity based decoder relies on the following choices: a) The choice of the number Nd of binary images. A good choice would be to ensure that the decodings of the different images provide sufficient "diversity" in that the convergence points differ the most for a constant average performance. In this scheme, it is desirable that the average performance of different decoders is approximately the same.

b) The choice of merging strategy that is linked to the performance/complexity trade-off.

The embodiment described with reference to the drawings comprises computer apparatus and involves processes performed in the computer apparatus. The invention also extends to computer programs, particularly computer programs on or in a carrier, adapted for putting the invention into practice. The program may be in the form of source code, object code, a code intermediate to source code and object code such as in partially compiled form, or in any other form suitable for using in the implementation of the processes according to the invention.

The carrier may be any entity or device capable of carrying the program. For example, the carrier may comprise a storage medium, such as a ROM, for example a CD-ROM or a semiconductor ROM, or a magnetic recording medium, for example a floppy disc or a hard disc, or an optical recording medium. Further, the carrier may be a transmissible carrier such as an electronic or optical signal which may be conveyed via electrical or optical cable or by radio or other means.

The carrier may be an integrated circuit in which the program is embedded, the integrated circuit being adapted for performing, or for use in the performance of, the relevant processes.

Although in the described embodiment the invention is implemented by software, it will be appreciated that alternatively the invention could be implemented by hardware devices or a combination of hardware devices and software.

Claims (9)

O CLAIMS

1. A decoder which is operable to decode an incoming data signal in accordance with an error correction code, wherein the decoder is operable to perform a plurality of decoding operations to decode incoming data, each decoding operation using a different representation of a parity check matrix for the error correction code corresponding to a respective different non-binary Tanner graph.

2. A decoder according to claim 1, wherein the decoder is operable to decode the incoming data signal using different representations of the parity check matrix in parallel.

3. A decoder according to claim 1 or 2, wherein the decoder is operable to process the incoming data signal using a first representation of the parity check matrix, and if decoding using the first representation is unsuccessful to process the incoming data signal using a second representation of the parity check matrix which is different from the first representation of the parity check matrix.

4. A decoder according to any preceding claim, wherein the decoder is a belief propagation decoder operable to perform multiple iterations of a belief propagation algorithm.

5. A decoder according to claim 4, wherein the decoder is a group non-binary belief propagation decoder.

6. A decoder according to claim 4 or 5, wherein the decoder is arranged to consider decoding unsuccessful if convergence has not been reached after a defined number of iterations of the belief propagation algorithm.

7. A decoder according to any preceding claim, wherein the output of a decoding operation is given in a hard decision.

8. A decoder according to any of claims 1 to 7, wherein the output of a decoding operation is given in a soft decision.

9. A decoder according to claim 8, wherein the decoder is operable to process a plurality of soft decisions provided by respective different processing operations to determine the output code.

9. A decoder according to claim 8, wherein the decoder is operable to process a plurality of soft decisions provided by respective different processing operations to determine the output code.

O

1. A decoder which is operable to decode an incoming data signal in accordance with an error correction code, wherein the decoder is operable to perform a plurality of decoding operations to decode incoming data, each decoding operation using a different representation of a parity check matrix for the error correction code corresponding to a respective different non-binary Tanner graph.

2. A decoder according to claim 1, wherein the decoder is operable to decode the incoming data signal using different representations of the parity check matrix in parallel.

3. A decoder according to claim 1 or 2, wherein the decoder is operable to process the incoming data signal using a first representation of the parity check matrix, and if decoding using the first representation is unsuccessful to process the incoming data signal using a second representation of the parity check matrix which is different from the first representation of the parity check matrix.

4. A decoder according to any preceding claim, wherein the decoder is a belief propagation decoder operable to perform multiple iterations of a belief propagation algorithm.

5. A decoder according to claim 4, wherein the decoder is a group non-binary belief propagation decoder.

6. A decoder according to claim 4 or 5, wherein the decoder is arranged to consider decoding unsuccessful if convergence has not been reached after a defined number of iterations of the belief propagation algorithm.

7. A decoder according to any preceding claim, wherein the output of a decoding operation is given in a hard decision.

8. A decoder according to any of claims 1 to 7, wherein the output of a decoding operation is given in a soft decision.